[PATCH v1] board: toradex: add aquila am69 support
Francesco Dolcini
francesco at dolcini.it
Fri Nov 7 09:24:26 CET 2025
From: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>
Add initial support for the Toradex Aquila AM69 module.
The Aquila AM69 SoM is based on the TI AM69 SoC from the Jacinto 7
family and is designed for high-end embedded computing, featuring up to
32GB of LPDDR4 and 256GB eMMC storage, extensive multimedia support (3x
Quad CSI, 2x Quad DSI, DisplayPort, 5x Audio I2S/TDM), six Ethernet
interfaces (1x 1G, 4x 2.5G SGMII, 1x 10G), USB 3.2 Host/DRD support, and
a Wi-Fi 7/BT 5.3 module, alongside an RX8130 RTC, I2C EEPROM and
Temperature Sensor, and optional TPM 2.0 module.
Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>
Co-developed-by: Parth Pancholi <parth.pancholi at toradex.com>
Signed-off-by: Parth Pancholi <parth.pancholi at toradex.com>
Co-developed-by: Franz Schnyder <franz.schnyder at toradex.com>
Signed-off-by: Franz Schnyder <franz.schnyder at toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini at toradex.com>
---
Full alignment will be completed once the board device tree is in
mainline Linux [1], at which point we'll move to OF_UPSTREAM.
[1] https://lore.kernel.org/all/20251104144915.60445-1-francesco@dolcini.it/
---
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi | 157 +
arch/arm/dts/k3-am69-aquila-dev.dts | 576 ++
arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi | 8786 ++++++++++++++++++
arch/arm/dts/k3-am69-aquila.dtsi | 1837 ++++
arch/arm/dts/k3-am69-r5-aquila-dev.dts | 19 +
arch/arm/mach-k3/j784s4/Kconfig | 18 +
board/toradex/aquila-am69/Kconfig | 59 +
board/toradex/aquila-am69/MAINTAINERS | 13 +
board/toradex/aquila-am69/Makefile | 9 +
board/toradex/aquila-am69/aquila-am69.c | 208 +
board/toradex/aquila-am69/aquila-am69.env | 41 +
board/toradex/aquila-am69/aquila_ddrs_16GB.c | 61 +
board/toradex/aquila-am69/aquila_ddrs_16GB.h | 11 +
board/toradex/aquila-am69/aquila_ddrs_8GB.c | 103 +
board/toradex/aquila-am69/aquila_ddrs_8GB.h | 11 +
board/toradex/aquila-am69/board-cfg.yaml | 37 +
board/toradex/aquila-am69/ddrs_patch.c | 94 +
board/toradex/aquila-am69/ddrs_patch.h | 38 +
board/toradex/aquila-am69/pm-cfg.yaml | 13 +
board/toradex/aquila-am69/rm-cfg.yaml | 3057 ++++++
board/toradex/aquila-am69/sec-cfg.yaml | 380 +
board/toradex/aquila-am69/tifs-rm-cfg.yaml | 2655 ++++++
configs/aquila-am69_a72_defconfig | 179 +
configs/aquila-am69_r5_defconfig | 134 +
doc/board/toradex/aquila-am69.rst | 221 +
doc/board/toradex/index.rst | 1 +
include/configs/aquila-am69.h | 15 +
28 files changed, 18736 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-am69-aquila-dev.dts
create mode 100644 arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi
create mode 100644 arch/arm/dts/k3-am69-aquila.dtsi
create mode 100644 arch/arm/dts/k3-am69-r5-aquila-dev.dts
create mode 100644 board/toradex/aquila-am69/Kconfig
create mode 100644 board/toradex/aquila-am69/MAINTAINERS
create mode 100644 board/toradex/aquila-am69/Makefile
create mode 100644 board/toradex/aquila-am69/aquila-am69.c
create mode 100644 board/toradex/aquila-am69/aquila-am69.env
create mode 100644 board/toradex/aquila-am69/aquila_ddrs_16GB.c
create mode 100644 board/toradex/aquila-am69/aquila_ddrs_16GB.h
create mode 100644 board/toradex/aquila-am69/aquila_ddrs_8GB.c
create mode 100644 board/toradex/aquila-am69/aquila_ddrs_8GB.h
create mode 100644 board/toradex/aquila-am69/board-cfg.yaml
create mode 100644 board/toradex/aquila-am69/ddrs_patch.c
create mode 100644 board/toradex/aquila-am69/ddrs_patch.h
create mode 100644 board/toradex/aquila-am69/pm-cfg.yaml
create mode 100644 board/toradex/aquila-am69/rm-cfg.yaml
create mode 100644 board/toradex/aquila-am69/sec-cfg.yaml
create mode 100644 board/toradex/aquila-am69/tifs-rm-cfg.yaml
create mode 100644 configs/aquila-am69_a72_defconfig
create mode 100644 configs/aquila-am69_r5_defconfig
create mode 100644 doc/board/toradex/aquila-am69.rst
create mode 100644 include/configs/aquila-am69.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 865ceb65f9a2..6d6dcbac8dbc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1084,7 +1084,9 @@ dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
-dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
+dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-aquila-dev.dtb \
+ k3-am69-r5-aquila-dev.dtb \
+ k3-am69-r5-sk.dtb \
k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb \
diff --git a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
new file mode 100644
index 000000000000..59948b9d1f4b
--- /dev/null
+++ b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#define SPL_BOARD_DTB "spl/dts/k3-am69-aquila-dev.dtb"
+#define BOARD_DESCRIPTION "k3-am69-aquila"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 Aquila board"
+
+#include "k3-j784s4-binman.dtsi"
+
+#if defined(CONFIG_CPU_V7R)
+
+&binman {
+ tiboot3-am69-hs {
+ insert-template = <&tiboot3_j784s4_hs>;
+ filename = "tiboot3-am69-hs-aquila.bin";
+ };
+
+ tiboot3-am69-hs-fs {
+ insert-template = <&tiboot3_j784s4_hs_fs>;
+ filename = "tiboot3-am69-hs-fs-aquila.bin";
+ symlink = "tiboot3.bin";
+ };
+};
+
+&ti_fs_enc {
+ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
+};
+
+&ti_fs_enc_fs {
+ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+ filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+ tispl {
+ insert-template = <&ti_spl>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
+ };
+
+ u-boot {
+ insert-template = <&u_boot>;
+ };
+
+ tispl-unsigned {
+ insert-template = <&ti_spl_unsigned>;
+
+ fit {
+ images {
+ dm {
+ ti-dm {
+ filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+ };
+ };
+ };
+ };
+ };
+
+ u-boot-unsigned {
+ insert-template = <&u_boot_unsigned>;
+ };
+};
+
+#endif
+
+/ {
+ memory at 80000000 {
+ bootph-all;
+ };
+
+ sysinfo {
+ compatible = "toradex,sysinfo";
+ };
+};
+
+&main_pmx0 {
+ bootph-pre-ram;
+};
+
+&main_sdhci0 {
+ bootph-pre-ram;
+};
+
+&main_uart8 {
+ bootph-pre-ram;
+};
+
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ bootph-pre-ram;
+};
+
+&pinctrl_main_uart8 {
+ bootph-pre-ram;
+};
+
+&pinctrl_wkup_i2c0 {
+ bootph-pre-ram;
+};
+
+&pmic_tps6594 {
+ bootph-pre-ram;
+ regulators {
+ bootph-pre-ram;
+ };
+};
+
+&tps62873a {
+ bootph-pre-ram;
+};
+
+&usb0 {
+ /delete-property/ phys;
+ /delete-property/ phy-names;
+ dr_mode = "peripheral";
+ maximum-speed = "high-speed";
+ bootph-pre-ram;
+};
+
+&usbss0 {
+ ti,usb2-only;
+ bootph-pre-ram;
+};
+
+&wkup_gpio0 {
+ bootph-pre-ram;
+};
+
+&wkup_i2c0 {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/k3-am69-aquila-dev.dts b/arch/arm/dts/k3-am69-aquila-dev.dts
new file mode 100644
index 000000000000..c7ce804eac70
--- /dev/null
+++ b/arch/arm/dts/k3-am69-aquila-dev.dts
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
+ * https://www.toradex.com/products/carrier-board/aquila-development-board-kit
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include "k3-am69-aquila.dtsi"
+
+/ {
+ model = "Toradex Aquila AM69 on Aquila Development Board";
+ compatible = "toradex,aquila-am69-dev",
+ "toradex,aquila-am69",
+ "ti,j784s4";
+
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ reg_1v8_sw: regulator-1v8-sw {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "Carrier_1V8";
+ };
+
+ reg_3v3_dp: regulator-3v3-dp {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_21_dp>;
+ /* Aquila GPIO_21_DP (AQUILA B57) */
+ gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "DP_3V3";
+ startup-delay-us = <10000>;
+ };
+
+ dp0-connector {
+ compatible = "dp-connector";
+ dp-pwr-supply = <®_3v3_dp>;
+ label = "Display Port";
+ type = "full-size";
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,name = "aquila-wm8904";
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "Microphone Jack", "MICBIAS",
+ "IN1L", "Microphone Jack",
+ "IN1R", "Digital Mic";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Microphone", "Digital Mic",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8904_1a>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp4>;
+ };
+ };
+};
+
+/* Aquila CTRL_PWR_BTN_MICO# */
+&aquila_key_power {
+ status = "okay";
+};
+
+/* Aquila CTRL_WAKE1_MICO# */
+&aquila_key_wake {
+ status = "okay";
+};
+
+/* On-module ETH_1 MDIO */
+&davinci_mdio {
+ status = "okay";
+};
+
+&dp0_ports {
+ port at 4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp0_connector_in>;
+ };
+ };
+};
+
+&dss {
+ status = "okay";
+};
+
+&main0_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device = <&fan 1 1>;
+ trip = <&main0_alert0>;
+ };
+
+ map1 {
+ cooling-device = <&fan 2 2>;
+ trip = <&main0_alert1>;
+ };
+ };
+};
+
+&main1_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device = <&fan 1 1>;
+ trip = <&main1_alert0>;
+ };
+
+ map1 {
+ cooling-device = <&fan 2 2>;
+ trip = <&main1_alert1>;
+ };
+ };
+};
+
+&main2_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device = <&fan 1 1>;
+ trip = <&main2_alert0>;
+ };
+
+ map1 {
+ cooling-device = <&fan 2 2>;
+ trip = <&main2_alert1>;
+ };
+ };
+};
+
+&main3_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device = <&fan 1 1>;
+ trip = <&main3_alert0>;
+ };
+
+ map1 {
+ cooling-device = <&fan 2 2>;
+ trip = <&main3_alert1>;
+ };
+ };
+};
+
+&main4_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device = <&fan 1 1>;
+ trip = <&main4_alert0>;
+ };
+
+ map1 {
+ cooling-device = <&fan 2 2>;
+ trip = <&main4_alert1>;
+ };
+ };
+};
+
+/* Aquila ETH_2 */
+&main_cpsw0 {
+ status = "okay";
+};
+
+/* Aquila ETH_2 SGMII PHY */
+&main_cpsw0_port8 {
+ phy-handle = <&cpsw0_port8_phy4>;
+ status = "okay";
+};
+
+/* Aquila ETH_2_XGMII_MDIO */
+&main_cpsw0_mdio {
+ status = "okay";
+
+ cpsw0_port8_phy4: ethernet-phy at 4 {
+ reg = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth2_int>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+/* Aquila PWM_1 */
+&main_ehrpwm0 {
+ status = "okay";
+};
+
+/* Aquila PWM_4_DP */
+&main_ehrpwm2 {
+ status = "okay";
+};
+
+/* Aquila PWM_2 */
+&main_ehrpwm1 {
+ status = "okay";
+};
+
+/* Aquila PWM_3_DSI */
+&main_ehrpwm5 {
+ status = "okay";
+};
+
+&main_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_01>, /* Aquila GPIO_01 */
+ <&pinctrl_gpio_02>, /* Aquila GPIO_02 */
+ <&pinctrl_gpio_03>; /* Aquila GPIO_03 */
+};
+
+/* Aquila I2C_3_DSI1 */
+&main_i2c0 {
+ status = "okay";
+
+ i2c-mux at 70 {
+ compatible = "nxp,pca9543";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* I2C on DSI Connector Pin #4 and #6 */
+ i2c_dsi_0: i2c at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* I2C on DSI Connector Pin #52 and #54 */
+ i2c_dsi_1: i2c at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+/* Aquila I2C_4_CSI1 */
+&main_i2c1 {
+ status = "okay";
+};
+
+/* Aquila I2C_5_CSI2 */
+&main_i2c2 {
+ status = "okay";
+};
+
+/* Aquila I2C_6 */
+&main_i2c5 {
+ status = "okay";
+};
+
+/* Aquila CAN_1 */
+&main_mcan10 {
+ status = "okay";
+};
+
+/* Aquila CAN_3 */
+&main_mcan13 {
+ status = "okay";
+};
+
+/* Aquila SD_1 */
+&main_sdhci1 {
+ status = "okay";
+};
+
+/* Aquila SPI_2 */
+&main_spi0 {
+ status = "okay";
+};
+
+/* Aquila SPI_1 */
+&main_spi2 {
+ status = "okay";
+};
+
+/* Aquila UART_1 */
+&main_uart4 {
+ status = "okay";
+};
+
+/* Aquila UART_3, used as the Linux console */
+&main_uart8 {
+ status = "okay";
+};
+
+/* Aquila I2S_1 */
+&mcasp4 {
+ status = "okay";
+};
+
+&mcu_cpsw {
+ status = "okay";
+};
+
+/* On-module ETH_1 RGMII */
+&mcu_cpsw_port1 {
+ status = "okay";
+};
+
+/* Aquila I2C_1 */
+&mcu_i2c0 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ fan_controller: fan at 18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ #pwm-cells = <2>;
+
+ fan: fan {
+ cooling-levels = <102 179 255>;
+ #cooling-cells = <2>;
+ pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
+ };
+ };
+
+ wm8904_1a: audio-codec at 1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audio_extrefclk1>;
+ #sound-dai-cells = <0>;
+ clocks = <&audio_refclk1>;
+ clock-names = "mclk";
+ AVDD-supply = <®_1v8_sw>;
+ CPVDD-supply = <®_1v8_sw>;
+ DBVDD-supply = <®_1v8_sw>;
+ DCVDD-supply = <®_1v8_sw>;
+ MICVDD-supply = <®_1v8_sw>;
+
+ wlf,drc-cfg-names = "default", "peaklimiter";
+ /*
+ * Config registers per name, respectively:
+ * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
+ * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
+ */
+ wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x0408>;
+
+ /* GPIO1 = DMIC_CLK, don't touch others */
+ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+
+ wlf,in1r-as-dmicdat2;
+ };
+
+ /* Current measurement into module VCC */
+ hwmon at 41 {
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+
+ temperature-sensor at 4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ /* USB-C OTG (TCPC USB PD PHY) */
+ tcpc at 52 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x52>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_int>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C OTG";
+ power-role = "dual";
+ try-power-role = "sink";
+ self-powered;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <1000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ usb_1_con_hs: endpoint {
+ remote-endpoint = <&usb0_hs>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ usb_1_con_ss: endpoint {
+ remote-endpoint = <&usb0_ss_mux>;
+ };
+ };
+ };
+ };
+ };
+
+ carrier_eeprom: eeprom at 57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Aquila I2C_2 */
+&mcu_i2c1 {
+ status = "okay";
+};
+
+/* Aquila CAN_2 */
+&mcu_mcan0 {
+ status = "okay";
+};
+
+/* Aquila CAN_4 */
+&mcu_mcan1 {
+ status = "okay";
+};
+
+/* Aquila UART_4 */
+&mcu_uart0 {
+ status = "okay";
+};
+
+&mhdp {
+ status = "okay";
+};
+
+/* Aquila QSPI_1 */
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_ospi0_4bit>, <&pinctrl_mcu_ospi0_cs0>;
+ status = "okay";
+
+ flash at 0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ spi-max-frequency = <66000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ cdns,read-delay = <0>;
+ cdns,tchsh-ns = <3>;
+ cdns,tsd2d-ns = <10>;
+ cdns,tshsl-ns = <30>;
+ cdns,tslch-ns = <8>;
+ };
+};
+
+/* Aquila PCIE_1 */
+&pcie0_rc {
+ status = "okay";
+};
+
+/* Aquila PCIE_2 */
+&pcie1_rc {
+ status = "okay";
+};
+
+&serdes2 {
+ status = "okay";
+};
+
+&serdes4 {
+ status = "okay";
+};
+
+&serdes_wiz2 {
+ status = "okay";
+};
+
+&serdes_wiz4 {
+ status = "okay";
+};
+
+/* Aquila ADC_[1-4] */
+&tscadc0 {
+ status = "okay";
+};
+
+&usbss0 {
+ status = "okay";
+};
+
+&usb0ss_mux {
+ status = "okay";
+
+ port {
+ usb0_ss_mux: endpoint {
+ remote-endpoint = <&usb_1_con_ss>;
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+
+ port {
+ usb0_hs: endpoint {
+ remote-endpoint = <&usb_1_con_hs>;
+ };
+ };
+};
+
+&wkup0_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device = <&fan 1 1>;
+ trip = <&wkup0_alert0>;
+ };
+
+ map1 {
+ cooling-device = <&fan 2 2>;
+ trip = <&wkup0_alert1>;
+ };
+ };
+};
+
+&wkup1_thermal {
+ cooling-maps {
+ map0 {
+ cooling-device = <&fan 1 1>;
+ trip = <&wkup1_alert0>;
+ };
+
+ map1 {
+ cooling-device = <&fan 2 2>;
+ trip = <&wkup1_alert1>;
+ };
+ };
+};
+
+&wkup_gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_04>, /* Aquila GPIO_04 */
+ <&pinctrl_gpio_05>, /* Aquila GPIO_05 */
+ <&pinctrl_gpio_06>, /* Aquila GPIO_06 */
+ <&pinctrl_gpio_07>, /* Aquila GPIO_07 */
+ <&pinctrl_gpio_08>; /* Aquila GPIO_08 */
+};
+
+/* Aquila UART_2, through RS485 transceiver */
+&wkup_uart0 {
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi b/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi
new file mode 100644
index 000000000000..adc34d3fef7a
--- /dev/null
+++ b/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi
@@ -0,0 +1,8786 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the following tool revisions:
+ * - SysConfig: Revision 1.25.0+4268
+ * - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
+ * This file was generated on Wed Nov 05 2025 15:15:21 GMT+0100 (Central European Standard Time)
+ *
+ * Multi DDR Configuration (table based on register configuration tool inputs):
+ * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE |
+ * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | 0 | 8 GB | 8 GB |
+ * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | 1 | 8 GB | 8 GB |
+ * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | 2 | 8 GB | 8 GB |
+ * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
+ * | 3 | 8 GB | 8 GB |
+ * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
+*/
+
+#define DDRSS_PLL_FHS_CNT 5
+#define DDRSS1_PLL_FHS_CNT 5
+#define DDRSS2_PLL_FHS_CNT 5
+#define DDRSS3_PLL_FHS_CNT 5
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 1066500000
+#define DDRSS_PLL_FREQUENCY_2 1066500000
+
+#define MULTI_DDR_CFG_INTRLV_GRAN 0
+#define MULTI_DDR_CFG_INTRLV_SIZE 12
+#define MULTI_DDR_CFG_ECC_ENABLE 0
+#define MULTI_DDR_CFG_HYBRID_SELECT 24
+#define MULTI_DDR_CFG_EMIFS_ACTIVE 15
+
+#define DDR0_CTL_NODE_STAT okay
+#define DDR1_CTL_NODE_STAT okay
+#define DDR2_CTL_NODE_STAT okay
+#define DDR3_CTL_NODE_STAT okay
+
+#define DDR_REG0_SIZE_MSB 0x00000000
+#define DDR_REG0_SIZE_LSB 0x80000000
+#define DDR_REG1_SIZE_MSB 0x00000007
+#define DDR_REG1_SIZE_LSB 0x80000000
+
+
+#define DDRSS0_CTL_00_DATA 0x00000B00
+#define DDRSS0_CTL_01_DATA 0x00000000
+#define DDRSS0_CTL_02_DATA 0x00000000
+#define DDRSS0_CTL_03_DATA 0x00000000
+#define DDRSS0_CTL_04_DATA 0x00000000
+#define DDRSS0_CTL_05_DATA 0x00000000
+#define DDRSS0_CTL_06_DATA 0x00000000
+#define DDRSS0_CTL_07_DATA 0x00002AF8
+#define DDRSS0_CTL_08_DATA 0x0001ADAF
+#define DDRSS0_CTL_09_DATA 0x00000005
+#define DDRSS0_CTL_10_DATA 0x0000006E
+#define DDRSS0_CTL_11_DATA 0x000681C8
+#define DDRSS0_CTL_12_DATA 0x004111C9
+#define DDRSS0_CTL_13_DATA 0x00000005
+#define DDRSS0_CTL_14_DATA 0x000010A9
+#define DDRSS0_CTL_15_DATA 0x000681C8
+#define DDRSS0_CTL_16_DATA 0x004111C9
+#define DDRSS0_CTL_17_DATA 0x00000005
+#define DDRSS0_CTL_18_DATA 0x000010A9
+#define DDRSS0_CTL_19_DATA 0x01010000
+#define DDRSS0_CTL_20_DATA 0x01011001
+#define DDRSS0_CTL_21_DATA 0x02010000
+#define DDRSS0_CTL_22_DATA 0x00020100
+#define DDRSS0_CTL_23_DATA 0x0000000B
+#define DDRSS0_CTL_24_DATA 0x0000001C
+#define DDRSS0_CTL_25_DATA 0x00000000
+#define DDRSS0_CTL_26_DATA 0x00000000
+#define DDRSS0_CTL_27_DATA 0x03020200
+#define DDRSS0_CTL_28_DATA 0x00005656
+#define DDRSS0_CTL_29_DATA 0x00100000
+#define DDRSS0_CTL_30_DATA 0x00000000
+#define DDRSS0_CTL_31_DATA 0x00000000
+#define DDRSS0_CTL_32_DATA 0x00000000
+#define DDRSS0_CTL_33_DATA 0x00000000
+#define DDRSS0_CTL_34_DATA 0x040C0000
+#define DDRSS0_CTL_35_DATA 0x12501250
+#define DDRSS0_CTL_36_DATA 0x00050804
+#define DDRSS0_CTL_37_DATA 0x09040008
+#define DDRSS0_CTL_38_DATA 0x15000204
+#define DDRSS0_CTL_39_DATA 0x1760008B
+#define DDRSS0_CTL_40_DATA 0x1500422B
+#define DDRSS0_CTL_41_DATA 0x1760008B
+#define DDRSS0_CTL_42_DATA 0x2000422B
+#define DDRSS0_CTL_43_DATA 0x000A0A09
+#define DDRSS0_CTL_44_DATA 0x040003C5
+#define DDRSS0_CTL_45_DATA 0x1E161104
+#define DDRSS0_CTL_46_DATA 0x1000922C
+#define DDRSS0_CTL_47_DATA 0x1E161110
+#define DDRSS0_CTL_48_DATA 0x1000922C
+#define DDRSS0_CTL_49_DATA 0x02030410
+#define DDRSS0_CTL_50_DATA 0x2C060500
+#define DDRSS0_CTL_51_DATA 0x08292C29
+#define DDRSS0_CTL_52_DATA 0x14000E0A
+#define DDRSS0_CTL_53_DATA 0x04010A0A
+#define DDRSS0_CTL_54_DATA 0x01010004
+#define DDRSS0_CTL_55_DATA 0x0454540A
+#define DDRSS0_CTL_56_DATA 0x04313104
+#define DDRSS0_CTL_57_DATA 0x00003131
+#define DDRSS0_CTL_58_DATA 0x00010100
+#define DDRSS0_CTL_59_DATA 0x03010000
+#define DDRSS0_CTL_60_DATA 0x00001508
+#define DDRSS0_CTL_61_DATA 0x00000068
+#define DDRSS0_CTL_62_DATA 0x0000032B
+#define DDRSS0_CTL_63_DATA 0x00001035
+#define DDRSS0_CTL_64_DATA 0x0000032B
+#define DDRSS0_CTL_65_DATA 0x00001035
+#define DDRSS0_CTL_66_DATA 0x00000005
+#define DDRSS0_CTL_67_DATA 0x00050000
+#define DDRSS0_CTL_68_DATA 0x00CB0005
+#define DDRSS0_CTL_69_DATA 0x00CB0200
+#define DDRSS0_CTL_70_DATA 0x00400200
+#define DDRSS0_CTL_71_DATA 0x00120103
+#define DDRSS0_CTL_72_DATA 0x00100005
+#define DDRSS0_CTL_73_DATA 0x2F080010
+#define DDRSS0_CTL_74_DATA 0x0505012F
+#define DDRSS0_CTL_75_DATA 0x0401030A
+#define DDRSS0_CTL_76_DATA 0x041E100B
+#define DDRSS0_CTL_77_DATA 0x100B0401
+#define DDRSS0_CTL_78_DATA 0x0001041E
+#define DDRSS0_CTL_79_DATA 0x00160016
+#define DDRSS0_CTL_80_DATA 0x033B033B
+#define DDRSS0_CTL_81_DATA 0x033B033B
+#define DDRSS0_CTL_82_DATA 0x03050505
+#define DDRSS0_CTL_83_DATA 0x03010303
+#define DDRSS0_CTL_84_DATA 0x200B100B
+#define DDRSS0_CTL_85_DATA 0x04041004
+#define DDRSS0_CTL_86_DATA 0x200B100B
+#define DDRSS0_CTL_87_DATA 0x04041004
+#define DDRSS0_CTL_88_DATA 0x03010000
+#define DDRSS0_CTL_89_DATA 0x00010000
+#define DDRSS0_CTL_90_DATA 0x00000000
+#define DDRSS0_CTL_91_DATA 0x00000000
+#define DDRSS0_CTL_92_DATA 0x01000000
+#define DDRSS0_CTL_93_DATA 0x80104002
+#define DDRSS0_CTL_94_DATA 0x00000000
+#define DDRSS0_CTL_95_DATA 0x00040005
+#define DDRSS0_CTL_96_DATA 0x00000000
+#define DDRSS0_CTL_97_DATA 0x00050000
+#define DDRSS0_CTL_98_DATA 0x00000004
+#define DDRSS0_CTL_99_DATA 0x00000000
+#define DDRSS0_CTL_100_DATA 0x00040005
+#define DDRSS0_CTL_101_DATA 0x00000000
+#define DDRSS0_CTL_102_DATA 0x000018C0
+#define DDRSS0_CTL_103_DATA 0x000018C0
+#define DDRSS0_CTL_104_DATA 0x000018C0
+#define DDRSS0_CTL_105_DATA 0x000018C0
+#define DDRSS0_CTL_106_DATA 0x000018C0
+#define DDRSS0_CTL_107_DATA 0x00000000
+#define DDRSS0_CTL_108_DATA 0x000002B5
+#define DDRSS0_CTL_109_DATA 0x00040D40
+#define DDRSS0_CTL_110_DATA 0x00040D40
+#define DDRSS0_CTL_111_DATA 0x00040D40
+#define DDRSS0_CTL_112_DATA 0x00040D40
+#define DDRSS0_CTL_113_DATA 0x00040D40
+#define DDRSS0_CTL_114_DATA 0x00000000
+#define DDRSS0_CTL_115_DATA 0x00007173
+#define DDRSS0_CTL_116_DATA 0x00040D40
+#define DDRSS0_CTL_117_DATA 0x00040D40
+#define DDRSS0_CTL_118_DATA 0x00040D40
+#define DDRSS0_CTL_119_DATA 0x00040D40
+#define DDRSS0_CTL_120_DATA 0x00040D40
+#define DDRSS0_CTL_121_DATA 0x00000000
+#define DDRSS0_CTL_122_DATA 0x00007173
+#define DDRSS0_CTL_123_DATA 0x00000000
+#define DDRSS0_CTL_124_DATA 0x00000000
+#define DDRSS0_CTL_125_DATA 0x00000000
+#define DDRSS0_CTL_126_DATA 0x00000000
+#define DDRSS0_CTL_127_DATA 0x00000000
+#define DDRSS0_CTL_128_DATA 0x00000000
+#define DDRSS0_CTL_129_DATA 0x00000000
+#define DDRSS0_CTL_130_DATA 0x00000000
+#define DDRSS0_CTL_131_DATA 0x0B030500
+#define DDRSS0_CTL_132_DATA 0x00040B04
+#define DDRSS0_CTL_133_DATA 0x0A090000
+#define DDRSS0_CTL_134_DATA 0x0A090701
+#define DDRSS0_CTL_135_DATA 0x0900000E
+#define DDRSS0_CTL_136_DATA 0x0907010A
+#define DDRSS0_CTL_137_DATA 0x00000E0A
+#define DDRSS0_CTL_138_DATA 0x07010A09
+#define DDRSS0_CTL_139_DATA 0x000E0A09
+#define DDRSS0_CTL_140_DATA 0x07000401
+#define DDRSS0_CTL_141_DATA 0x00000000
+#define DDRSS0_CTL_142_DATA 0x00000000
+#define DDRSS0_CTL_143_DATA 0x00000000
+#define DDRSS0_CTL_144_DATA 0x00000000
+#define DDRSS0_CTL_145_DATA 0x00000000
+#define DDRSS0_CTL_146_DATA 0x00000000
+#define DDRSS0_CTL_147_DATA 0x00000000
+#define DDRSS0_CTL_148_DATA 0x08080000
+#define DDRSS0_CTL_149_DATA 0x01000000
+#define DDRSS0_CTL_150_DATA 0x800000C0
+#define DDRSS0_CTL_151_DATA 0x800000C0
+#define DDRSS0_CTL_152_DATA 0x800000C0
+#define DDRSS0_CTL_153_DATA 0x00000000
+#define DDRSS0_CTL_154_DATA 0x00001500
+#define DDRSS0_CTL_155_DATA 0x00000000
+#define DDRSS0_CTL_156_DATA 0x00000001
+#define DDRSS0_CTL_157_DATA 0x00000002
+#define DDRSS0_CTL_158_DATA 0x0000100E
+#define DDRSS0_CTL_159_DATA 0x00000000
+#define DDRSS0_CTL_160_DATA 0x00000000
+#define DDRSS0_CTL_161_DATA 0x00000000
+#define DDRSS0_CTL_162_DATA 0x00000000
+#define DDRSS0_CTL_163_DATA 0x00000000
+#define DDRSS0_CTL_164_DATA 0x000B0000
+#define DDRSS0_CTL_165_DATA 0x000E0006
+#define DDRSS0_CTL_166_DATA 0x000E0404
+#define DDRSS0_CTL_167_DATA 0x00D601AB
+#define DDRSS0_CTL_168_DATA 0x10100216
+#define DDRSS0_CTL_169_DATA 0x01AB0216
+#define DDRSS0_CTL_170_DATA 0x021600D6
+#define DDRSS0_CTL_171_DATA 0x02161010
+#define DDRSS0_CTL_172_DATA 0x00000000
+#define DDRSS0_CTL_173_DATA 0x00000000
+#define DDRSS0_CTL_174_DATA 0x00000000
+#define DDRSS0_CTL_175_DATA 0x3FF40084
+#define DDRSS0_CTL_176_DATA 0xF3003FF4
+#define DDRSS0_CTL_177_DATA 0x0000F3F3
+#define DDRSS0_CTL_178_DATA 0x35000000
+#define DDRSS0_CTL_179_DATA 0x27270035
+#define DDRSS0_CTL_180_DATA 0x0F0F0000
+#define DDRSS0_CTL_181_DATA 0x16000000
+#define DDRSS0_CTL_182_DATA 0x00841616
+#define DDRSS0_CTL_183_DATA 0x3FF43FF4
+#define DDRSS0_CTL_184_DATA 0xF3F3F300
+#define DDRSS0_CTL_185_DATA 0x00000000
+#define DDRSS0_CTL_186_DATA 0x00353500
+#define DDRSS0_CTL_187_DATA 0x00002727
+#define DDRSS0_CTL_188_DATA 0x00000F0F
+#define DDRSS0_CTL_189_DATA 0x16161600
+#define DDRSS0_CTL_190_DATA 0x00000020
+#define DDRSS0_CTL_191_DATA 0x01000000
+#define DDRSS0_CTL_192_DATA 0x00000001
+#define DDRSS0_CTL_193_DATA 0x00000000
+#define DDRSS0_CTL_194_DATA 0x01000000
+#define DDRSS0_CTL_195_DATA 0x00000001
+#define DDRSS0_CTL_196_DATA 0x00000000
+#define DDRSS0_CTL_197_DATA 0x00000000
+#define DDRSS0_CTL_198_DATA 0x00000000
+#define DDRSS0_CTL_199_DATA 0x00000000
+#define DDRSS0_CTL_200_DATA 0x00000000
+#define DDRSS0_CTL_201_DATA 0x00000000
+#define DDRSS0_CTL_202_DATA 0x00000000
+#define DDRSS0_CTL_203_DATA 0x00000000
+#define DDRSS0_CTL_204_DATA 0x00000000
+#define DDRSS0_CTL_205_DATA 0x00000000
+#define DDRSS0_CTL_206_DATA 0x02000000
+#define DDRSS0_CTL_207_DATA 0x01080101
+#define DDRSS0_CTL_208_DATA 0x00000000
+#define DDRSS0_CTL_209_DATA 0x00000000
+#define DDRSS0_CTL_210_DATA 0x00000000
+#define DDRSS0_CTL_211_DATA 0x00000000
+#define DDRSS0_CTL_212_DATA 0x00000000
+#define DDRSS0_CTL_213_DATA 0x00000000
+#define DDRSS0_CTL_214_DATA 0x00000000
+#define DDRSS0_CTL_215_DATA 0x00000000
+#define DDRSS0_CTL_216_DATA 0x00000000
+#define DDRSS0_CTL_217_DATA 0x00000000
+#define DDRSS0_CTL_218_DATA 0x00000000
+#define DDRSS0_CTL_219_DATA 0x00000000
+#define DDRSS0_CTL_220_DATA 0x00000000
+#define DDRSS0_CTL_221_DATA 0x00000000
+#define DDRSS0_CTL_222_DATA 0x00001000
+#define DDRSS0_CTL_223_DATA 0x006403E8
+#define DDRSS0_CTL_224_DATA 0x00000000
+#define DDRSS0_CTL_225_DATA 0x00000000
+#define DDRSS0_CTL_226_DATA 0x00000000
+#define DDRSS0_CTL_227_DATA 0x15110000
+#define DDRSS0_CTL_228_DATA 0x00040C18
+#define DDRSS0_CTL_229_DATA 0xF000C000
+#define DDRSS0_CTL_230_DATA 0x0000F000
+#define DDRSS0_CTL_231_DATA 0x00000000
+#define DDRSS0_CTL_232_DATA 0x00000000
+#define DDRSS0_CTL_233_DATA 0xC0000000
+#define DDRSS0_CTL_234_DATA 0xF000F000
+#define DDRSS0_CTL_235_DATA 0x00000000
+#define DDRSS0_CTL_236_DATA 0x00000000
+#define DDRSS0_CTL_237_DATA 0x00000000
+#define DDRSS0_CTL_238_DATA 0xF000C000
+#define DDRSS0_CTL_239_DATA 0x0000F000
+#define DDRSS0_CTL_240_DATA 0x00000000
+#define DDRSS0_CTL_241_DATA 0x00000000
+#define DDRSS0_CTL_242_DATA 0x00030000
+#define DDRSS0_CTL_243_DATA 0x00000000
+#define DDRSS0_CTL_244_DATA 0x00000000
+#define DDRSS0_CTL_245_DATA 0x00000000
+#define DDRSS0_CTL_246_DATA 0x00000000
+#define DDRSS0_CTL_247_DATA 0x00000000
+#define DDRSS0_CTL_248_DATA 0x00000000
+#define DDRSS0_CTL_249_DATA 0x00000000
+#define DDRSS0_CTL_250_DATA 0x00000000
+#define DDRSS0_CTL_251_DATA 0x00000000
+#define DDRSS0_CTL_252_DATA 0x00000000
+#define DDRSS0_CTL_253_DATA 0x00000000
+#define DDRSS0_CTL_254_DATA 0x00000000
+#define DDRSS0_CTL_255_DATA 0x00000000
+#define DDRSS0_CTL_256_DATA 0x00000000
+#define DDRSS0_CTL_257_DATA 0x01000200
+#define DDRSS0_CTL_258_DATA 0x00370040
+#define DDRSS0_CTL_259_DATA 0x00020008
+#define DDRSS0_CTL_260_DATA 0x00400100
+#define DDRSS0_CTL_261_DATA 0x00400855
+#define DDRSS0_CTL_262_DATA 0x01000200
+#define DDRSS0_CTL_263_DATA 0x08550040
+#define DDRSS0_CTL_264_DATA 0x00000040
+#define DDRSS0_CTL_265_DATA 0x006B0003
+#define DDRSS0_CTL_266_DATA 0x0100006B
+#define DDRSS0_CTL_267_DATA 0x03030303
+#define DDRSS0_CTL_268_DATA 0x00000000
+#define DDRSS0_CTL_269_DATA 0x00000202
+#define DDRSS0_CTL_270_DATA 0x00001FFF
+#define DDRSS0_CTL_271_DATA 0x3FFF2000
+#define DDRSS0_CTL_272_DATA 0x03FF0000
+#define DDRSS0_CTL_273_DATA 0x000103FF
+#define DDRSS0_CTL_274_DATA 0x0FFF0B00
+#define DDRSS0_CTL_275_DATA 0x01010001
+#define DDRSS0_CTL_276_DATA 0x01010101
+#define DDRSS0_CTL_277_DATA 0x01180101
+#define DDRSS0_CTL_278_DATA 0x00030000
+#define DDRSS0_CTL_279_DATA 0x00000000
+#define DDRSS0_CTL_280_DATA 0x00000000
+#define DDRSS0_CTL_281_DATA 0x00000000
+#define DDRSS0_CTL_282_DATA 0x00000000
+#define DDRSS0_CTL_283_DATA 0x00000000
+#define DDRSS0_CTL_284_DATA 0x00000000
+#define DDRSS0_CTL_285_DATA 0x00000000
+#define DDRSS0_CTL_286_DATA 0x00040101
+#define DDRSS0_CTL_287_DATA 0x04010100
+#define DDRSS0_CTL_288_DATA 0x00000000
+#define DDRSS0_CTL_289_DATA 0x00000000
+#define DDRSS0_CTL_290_DATA 0x03030300
+#define DDRSS0_CTL_291_DATA 0x00010101
+#define DDRSS0_CTL_292_DATA 0x00000000
+#define DDRSS0_CTL_293_DATA 0x00000000
+#define DDRSS0_CTL_294_DATA 0x00000000
+#define DDRSS0_CTL_295_DATA 0x00000000
+#define DDRSS0_CTL_296_DATA 0x00000000
+#define DDRSS0_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_298_DATA 0x00000FFF
+#define DDRSS0_CTL_299_DATA 0x00000000
+#define DDRSS0_CTL_300_DATA 0x00000000
+#define DDRSS0_CTL_301_DATA 0x00000000
+#define DDRSS0_CTL_302_DATA 0x00000000
+#define DDRSS0_CTL_303_DATA 0x00000000
+#define DDRSS0_CTL_304_DATA 0x00000000
+#define DDRSS0_CTL_305_DATA 0x00000000
+#define DDRSS0_CTL_306_DATA 0x00000000
+#define DDRSS0_CTL_307_DATA 0x00000000
+#define DDRSS0_CTL_308_DATA 0x00000000
+#define DDRSS0_CTL_309_DATA 0x00000000
+#define DDRSS0_CTL_310_DATA 0x00000000
+#define DDRSS0_CTL_311_DATA 0x00000000
+#define DDRSS0_CTL_312_DATA 0x00000000
+#define DDRSS0_CTL_313_DATA 0x01000000
+#define DDRSS0_CTL_314_DATA 0x00020201
+#define DDRSS0_CTL_315_DATA 0x01000101
+#define DDRSS0_CTL_316_DATA 0x01010001
+#define DDRSS0_CTL_317_DATA 0x00010101
+#define DDRSS0_CTL_318_DATA 0x050A0A03
+#define DDRSS0_CTL_319_DATA 0x10082323
+#define DDRSS0_CTL_320_DATA 0x00090310
+#define DDRSS0_CTL_321_DATA 0x0B0C030F
+#define DDRSS0_CTL_322_DATA 0x0B0C0306
+#define DDRSS0_CTL_323_DATA 0x0C090006
+#define DDRSS0_CTL_324_DATA 0x0100000C
+#define DDRSS0_CTL_325_DATA 0x08040801
+#define DDRSS0_CTL_326_DATA 0x00000004
+#define DDRSS0_CTL_327_DATA 0x00000000
+#define DDRSS0_CTL_328_DATA 0x00010000
+#define DDRSS0_CTL_329_DATA 0x00280D00
+#define DDRSS0_CTL_330_DATA 0x00000001
+#define DDRSS0_CTL_331_DATA 0x00030001
+#define DDRSS0_CTL_332_DATA 0x00000000
+#define DDRSS0_CTL_333_DATA 0x00000000
+#define DDRSS0_CTL_334_DATA 0x00000000
+#define DDRSS0_CTL_335_DATA 0x00000000
+#define DDRSS0_CTL_336_DATA 0x00000000
+#define DDRSS0_CTL_337_DATA 0x00000000
+#define DDRSS0_CTL_338_DATA 0x00000000
+#define DDRSS0_CTL_339_DATA 0x00000000
+#define DDRSS0_CTL_340_DATA 0x01000000
+#define DDRSS0_CTL_341_DATA 0x00000001
+#define DDRSS0_CTL_342_DATA 0x00010100
+#define DDRSS0_CTL_343_DATA 0x03030000
+#define DDRSS0_CTL_344_DATA 0x00000000
+#define DDRSS0_CTL_345_DATA 0x00000000
+#define DDRSS0_CTL_346_DATA 0x00000000
+#define DDRSS0_CTL_347_DATA 0x00000000
+#define DDRSS0_CTL_348_DATA 0x00000000
+#define DDRSS0_CTL_349_DATA 0x00000000
+#define DDRSS0_CTL_350_DATA 0x00000000
+#define DDRSS0_CTL_351_DATA 0x00000000
+#define DDRSS0_CTL_352_DATA 0x00000000
+#define DDRSS0_CTL_353_DATA 0x00000000
+#define DDRSS0_CTL_354_DATA 0x00000000
+#define DDRSS0_CTL_355_DATA 0x00000000
+#define DDRSS0_CTL_356_DATA 0x00000000
+#define DDRSS0_CTL_357_DATA 0x00000000
+#define DDRSS0_CTL_358_DATA 0x00000000
+#define DDRSS0_CTL_359_DATA 0x00000000
+#define DDRSS0_CTL_360_DATA 0x000556AA
+#define DDRSS0_CTL_361_DATA 0x000AAAAA
+#define DDRSS0_CTL_362_DATA 0x000AA955
+#define DDRSS0_CTL_363_DATA 0x00055555
+#define DDRSS0_CTL_364_DATA 0x000B3133
+#define DDRSS0_CTL_365_DATA 0x0004CD33
+#define DDRSS0_CTL_366_DATA 0x0004CECC
+#define DDRSS0_CTL_367_DATA 0x000B32CC
+#define DDRSS0_CTL_368_DATA 0x00010300
+#define DDRSS0_CTL_369_DATA 0x03000100
+#define DDRSS0_CTL_370_DATA 0x00000000
+#define DDRSS0_CTL_371_DATA 0x00000000
+#define DDRSS0_CTL_372_DATA 0x00000000
+#define DDRSS0_CTL_373_DATA 0x00000000
+#define DDRSS0_CTL_374_DATA 0x00000000
+#define DDRSS0_CTL_375_DATA 0x00000000
+#define DDRSS0_CTL_376_DATA 0x00000000
+#define DDRSS0_CTL_377_DATA 0x00010000
+#define DDRSS0_CTL_378_DATA 0x00000404
+#define DDRSS0_CTL_379_DATA 0x00000000
+#define DDRSS0_CTL_380_DATA 0x00000000
+#define DDRSS0_CTL_381_DATA 0x00000000
+#define DDRSS0_CTL_382_DATA 0x00000000
+#define DDRSS0_CTL_383_DATA 0x00000000
+#define DDRSS0_CTL_384_DATA 0x00000000
+#define DDRSS0_CTL_385_DATA 0x00000000
+#define DDRSS0_CTL_386_DATA 0x00000000
+#define DDRSS0_CTL_387_DATA 0x3A3A1B00
+#define DDRSS0_CTL_388_DATA 0x000A0000
+#define DDRSS0_CTL_389_DATA 0x000000C6
+#define DDRSS0_CTL_390_DATA 0x00000200
+#define DDRSS0_CTL_391_DATA 0x00000200
+#define DDRSS0_CTL_392_DATA 0x00000200
+#define DDRSS0_CTL_393_DATA 0x00000200
+#define DDRSS0_CTL_394_DATA 0x00000270
+#define DDRSS0_CTL_395_DATA 0x000007BC
+#define DDRSS0_CTL_396_DATA 0x00000204
+#define DDRSS0_CTL_397_DATA 0x0000206A
+#define DDRSS0_CTL_398_DATA 0x00000200
+#define DDRSS0_CTL_399_DATA 0x00000200
+#define DDRSS0_CTL_400_DATA 0x00000200
+#define DDRSS0_CTL_401_DATA 0x00000200
+#define DDRSS0_CTL_402_DATA 0x0000613E
+#define DDRSS0_CTL_403_DATA 0x00014424
+#define DDRSS0_CTL_404_DATA 0x00000E19
+#define DDRSS0_CTL_405_DATA 0x0000206A
+#define DDRSS0_CTL_406_DATA 0x00000200
+#define DDRSS0_CTL_407_DATA 0x00000200
+#define DDRSS0_CTL_408_DATA 0x00000200
+#define DDRSS0_CTL_409_DATA 0x00000200
+#define DDRSS0_CTL_410_DATA 0x0000613E
+#define DDRSS0_CTL_411_DATA 0x00014424
+#define DDRSS0_CTL_412_DATA 0x02020E19
+#define DDRSS0_CTL_413_DATA 0x03030202
+#define DDRSS0_CTL_414_DATA 0x00000022
+#define DDRSS0_CTL_415_DATA 0x00000000
+#define DDRSS0_CTL_416_DATA 0x00000000
+#define DDRSS0_CTL_417_DATA 0x00001403
+#define DDRSS0_CTL_418_DATA 0x000007D0
+#define DDRSS0_CTL_419_DATA 0x00000000
+#define DDRSS0_CTL_420_DATA 0x00000000
+#define DDRSS0_CTL_421_DATA 0x00030000
+#define DDRSS0_CTL_422_DATA 0x0007001F
+#define DDRSS0_CTL_423_DATA 0x001B0033
+#define DDRSS0_CTL_424_DATA 0x001B0033
+#define DDRSS0_CTL_425_DATA 0x00000000
+#define DDRSS0_CTL_426_DATA 0x00000000
+#define DDRSS0_CTL_427_DATA 0x02000000
+#define DDRSS0_CTL_428_DATA 0x01000404
+#define DDRSS0_CTL_429_DATA 0x0B220B22
+#define DDRSS0_CTL_430_DATA 0x00000105
+#define DDRSS0_CTL_431_DATA 0x00010101
+#define DDRSS0_CTL_432_DATA 0x00010101
+#define DDRSS0_CTL_433_DATA 0x00010001
+#define DDRSS0_CTL_434_DATA 0x00000101
+#define DDRSS0_CTL_435_DATA 0x02000201
+#define DDRSS0_CTL_436_DATA 0x02010000
+#define DDRSS0_CTL_437_DATA 0x00000200
+#define DDRSS0_CTL_438_DATA 0x28060000
+#define DDRSS0_CTL_439_DATA 0x00000128
+#define DDRSS0_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_442_DATA 0x00000000
+#define DDRSS0_CTL_443_DATA 0x00000000
+#define DDRSS0_CTL_444_DATA 0x00000000
+#define DDRSS0_CTL_445_DATA 0x00000000
+#define DDRSS0_CTL_446_DATA 0x00000000
+#define DDRSS0_CTL_447_DATA 0x00000000
+#define DDRSS0_CTL_448_DATA 0x00000000
+#define DDRSS0_CTL_449_DATA 0x00000000
+#define DDRSS0_CTL_450_DATA 0x00000000
+#define DDRSS0_CTL_451_DATA 0x00000000
+#define DDRSS0_CTL_452_DATA 0x00000000
+#define DDRSS0_CTL_453_DATA 0x00000000
+#define DDRSS0_CTL_454_DATA 0x00000000
+#define DDRSS0_CTL_455_DATA 0x00000000
+#define DDRSS0_CTL_456_DATA 0x00000000
+#define DDRSS0_CTL_457_DATA 0x00000000
+#define DDRSS0_CTL_458_DATA 0x00000000
+
+#define DDRSS0_PI_00_DATA 0x00000B00
+#define DDRSS0_PI_01_DATA 0x00000000
+#define DDRSS0_PI_02_DATA 0x00000000
+#define DDRSS0_PI_03_DATA 0x00000000
+#define DDRSS0_PI_04_DATA 0x00000000
+#define DDRSS0_PI_05_DATA 0x00000101
+#define DDRSS0_PI_06_DATA 0x00640000
+#define DDRSS0_PI_07_DATA 0x00000001
+#define DDRSS0_PI_08_DATA 0x00000000
+#define DDRSS0_PI_09_DATA 0x00000000
+#define DDRSS0_PI_10_DATA 0x00000000
+#define DDRSS0_PI_11_DATA 0x00000000
+#define DDRSS0_PI_12_DATA 0x00000003
+#define DDRSS0_PI_13_DATA 0x00010001
+#define DDRSS0_PI_14_DATA 0x0800000F
+#define DDRSS0_PI_15_DATA 0x00000103
+#define DDRSS0_PI_16_DATA 0x00000005
+#define DDRSS0_PI_17_DATA 0x00000000
+#define DDRSS0_PI_18_DATA 0x00000000
+#define DDRSS0_PI_19_DATA 0x00000000
+#define DDRSS0_PI_20_DATA 0x00000000
+#define DDRSS0_PI_21_DATA 0x00000000
+#define DDRSS0_PI_22_DATA 0x00000000
+#define DDRSS0_PI_23_DATA 0x00000000
+#define DDRSS0_PI_24_DATA 0x00000000
+#define DDRSS0_PI_25_DATA 0x00000000
+#define DDRSS0_PI_26_DATA 0x00010100
+#define DDRSS0_PI_27_DATA 0x00280A00
+#define DDRSS0_PI_28_DATA 0x00000000
+#define DDRSS0_PI_29_DATA 0x0F000000
+#define DDRSS0_PI_30_DATA 0x00003200
+#define DDRSS0_PI_31_DATA 0x00000000
+#define DDRSS0_PI_32_DATA 0x00000000
+#define DDRSS0_PI_33_DATA 0x01010102
+#define DDRSS0_PI_34_DATA 0x00000000
+#define DDRSS0_PI_35_DATA 0x000000AA
+#define DDRSS0_PI_36_DATA 0x00000055
+#define DDRSS0_PI_37_DATA 0x000000B5
+#define DDRSS0_PI_38_DATA 0x0000004A
+#define DDRSS0_PI_39_DATA 0x00000056
+#define DDRSS0_PI_40_DATA 0x000000A9
+#define DDRSS0_PI_41_DATA 0x000000A9
+#define DDRSS0_PI_42_DATA 0x000000B5
+#define DDRSS0_PI_43_DATA 0x00000000
+#define DDRSS0_PI_44_DATA 0x00000000
+#define DDRSS0_PI_45_DATA 0x000F0F00
+#define DDRSS0_PI_46_DATA 0x0000001B
+#define DDRSS0_PI_47_DATA 0x000007D0
+#define DDRSS0_PI_48_DATA 0x00000300
+#define DDRSS0_PI_49_DATA 0x00000000
+#define DDRSS0_PI_50_DATA 0x00000000
+#define DDRSS0_PI_51_DATA 0x01000000
+#define DDRSS0_PI_52_DATA 0x00010101
+#define DDRSS0_PI_53_DATA 0x00000000
+#define DDRSS0_PI_54_DATA 0x00030000
+#define DDRSS0_PI_55_DATA 0x0F000000
+#define DDRSS0_PI_56_DATA 0x00000017
+#define DDRSS0_PI_57_DATA 0x00000000
+#define DDRSS0_PI_58_DATA 0x00000000
+#define DDRSS0_PI_59_DATA 0x00000000
+#define DDRSS0_PI_60_DATA 0x0A0A140A
+#define DDRSS0_PI_61_DATA 0x10020201
+#define DDRSS0_PI_62_DATA 0x00020805
+#define DDRSS0_PI_63_DATA 0x01000404
+#define DDRSS0_PI_64_DATA 0x00000000
+#define DDRSS0_PI_65_DATA 0x00000000
+#define DDRSS0_PI_66_DATA 0x00000100
+#define DDRSS0_PI_67_DATA 0x0002020F
+#define DDRSS0_PI_68_DATA 0x00340000
+#define DDRSS0_PI_69_DATA 0x00000000
+#define DDRSS0_PI_70_DATA 0x00000000
+#define DDRSS0_PI_71_DATA 0x0000FFFF
+#define DDRSS0_PI_72_DATA 0x01000000
+#define DDRSS0_PI_73_DATA 0x00080000
+#define DDRSS0_PI_74_DATA 0x02000200
+#define DDRSS0_PI_75_DATA 0x01000100
+#define DDRSS0_PI_76_DATA 0x01000000
+#define DDRSS0_PI_77_DATA 0x02000200
+#define DDRSS0_PI_78_DATA 0x00000200
+#define DDRSS0_PI_79_DATA 0x00000000
+#define DDRSS0_PI_80_DATA 0x00000000
+#define DDRSS0_PI_81_DATA 0x00000000
+#define DDRSS0_PI_82_DATA 0x00000000
+#define DDRSS0_PI_83_DATA 0x00000000
+#define DDRSS0_PI_84_DATA 0x00000000
+#define DDRSS0_PI_85_DATA 0x00000000
+#define DDRSS0_PI_86_DATA 0x00000000
+#define DDRSS0_PI_87_DATA 0x00000000
+#define DDRSS0_PI_88_DATA 0x00000000
+#define DDRSS0_PI_89_DATA 0x00000000
+#define DDRSS0_PI_90_DATA 0x00000000
+#define DDRSS0_PI_91_DATA 0x00000400
+#define DDRSS0_PI_92_DATA 0x02010000
+#define DDRSS0_PI_93_DATA 0x00080003
+#define DDRSS0_PI_94_DATA 0x00080000
+#define DDRSS0_PI_95_DATA 0x00000001
+#define DDRSS0_PI_96_DATA 0x00000000
+#define DDRSS0_PI_97_DATA 0x0000AA00
+#define DDRSS0_PI_98_DATA 0x00000000
+#define DDRSS0_PI_99_DATA 0x00000000
+#define DDRSS0_PI_100_DATA 0x00010000
+#define DDRSS0_PI_101_DATA 0x00000000
+#define DDRSS0_PI_102_DATA 0x00000000
+#define DDRSS0_PI_103_DATA 0x00000000
+#define DDRSS0_PI_104_DATA 0x00000000
+#define DDRSS0_PI_105_DATA 0x00000000
+#define DDRSS0_PI_106_DATA 0x00000000
+#define DDRSS0_PI_107_DATA 0x00000000
+#define DDRSS0_PI_108_DATA 0x00000000
+#define DDRSS0_PI_109_DATA 0x00000000
+#define DDRSS0_PI_110_DATA 0x00000000
+#define DDRSS0_PI_111_DATA 0x00000000
+#define DDRSS0_PI_112_DATA 0x00000000
+#define DDRSS0_PI_113_DATA 0x00000000
+#define DDRSS0_PI_114_DATA 0x00000000
+#define DDRSS0_PI_115_DATA 0x00000000
+#define DDRSS0_PI_116_DATA 0x00000000
+#define DDRSS0_PI_117_DATA 0x00000000
+#define DDRSS0_PI_118_DATA 0x00000000
+#define DDRSS0_PI_119_DATA 0x00000000
+#define DDRSS0_PI_120_DATA 0x00000000
+#define DDRSS0_PI_121_DATA 0x00000000
+#define DDRSS0_PI_122_DATA 0x00000000
+#define DDRSS0_PI_123_DATA 0x00000000
+#define DDRSS0_PI_124_DATA 0x00000000
+#define DDRSS0_PI_125_DATA 0x00000008
+#define DDRSS0_PI_126_DATA 0x00000000
+#define DDRSS0_PI_127_DATA 0x00000000
+#define DDRSS0_PI_128_DATA 0x00000000
+#define DDRSS0_PI_129_DATA 0x00000000
+#define DDRSS0_PI_130_DATA 0x00000000
+#define DDRSS0_PI_131_DATA 0x00000000
+#define DDRSS0_PI_132_DATA 0x00000000
+#define DDRSS0_PI_133_DATA 0x00000000
+#define DDRSS0_PI_134_DATA 0x00000002
+#define DDRSS0_PI_135_DATA 0x00000000
+#define DDRSS0_PI_136_DATA 0x00000000
+#define DDRSS0_PI_137_DATA 0x0000000A
+#define DDRSS0_PI_138_DATA 0x00000019
+#define DDRSS0_PI_139_DATA 0x00000100
+#define DDRSS0_PI_140_DATA 0x00000000
+#define DDRSS0_PI_141_DATA 0x00000000
+#define DDRSS0_PI_142_DATA 0x00000000
+#define DDRSS0_PI_143_DATA 0x00000000
+#define DDRSS0_PI_144_DATA 0x01000000
+#define DDRSS0_PI_145_DATA 0x00010003
+#define DDRSS0_PI_146_DATA 0x02000101
+#define DDRSS0_PI_147_DATA 0x01030001
+#define DDRSS0_PI_148_DATA 0x00010400
+#define DDRSS0_PI_149_DATA 0x06000105
+#define DDRSS0_PI_150_DATA 0x01070001
+#define DDRSS0_PI_151_DATA 0x00000000
+#define DDRSS0_PI_152_DATA 0x00000000
+#define DDRSS0_PI_153_DATA 0x00000000
+#define DDRSS0_PI_154_DATA 0x00010001
+#define DDRSS0_PI_155_DATA 0x00000000
+#define DDRSS0_PI_156_DATA 0x00000000
+#define DDRSS0_PI_157_DATA 0x00000000
+#define DDRSS0_PI_158_DATA 0x00000000
+#define DDRSS0_PI_159_DATA 0x00000401
+#define DDRSS0_PI_160_DATA 0x00000000
+#define DDRSS0_PI_161_DATA 0x05010000
+#define DDRSS0_PI_162_DATA 0x00000001
+#define DDRSS0_PI_163_DATA 0x2B2B0201
+#define DDRSS0_PI_164_DATA 0x00000034
+#define DDRSS0_PI_165_DATA 0x00000068
+#define DDRSS0_PI_166_DATA 0x00020068
+#define DDRSS0_PI_167_DATA 0x02000200
+#define DDRSS0_PI_168_DATA 0x50120C04
+#define DDRSS0_PI_169_DATA 0x00155012
+#define DDRSS0_PI_170_DATA 0x00000068
+#define DDRSS0_PI_171_DATA 0x0000032B
+#define DDRSS0_PI_172_DATA 0x00001035
+#define DDRSS0_PI_173_DATA 0x0000032B
+#define DDRSS0_PI_174_DATA 0x04001035
+#define DDRSS0_PI_175_DATA 0x01010404
+#define DDRSS0_PI_176_DATA 0x00001500
+#define DDRSS0_PI_177_DATA 0x00150015
+#define DDRSS0_PI_178_DATA 0x01000100
+#define DDRSS0_PI_179_DATA 0x00000100
+#define DDRSS0_PI_180_DATA 0x00000000
+#define DDRSS0_PI_181_DATA 0x01010101
+#define DDRSS0_PI_182_DATA 0x00000000
+#define DDRSS0_PI_183_DATA 0x00000000
+#define DDRSS0_PI_184_DATA 0x00000000
+#define DDRSS0_PI_185_DATA 0x19040000
+#define DDRSS0_PI_186_DATA 0x0E0E0219
+#define DDRSS0_PI_187_DATA 0x00040402
+#define DDRSS0_PI_188_DATA 0x000D0035
+#define DDRSS0_PI_189_DATA 0x00218049
+#define DDRSS0_PI_190_DATA 0x00218049
+#define DDRSS0_PI_191_DATA 0x01000101
+#define DDRSS0_PI_192_DATA 0x0004000E
+#define DDRSS0_PI_193_DATA 0x00040216
+#define DDRSS0_PI_194_DATA 0x01000216
+#define DDRSS0_PI_195_DATA 0x000F000F
+#define DDRSS0_PI_196_DATA 0x02170100
+#define DDRSS0_PI_197_DATA 0x01000217
+#define DDRSS0_PI_198_DATA 0x02170217
+#define DDRSS0_PI_199_DATA 0x2F1B3200
+#define DDRSS0_PI_200_DATA 0x01012F1B
+#define DDRSS0_PI_201_DATA 0x0A070601
+#define DDRSS0_PI_202_DATA 0x1F130A0D
+#define DDRSS0_PI_203_DATA 0x1F130A14
+#define DDRSS0_PI_204_DATA 0x0000C014
+#define DDRSS0_PI_205_DATA 0x00C01000
+#define DDRSS0_PI_206_DATA 0x00C01000
+#define DDRSS0_PI_207_DATA 0x00021000
+#define DDRSS0_PI_208_DATA 0x0024000E
+#define DDRSS0_PI_209_DATA 0x00240216
+#define DDRSS0_PI_210_DATA 0x00110216
+#define DDRSS0_PI_211_DATA 0x32000056
+#define DDRSS0_PI_212_DATA 0x00000101
+#define DDRSS0_PI_213_DATA 0x005F0036
+#define DDRSS0_PI_214_DATA 0x03013212
+#define DDRSS0_PI_215_DATA 0x00003600
+#define DDRSS0_PI_216_DATA 0x3212005F
+#define DDRSS0_PI_217_DATA 0x09000001
+#define DDRSS0_PI_218_DATA 0x06010504
+#define DDRSS0_PI_219_DATA 0x04000364
+#define DDRSS0_PI_220_DATA 0x0A032001
+#define DDRSS0_PI_221_DATA 0x2C31110A
+#define DDRSS0_PI_222_DATA 0x00002918
+#define DDRSS0_PI_223_DATA 0x6000838E
+#define DDRSS0_PI_224_DATA 0x1E202008
+#define DDRSS0_PI_225_DATA 0x2C311116
+#define DDRSS0_PI_226_DATA 0x00002918
+#define DDRSS0_PI_227_DATA 0x6000838E
+#define DDRSS0_PI_228_DATA 0x1E202008
+#define DDRSS0_PI_229_DATA 0x0000C616
+#define DDRSS0_PI_230_DATA 0x000007BC
+#define DDRSS0_PI_231_DATA 0x0000206A
+#define DDRSS0_PI_232_DATA 0x00014424
+#define DDRSS0_PI_233_DATA 0x0000206A
+#define DDRSS0_PI_234_DATA 0x00014424
+#define DDRSS0_PI_235_DATA 0x033B0016
+#define DDRSS0_PI_236_DATA 0x0303033B
+#define DDRSS0_PI_237_DATA 0x002AF803
+#define DDRSS0_PI_238_DATA 0x0001ADAF
+#define DDRSS0_PI_239_DATA 0x00000005
+#define DDRSS0_PI_240_DATA 0x0000006E
+#define DDRSS0_PI_241_DATA 0x00000016
+#define DDRSS0_PI_242_DATA 0x000681C8
+#define DDRSS0_PI_243_DATA 0x0001ADAF
+#define DDRSS0_PI_244_DATA 0x00000005
+#define DDRSS0_PI_245_DATA 0x000010A9
+#define DDRSS0_PI_246_DATA 0x0000033B
+#define DDRSS0_PI_247_DATA 0x000681C8
+#define DDRSS0_PI_248_DATA 0x0001ADAF
+#define DDRSS0_PI_249_DATA 0x00000005
+#define DDRSS0_PI_250_DATA 0x000010A9
+#define DDRSS0_PI_251_DATA 0x0100033B
+#define DDRSS0_PI_252_DATA 0x00370040
+#define DDRSS0_PI_253_DATA 0x00010008
+#define DDRSS0_PI_254_DATA 0x08550040
+#define DDRSS0_PI_255_DATA 0x00010040
+#define DDRSS0_PI_256_DATA 0x08550040
+#define DDRSS0_PI_257_DATA 0x00000340
+#define DDRSS0_PI_258_DATA 0x006B006B
+#define DDRSS0_PI_259_DATA 0x08040404
+#define DDRSS0_PI_260_DATA 0x00000055
+#define DDRSS0_PI_261_DATA 0x55083C5A
+#define DDRSS0_PI_262_DATA 0x5A000000
+#define DDRSS0_PI_263_DATA 0x0055083C
+#define DDRSS0_PI_264_DATA 0x3C5A0000
+#define DDRSS0_PI_265_DATA 0x00005508
+#define DDRSS0_PI_266_DATA 0x0C3C5A00
+#define DDRSS0_PI_267_DATA 0x080F0E0D
+#define DDRSS0_PI_268_DATA 0x000B0A09
+#define DDRSS0_PI_269_DATA 0x00030201
+#define DDRSS0_PI_270_DATA 0x01000000
+#define DDRSS0_PI_271_DATA 0x04020201
+#define DDRSS0_PI_272_DATA 0x00080804
+#define DDRSS0_PI_273_DATA 0x00000000
+#define DDRSS0_PI_274_DATA 0x00000000
+#define DDRSS0_PI_275_DATA 0x00F30084
+#define DDRSS0_PI_276_DATA 0x00160000
+#define DDRSS0_PI_277_DATA 0x35F33FF4
+#define DDRSS0_PI_278_DATA 0x00160F27
+#define DDRSS0_PI_279_DATA 0x35F33FF4
+#define DDRSS0_PI_280_DATA 0x00160F27
+#define DDRSS0_PI_281_DATA 0x00F30084
+#define DDRSS0_PI_282_DATA 0x00160000
+#define DDRSS0_PI_283_DATA 0x35F33FF4
+#define DDRSS0_PI_284_DATA 0x00160F27
+#define DDRSS0_PI_285_DATA 0x35F33FF4
+#define DDRSS0_PI_286_DATA 0x00160F27
+#define DDRSS0_PI_287_DATA 0x00F30084
+#define DDRSS0_PI_288_DATA 0x00160000
+#define DDRSS0_PI_289_DATA 0x35F33FF4
+#define DDRSS0_PI_290_DATA 0x00160F27
+#define DDRSS0_PI_291_DATA 0x35F33FF4
+#define DDRSS0_PI_292_DATA 0x00160F27
+#define DDRSS0_PI_293_DATA 0x00F30084
+#define DDRSS0_PI_294_DATA 0x00160000
+#define DDRSS0_PI_295_DATA 0x35F33FF4
+#define DDRSS0_PI_296_DATA 0x00160F27
+#define DDRSS0_PI_297_DATA 0x35F33FF4
+#define DDRSS0_PI_298_DATA 0x00160F27
+#define DDRSS0_PI_299_DATA 0x00000000
+
+#define DDRSS0_PHY_00_DATA 0x000004F0
+#define DDRSS0_PHY_01_DATA 0x00000000
+#define DDRSS0_PHY_02_DATA 0x00030200
+#define DDRSS0_PHY_03_DATA 0x00000000
+#define DDRSS0_PHY_04_DATA 0x00000000
+#define DDRSS0_PHY_05_DATA 0x01030000
+#define DDRSS0_PHY_06_DATA 0x00010000
+#define DDRSS0_PHY_07_DATA 0x01030004
+#define DDRSS0_PHY_08_DATA 0x01000000
+#define DDRSS0_PHY_09_DATA 0x00000000
+#define DDRSS0_PHY_10_DATA 0x00000000
+#define DDRSS0_PHY_11_DATA 0x01000001
+#define DDRSS0_PHY_12_DATA 0x00000200
+#define DDRSS0_PHY_13_DATA 0x000800C0
+#define DDRSS0_PHY_14_DATA 0x060100CC
+#define DDRSS0_PHY_15_DATA 0x00030066
+#define DDRSS0_PHY_16_DATA 0x00000000
+#define DDRSS0_PHY_17_DATA 0x00000301
+#define DDRSS0_PHY_18_DATA 0x0000AAAA
+#define DDRSS0_PHY_19_DATA 0x00005555
+#define DDRSS0_PHY_20_DATA 0x0000B5B5
+#define DDRSS0_PHY_21_DATA 0x00004A4A
+#define DDRSS0_PHY_22_DATA 0x00005656
+#define DDRSS0_PHY_23_DATA 0x0000A9A9
+#define DDRSS0_PHY_24_DATA 0x0000A9A9
+#define DDRSS0_PHY_25_DATA 0x0000B5B5
+#define DDRSS0_PHY_26_DATA 0x00000000
+#define DDRSS0_PHY_27_DATA 0x00000000
+#define DDRSS0_PHY_28_DATA 0x2A000000
+#define DDRSS0_PHY_29_DATA 0x00000808
+#define DDRSS0_PHY_30_DATA 0x0F000000
+#define DDRSS0_PHY_31_DATA 0x00000F08
+#define DDRSS0_PHY_32_DATA 0x10400000
+#define DDRSS0_PHY_33_DATA 0x0C002006
+#define DDRSS0_PHY_34_DATA 0x00000000
+#define DDRSS0_PHY_35_DATA 0x00000000
+#define DDRSS0_PHY_36_DATA 0x55555555
+#define DDRSS0_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_38_DATA 0x55555555
+#define DDRSS0_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_40_DATA 0x00005555
+#define DDRSS0_PHY_41_DATA 0x01000100
+#define DDRSS0_PHY_42_DATA 0x00800180
+#define DDRSS0_PHY_43_DATA 0x00000001
+#define DDRSS0_PHY_44_DATA 0x00000000
+#define DDRSS0_PHY_45_DATA 0x00000000
+#define DDRSS0_PHY_46_DATA 0x00000000
+#define DDRSS0_PHY_47_DATA 0x00000000
+#define DDRSS0_PHY_48_DATA 0x00000000
+#define DDRSS0_PHY_49_DATA 0x00000000
+#define DDRSS0_PHY_50_DATA 0x00000000
+#define DDRSS0_PHY_51_DATA 0x00000000
+#define DDRSS0_PHY_52_DATA 0x00000000
+#define DDRSS0_PHY_53_DATA 0x00000000
+#define DDRSS0_PHY_54_DATA 0x00000000
+#define DDRSS0_PHY_55_DATA 0x00000000
+#define DDRSS0_PHY_56_DATA 0x00000000
+#define DDRSS0_PHY_57_DATA 0x00000000
+#define DDRSS0_PHY_58_DATA 0x00000000
+#define DDRSS0_PHY_59_DATA 0x00000000
+#define DDRSS0_PHY_60_DATA 0x00000000
+#define DDRSS0_PHY_61_DATA 0x00000000
+#define DDRSS0_PHY_62_DATA 0x00000000
+#define DDRSS0_PHY_63_DATA 0x00000000
+#define DDRSS0_PHY_64_DATA 0x00000000
+#define DDRSS0_PHY_65_DATA 0x00000000
+#define DDRSS0_PHY_66_DATA 0x00000104
+#define DDRSS0_PHY_67_DATA 0x00000120
+#define DDRSS0_PHY_68_DATA 0x00000000
+#define DDRSS0_PHY_69_DATA 0x00000000
+#define DDRSS0_PHY_70_DATA 0x00000000
+#define DDRSS0_PHY_71_DATA 0x00000000
+#define DDRSS0_PHY_72_DATA 0x00000000
+#define DDRSS0_PHY_73_DATA 0x00000000
+#define DDRSS0_PHY_74_DATA 0x00000000
+#define DDRSS0_PHY_75_DATA 0x00000001
+#define DDRSS0_PHY_76_DATA 0x07FF0000
+#define DDRSS0_PHY_77_DATA 0x0080081F
+#define DDRSS0_PHY_78_DATA 0x00081020
+#define DDRSS0_PHY_79_DATA 0x04010000
+#define DDRSS0_PHY_80_DATA 0x00000000
+#define DDRSS0_PHY_81_DATA 0x00000000
+#define DDRSS0_PHY_82_DATA 0x00000000
+#define DDRSS0_PHY_83_DATA 0x00000100
+#define DDRSS0_PHY_84_DATA 0x01CC0C01
+#define DDRSS0_PHY_85_DATA 0x1003CC0C
+#define DDRSS0_PHY_86_DATA 0x20000140
+#define DDRSS0_PHY_87_DATA 0x07FF0200
+#define DDRSS0_PHY_88_DATA 0x0000DD01
+#define DDRSS0_PHY_89_DATA 0x10100303
+#define DDRSS0_PHY_90_DATA 0x10101010
+#define DDRSS0_PHY_91_DATA 0x10101010
+#define DDRSS0_PHY_92_DATA 0x00021010
+#define DDRSS0_PHY_93_DATA 0x00100010
+#define DDRSS0_PHY_94_DATA 0x00100010
+#define DDRSS0_PHY_95_DATA 0x00100010
+#define DDRSS0_PHY_96_DATA 0x00100010
+#define DDRSS0_PHY_97_DATA 0x00050010
+#define DDRSS0_PHY_98_DATA 0x51517041
+#define DDRSS0_PHY_99_DATA 0x31C06001
+#define DDRSS0_PHY_100_DATA 0x07AB01AB
+#define DDRSS0_PHY_101_DATA 0x00C0C001
+#define DDRSS0_PHY_102_DATA 0x0E0D0101
+#define DDRSS0_PHY_103_DATA 0x10001000
+#define DDRSS0_PHY_104_DATA 0x0C083E42
+#define DDRSS0_PHY_105_DATA 0x0F0C3701
+#define DDRSS0_PHY_106_DATA 0x01000140
+#define DDRSS0_PHY_107_DATA 0x0C000420
+#define DDRSS0_PHY_108_DATA 0x00000198
+#define DDRSS0_PHY_109_DATA 0x0A0000D0
+#define DDRSS0_PHY_110_DATA 0x00030200
+#define DDRSS0_PHY_111_DATA 0x02800000
+#define DDRSS0_PHY_112_DATA 0x80800000
+#define DDRSS0_PHY_113_DATA 0x000E2010
+#define DDRSS0_PHY_114_DATA 0x76543210
+#define DDRSS0_PHY_115_DATA 0x00000008
+#define DDRSS0_PHY_116_DATA 0x02800280
+#define DDRSS0_PHY_117_DATA 0x02800280
+#define DDRSS0_PHY_118_DATA 0x02800280
+#define DDRSS0_PHY_119_DATA 0x02800280
+#define DDRSS0_PHY_120_DATA 0x00000280
+#define DDRSS0_PHY_121_DATA 0x0000A000
+#define DDRSS0_PHY_122_DATA 0x00A000A0
+#define DDRSS0_PHY_123_DATA 0x00A000A0
+#define DDRSS0_PHY_124_DATA 0x00A000A0
+#define DDRSS0_PHY_125_DATA 0x00A000A0
+#define DDRSS0_PHY_126_DATA 0x00A000A0
+#define DDRSS0_PHY_127_DATA 0x00A000A0
+#define DDRSS0_PHY_128_DATA 0x00A000A0
+#define DDRSS0_PHY_129_DATA 0x00A000A0
+#define DDRSS0_PHY_130_DATA 0x01C200A0
+#define DDRSS0_PHY_131_DATA 0x01A00005
+#define DDRSS0_PHY_132_DATA 0x00000000
+#define DDRSS0_PHY_133_DATA 0x00000000
+#define DDRSS0_PHY_134_DATA 0x00080200
+#define DDRSS0_PHY_135_DATA 0x00000000
+#define DDRSS0_PHY_136_DATA 0x20202000
+#define DDRSS0_PHY_137_DATA 0x20202020
+#define DDRSS0_PHY_138_DATA 0xF0F02020
+#define DDRSS0_PHY_139_DATA 0x00000000
+#define DDRSS0_PHY_140_DATA 0x00000000
+#define DDRSS0_PHY_141_DATA 0x00000000
+#define DDRSS0_PHY_142_DATA 0x00000000
+#define DDRSS0_PHY_143_DATA 0x00000000
+#define DDRSS0_PHY_144_DATA 0x00000000
+#define DDRSS0_PHY_145_DATA 0x00000000
+#define DDRSS0_PHY_146_DATA 0x00000000
+#define DDRSS0_PHY_147_DATA 0x00000000
+#define DDRSS0_PHY_148_DATA 0x00000000
+#define DDRSS0_PHY_149_DATA 0x00000000
+#define DDRSS0_PHY_150_DATA 0x00000000
+#define DDRSS0_PHY_151_DATA 0x00000000
+#define DDRSS0_PHY_152_DATA 0x00000000
+#define DDRSS0_PHY_153_DATA 0x00000000
+#define DDRSS0_PHY_154_DATA 0x00000000
+#define DDRSS0_PHY_155_DATA 0x00000000
+#define DDRSS0_PHY_156_DATA 0x00000000
+#define DDRSS0_PHY_157_DATA 0x00000000
+#define DDRSS0_PHY_158_DATA 0x00000000
+#define DDRSS0_PHY_159_DATA 0x00000000
+#define DDRSS0_PHY_160_DATA 0x00000000
+#define DDRSS0_PHY_161_DATA 0x00000000
+#define DDRSS0_PHY_162_DATA 0x00000000
+#define DDRSS0_PHY_163_DATA 0x00000000
+#define DDRSS0_PHY_164_DATA 0x00000000
+#define DDRSS0_PHY_165_DATA 0x00000000
+#define DDRSS0_PHY_166_DATA 0x00000000
+#define DDRSS0_PHY_167_DATA 0x00000000
+#define DDRSS0_PHY_168_DATA 0x00000000
+#define DDRSS0_PHY_169_DATA 0x00000000
+#define DDRSS0_PHY_170_DATA 0x00000000
+#define DDRSS0_PHY_171_DATA 0x00000000
+#define DDRSS0_PHY_172_DATA 0x00000000
+#define DDRSS0_PHY_173_DATA 0x00000000
+#define DDRSS0_PHY_174_DATA 0x00000000
+#define DDRSS0_PHY_175_DATA 0x00000000
+#define DDRSS0_PHY_176_DATA 0x00000000
+#define DDRSS0_PHY_177_DATA 0x00000000
+#define DDRSS0_PHY_178_DATA 0x00000000
+#define DDRSS0_PHY_179_DATA 0x00000000
+#define DDRSS0_PHY_180_DATA 0x00000000
+#define DDRSS0_PHY_181_DATA 0x00000000
+#define DDRSS0_PHY_182_DATA 0x00000000
+#define DDRSS0_PHY_183_DATA 0x00000000
+#define DDRSS0_PHY_184_DATA 0x00000000
+#define DDRSS0_PHY_185_DATA 0x00000000
+#define DDRSS0_PHY_186_DATA 0x00000000
+#define DDRSS0_PHY_187_DATA 0x00000000
+#define DDRSS0_PHY_188_DATA 0x00000000
+#define DDRSS0_PHY_189_DATA 0x00000000
+#define DDRSS0_PHY_190_DATA 0x00000000
+#define DDRSS0_PHY_191_DATA 0x00000000
+#define DDRSS0_PHY_192_DATA 0x00000000
+#define DDRSS0_PHY_193_DATA 0x00000000
+#define DDRSS0_PHY_194_DATA 0x00000000
+#define DDRSS0_PHY_195_DATA 0x00000000
+#define DDRSS0_PHY_196_DATA 0x00000000
+#define DDRSS0_PHY_197_DATA 0x00000000
+#define DDRSS0_PHY_198_DATA 0x00000000
+#define DDRSS0_PHY_199_DATA 0x00000000
+#define DDRSS0_PHY_200_DATA 0x00000000
+#define DDRSS0_PHY_201_DATA 0x00000000
+#define DDRSS0_PHY_202_DATA 0x00000000
+#define DDRSS0_PHY_203_DATA 0x00000000
+#define DDRSS0_PHY_204_DATA 0x00000000
+#define DDRSS0_PHY_205_DATA 0x00000000
+#define DDRSS0_PHY_206_DATA 0x00000000
+#define DDRSS0_PHY_207_DATA 0x00000000
+#define DDRSS0_PHY_208_DATA 0x00000000
+#define DDRSS0_PHY_209_DATA 0x00000000
+#define DDRSS0_PHY_210_DATA 0x00000000
+#define DDRSS0_PHY_211_DATA 0x00000000
+#define DDRSS0_PHY_212_DATA 0x00000000
+#define DDRSS0_PHY_213_DATA 0x00000000
+#define DDRSS0_PHY_214_DATA 0x00000000
+#define DDRSS0_PHY_215_DATA 0x00000000
+#define DDRSS0_PHY_216_DATA 0x00000000
+#define DDRSS0_PHY_217_DATA 0x00000000
+#define DDRSS0_PHY_218_DATA 0x00000000
+#define DDRSS0_PHY_219_DATA 0x00000000
+#define DDRSS0_PHY_220_DATA 0x00000000
+#define DDRSS0_PHY_221_DATA 0x00000000
+#define DDRSS0_PHY_222_DATA 0x00000000
+#define DDRSS0_PHY_223_DATA 0x00000000
+#define DDRSS0_PHY_224_DATA 0x00000000
+#define DDRSS0_PHY_225_DATA 0x00000000
+#define DDRSS0_PHY_226_DATA 0x00000000
+#define DDRSS0_PHY_227_DATA 0x00000000
+#define DDRSS0_PHY_228_DATA 0x00000000
+#define DDRSS0_PHY_229_DATA 0x00000000
+#define DDRSS0_PHY_230_DATA 0x00000000
+#define DDRSS0_PHY_231_DATA 0x00000000
+#define DDRSS0_PHY_232_DATA 0x00000000
+#define DDRSS0_PHY_233_DATA 0x00000000
+#define DDRSS0_PHY_234_DATA 0x00000000
+#define DDRSS0_PHY_235_DATA 0x00000000
+#define DDRSS0_PHY_236_DATA 0x00000000
+#define DDRSS0_PHY_237_DATA 0x00000000
+#define DDRSS0_PHY_238_DATA 0x00000000
+#define DDRSS0_PHY_239_DATA 0x00000000
+#define DDRSS0_PHY_240_DATA 0x00000000
+#define DDRSS0_PHY_241_DATA 0x00000000
+#define DDRSS0_PHY_242_DATA 0x00000000
+#define DDRSS0_PHY_243_DATA 0x00000000
+#define DDRSS0_PHY_244_DATA 0x00000000
+#define DDRSS0_PHY_245_DATA 0x00000000
+#define DDRSS0_PHY_246_DATA 0x00000000
+#define DDRSS0_PHY_247_DATA 0x00000000
+#define DDRSS0_PHY_248_DATA 0x00000000
+#define DDRSS0_PHY_249_DATA 0x00000000
+#define DDRSS0_PHY_250_DATA 0x00000000
+#define DDRSS0_PHY_251_DATA 0x00000000
+#define DDRSS0_PHY_252_DATA 0x00000000
+#define DDRSS0_PHY_253_DATA 0x00000000
+#define DDRSS0_PHY_254_DATA 0x00000000
+#define DDRSS0_PHY_255_DATA 0x00000000
+#define DDRSS0_PHY_256_DATA 0x000004F0
+#define DDRSS0_PHY_257_DATA 0x00000000
+#define DDRSS0_PHY_258_DATA 0x00030200
+#define DDRSS0_PHY_259_DATA 0x00000000
+#define DDRSS0_PHY_260_DATA 0x00000000
+#define DDRSS0_PHY_261_DATA 0x01030000
+#define DDRSS0_PHY_262_DATA 0x00010000
+#define DDRSS0_PHY_263_DATA 0x01030004
+#define DDRSS0_PHY_264_DATA 0x01000000
+#define DDRSS0_PHY_265_DATA 0x00000000
+#define DDRSS0_PHY_266_DATA 0x00000000
+#define DDRSS0_PHY_267_DATA 0x01000001
+#define DDRSS0_PHY_268_DATA 0x00000200
+#define DDRSS0_PHY_269_DATA 0x000800C0
+#define DDRSS0_PHY_270_DATA 0x060100CC
+#define DDRSS0_PHY_271_DATA 0x00030066
+#define DDRSS0_PHY_272_DATA 0x00000000
+#define DDRSS0_PHY_273_DATA 0x00000301
+#define DDRSS0_PHY_274_DATA 0x0000AAAA
+#define DDRSS0_PHY_275_DATA 0x00005555
+#define DDRSS0_PHY_276_DATA 0x0000B5B5
+#define DDRSS0_PHY_277_DATA 0x00004A4A
+#define DDRSS0_PHY_278_DATA 0x00005656
+#define DDRSS0_PHY_279_DATA 0x0000A9A9
+#define DDRSS0_PHY_280_DATA 0x0000A9A9
+#define DDRSS0_PHY_281_DATA 0x0000B5B5
+#define DDRSS0_PHY_282_DATA 0x00000000
+#define DDRSS0_PHY_283_DATA 0x00000000
+#define DDRSS0_PHY_284_DATA 0x2A000000
+#define DDRSS0_PHY_285_DATA 0x00000808
+#define DDRSS0_PHY_286_DATA 0x0F000000
+#define DDRSS0_PHY_287_DATA 0x00000F08
+#define DDRSS0_PHY_288_DATA 0x10400000
+#define DDRSS0_PHY_289_DATA 0x0C002006
+#define DDRSS0_PHY_290_DATA 0x00000000
+#define DDRSS0_PHY_291_DATA 0x00000000
+#define DDRSS0_PHY_292_DATA 0x55555555
+#define DDRSS0_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_294_DATA 0x55555555
+#define DDRSS0_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_296_DATA 0x00005555
+#define DDRSS0_PHY_297_DATA 0x01000100
+#define DDRSS0_PHY_298_DATA 0x00800180
+#define DDRSS0_PHY_299_DATA 0x00000000
+#define DDRSS0_PHY_300_DATA 0x00000000
+#define DDRSS0_PHY_301_DATA 0x00000000
+#define DDRSS0_PHY_302_DATA 0x00000000
+#define DDRSS0_PHY_303_DATA 0x00000000
+#define DDRSS0_PHY_304_DATA 0x00000000
+#define DDRSS0_PHY_305_DATA 0x00000000
+#define DDRSS0_PHY_306_DATA 0x00000000
+#define DDRSS0_PHY_307_DATA 0x00000000
+#define DDRSS0_PHY_308_DATA 0x00000000
+#define DDRSS0_PHY_309_DATA 0x00000000
+#define DDRSS0_PHY_310_DATA 0x00000000
+#define DDRSS0_PHY_311_DATA 0x00000000
+#define DDRSS0_PHY_312_DATA 0x00000000
+#define DDRSS0_PHY_313_DATA 0x00000000
+#define DDRSS0_PHY_314_DATA 0x00000000
+#define DDRSS0_PHY_315_DATA 0x00000000
+#define DDRSS0_PHY_316_DATA 0x00000000
+#define DDRSS0_PHY_317_DATA 0x00000000
+#define DDRSS0_PHY_318_DATA 0x00000000
+#define DDRSS0_PHY_319_DATA 0x00000000
+#define DDRSS0_PHY_320_DATA 0x00000000
+#define DDRSS0_PHY_321_DATA 0x00000000
+#define DDRSS0_PHY_322_DATA 0x00000104
+#define DDRSS0_PHY_323_DATA 0x00000120
+#define DDRSS0_PHY_324_DATA 0x00000000
+#define DDRSS0_PHY_325_DATA 0x00000000
+#define DDRSS0_PHY_326_DATA 0x00000000
+#define DDRSS0_PHY_327_DATA 0x00000000
+#define DDRSS0_PHY_328_DATA 0x00000000
+#define DDRSS0_PHY_329_DATA 0x00000000
+#define DDRSS0_PHY_330_DATA 0x00000000
+#define DDRSS0_PHY_331_DATA 0x00000001
+#define DDRSS0_PHY_332_DATA 0x07FF0000
+#define DDRSS0_PHY_333_DATA 0x0080081F
+#define DDRSS0_PHY_334_DATA 0x00081020
+#define DDRSS0_PHY_335_DATA 0x04010000
+#define DDRSS0_PHY_336_DATA 0x00000000
+#define DDRSS0_PHY_337_DATA 0x00000000
+#define DDRSS0_PHY_338_DATA 0x00000000
+#define DDRSS0_PHY_339_DATA 0x00000100
+#define DDRSS0_PHY_340_DATA 0x01CC0C01
+#define DDRSS0_PHY_341_DATA 0x1003CC0C
+#define DDRSS0_PHY_342_DATA 0x20000140
+#define DDRSS0_PHY_343_DATA 0x07FF0200
+#define DDRSS0_PHY_344_DATA 0x0000DD01
+#define DDRSS0_PHY_345_DATA 0x10100303
+#define DDRSS0_PHY_346_DATA 0x10101010
+#define DDRSS0_PHY_347_DATA 0x10101010
+#define DDRSS0_PHY_348_DATA 0x00021010
+#define DDRSS0_PHY_349_DATA 0x00100010
+#define DDRSS0_PHY_350_DATA 0x00100010
+#define DDRSS0_PHY_351_DATA 0x00100010
+#define DDRSS0_PHY_352_DATA 0x00100010
+#define DDRSS0_PHY_353_DATA 0x00050010
+#define DDRSS0_PHY_354_DATA 0x51517041
+#define DDRSS0_PHY_355_DATA 0x31C06001
+#define DDRSS0_PHY_356_DATA 0x07AB01AB
+#define DDRSS0_PHY_357_DATA 0x00C0C001
+#define DDRSS0_PHY_358_DATA 0x0E0D0101
+#define DDRSS0_PHY_359_DATA 0x10001000
+#define DDRSS0_PHY_360_DATA 0x0C083E42
+#define DDRSS0_PHY_361_DATA 0x0F0C3701
+#define DDRSS0_PHY_362_DATA 0x01000140
+#define DDRSS0_PHY_363_DATA 0x0C000420
+#define DDRSS0_PHY_364_DATA 0x00000198
+#define DDRSS0_PHY_365_DATA 0x0A0000D0
+#define DDRSS0_PHY_366_DATA 0x00030200
+#define DDRSS0_PHY_367_DATA 0x02800000
+#define DDRSS0_PHY_368_DATA 0x80800000
+#define DDRSS0_PHY_369_DATA 0x000E2010
+#define DDRSS0_PHY_370_DATA 0x76543210
+#define DDRSS0_PHY_371_DATA 0x00000008
+#define DDRSS0_PHY_372_DATA 0x02800280
+#define DDRSS0_PHY_373_DATA 0x02800280
+#define DDRSS0_PHY_374_DATA 0x02800280
+#define DDRSS0_PHY_375_DATA 0x02800280
+#define DDRSS0_PHY_376_DATA 0x00000280
+#define DDRSS0_PHY_377_DATA 0x0000A000
+#define DDRSS0_PHY_378_DATA 0x00A000A0
+#define DDRSS0_PHY_379_DATA 0x00A000A0
+#define DDRSS0_PHY_380_DATA 0x00A000A0
+#define DDRSS0_PHY_381_DATA 0x00A000A0
+#define DDRSS0_PHY_382_DATA 0x00A000A0
+#define DDRSS0_PHY_383_DATA 0x00A000A0
+#define DDRSS0_PHY_384_DATA 0x00A000A0
+#define DDRSS0_PHY_385_DATA 0x00A000A0
+#define DDRSS0_PHY_386_DATA 0x01C200A0
+#define DDRSS0_PHY_387_DATA 0x01A00005
+#define DDRSS0_PHY_388_DATA 0x00000000
+#define DDRSS0_PHY_389_DATA 0x00000000
+#define DDRSS0_PHY_390_DATA 0x00080200
+#define DDRSS0_PHY_391_DATA 0x00000000
+#define DDRSS0_PHY_392_DATA 0x20202000
+#define DDRSS0_PHY_393_DATA 0x20202020
+#define DDRSS0_PHY_394_DATA 0xF0F02020
+#define DDRSS0_PHY_395_DATA 0x00000000
+#define DDRSS0_PHY_396_DATA 0x00000000
+#define DDRSS0_PHY_397_DATA 0x00000000
+#define DDRSS0_PHY_398_DATA 0x00000000
+#define DDRSS0_PHY_399_DATA 0x00000000
+#define DDRSS0_PHY_400_DATA 0x00000000
+#define DDRSS0_PHY_401_DATA 0x00000000
+#define DDRSS0_PHY_402_DATA 0x00000000
+#define DDRSS0_PHY_403_DATA 0x00000000
+#define DDRSS0_PHY_404_DATA 0x00000000
+#define DDRSS0_PHY_405_DATA 0x00000000
+#define DDRSS0_PHY_406_DATA 0x00000000
+#define DDRSS0_PHY_407_DATA 0x00000000
+#define DDRSS0_PHY_408_DATA 0x00000000
+#define DDRSS0_PHY_409_DATA 0x00000000
+#define DDRSS0_PHY_410_DATA 0x00000000
+#define DDRSS0_PHY_411_DATA 0x00000000
+#define DDRSS0_PHY_412_DATA 0x00000000
+#define DDRSS0_PHY_413_DATA 0x00000000
+#define DDRSS0_PHY_414_DATA 0x00000000
+#define DDRSS0_PHY_415_DATA 0x00000000
+#define DDRSS0_PHY_416_DATA 0x00000000
+#define DDRSS0_PHY_417_DATA 0x00000000
+#define DDRSS0_PHY_418_DATA 0x00000000
+#define DDRSS0_PHY_419_DATA 0x00000000
+#define DDRSS0_PHY_420_DATA 0x00000000
+#define DDRSS0_PHY_421_DATA 0x00000000
+#define DDRSS0_PHY_422_DATA 0x00000000
+#define DDRSS0_PHY_423_DATA 0x00000000
+#define DDRSS0_PHY_424_DATA 0x00000000
+#define DDRSS0_PHY_425_DATA 0x00000000
+#define DDRSS0_PHY_426_DATA 0x00000000
+#define DDRSS0_PHY_427_DATA 0x00000000
+#define DDRSS0_PHY_428_DATA 0x00000000
+#define DDRSS0_PHY_429_DATA 0x00000000
+#define DDRSS0_PHY_430_DATA 0x00000000
+#define DDRSS0_PHY_431_DATA 0x00000000
+#define DDRSS0_PHY_432_DATA 0x00000000
+#define DDRSS0_PHY_433_DATA 0x00000000
+#define DDRSS0_PHY_434_DATA 0x00000000
+#define DDRSS0_PHY_435_DATA 0x00000000
+#define DDRSS0_PHY_436_DATA 0x00000000
+#define DDRSS0_PHY_437_DATA 0x00000000
+#define DDRSS0_PHY_438_DATA 0x00000000
+#define DDRSS0_PHY_439_DATA 0x00000000
+#define DDRSS0_PHY_440_DATA 0x00000000
+#define DDRSS0_PHY_441_DATA 0x00000000
+#define DDRSS0_PHY_442_DATA 0x00000000
+#define DDRSS0_PHY_443_DATA 0x00000000
+#define DDRSS0_PHY_444_DATA 0x00000000
+#define DDRSS0_PHY_445_DATA 0x00000000
+#define DDRSS0_PHY_446_DATA 0x00000000
+#define DDRSS0_PHY_447_DATA 0x00000000
+#define DDRSS0_PHY_448_DATA 0x00000000
+#define DDRSS0_PHY_449_DATA 0x00000000
+#define DDRSS0_PHY_450_DATA 0x00000000
+#define DDRSS0_PHY_451_DATA 0x00000000
+#define DDRSS0_PHY_452_DATA 0x00000000
+#define DDRSS0_PHY_453_DATA 0x00000000
+#define DDRSS0_PHY_454_DATA 0x00000000
+#define DDRSS0_PHY_455_DATA 0x00000000
+#define DDRSS0_PHY_456_DATA 0x00000000
+#define DDRSS0_PHY_457_DATA 0x00000000
+#define DDRSS0_PHY_458_DATA 0x00000000
+#define DDRSS0_PHY_459_DATA 0x00000000
+#define DDRSS0_PHY_460_DATA 0x00000000
+#define DDRSS0_PHY_461_DATA 0x00000000
+#define DDRSS0_PHY_462_DATA 0x00000000
+#define DDRSS0_PHY_463_DATA 0x00000000
+#define DDRSS0_PHY_464_DATA 0x00000000
+#define DDRSS0_PHY_465_DATA 0x00000000
+#define DDRSS0_PHY_466_DATA 0x00000000
+#define DDRSS0_PHY_467_DATA 0x00000000
+#define DDRSS0_PHY_468_DATA 0x00000000
+#define DDRSS0_PHY_469_DATA 0x00000000
+#define DDRSS0_PHY_470_DATA 0x00000000
+#define DDRSS0_PHY_471_DATA 0x00000000
+#define DDRSS0_PHY_472_DATA 0x00000000
+#define DDRSS0_PHY_473_DATA 0x00000000
+#define DDRSS0_PHY_474_DATA 0x00000000
+#define DDRSS0_PHY_475_DATA 0x00000000
+#define DDRSS0_PHY_476_DATA 0x00000000
+#define DDRSS0_PHY_477_DATA 0x00000000
+#define DDRSS0_PHY_478_DATA 0x00000000
+#define DDRSS0_PHY_479_DATA 0x00000000
+#define DDRSS0_PHY_480_DATA 0x00000000
+#define DDRSS0_PHY_481_DATA 0x00000000
+#define DDRSS0_PHY_482_DATA 0x00000000
+#define DDRSS0_PHY_483_DATA 0x00000000
+#define DDRSS0_PHY_484_DATA 0x00000000
+#define DDRSS0_PHY_485_DATA 0x00000000
+#define DDRSS0_PHY_486_DATA 0x00000000
+#define DDRSS0_PHY_487_DATA 0x00000000
+#define DDRSS0_PHY_488_DATA 0x00000000
+#define DDRSS0_PHY_489_DATA 0x00000000
+#define DDRSS0_PHY_490_DATA 0x00000000
+#define DDRSS0_PHY_491_DATA 0x00000000
+#define DDRSS0_PHY_492_DATA 0x00000000
+#define DDRSS0_PHY_493_DATA 0x00000000
+#define DDRSS0_PHY_494_DATA 0x00000000
+#define DDRSS0_PHY_495_DATA 0x00000000
+#define DDRSS0_PHY_496_DATA 0x00000000
+#define DDRSS0_PHY_497_DATA 0x00000000
+#define DDRSS0_PHY_498_DATA 0x00000000
+#define DDRSS0_PHY_499_DATA 0x00000000
+#define DDRSS0_PHY_500_DATA 0x00000000
+#define DDRSS0_PHY_501_DATA 0x00000000
+#define DDRSS0_PHY_502_DATA 0x00000000
+#define DDRSS0_PHY_503_DATA 0x00000000
+#define DDRSS0_PHY_504_DATA 0x00000000
+#define DDRSS0_PHY_505_DATA 0x00000000
+#define DDRSS0_PHY_506_DATA 0x00000000
+#define DDRSS0_PHY_507_DATA 0x00000000
+#define DDRSS0_PHY_508_DATA 0x00000000
+#define DDRSS0_PHY_509_DATA 0x00000000
+#define DDRSS0_PHY_510_DATA 0x00000000
+#define DDRSS0_PHY_511_DATA 0x00000000
+#define DDRSS0_PHY_512_DATA 0x000004F0
+#define DDRSS0_PHY_513_DATA 0x00000000
+#define DDRSS0_PHY_514_DATA 0x00030200
+#define DDRSS0_PHY_515_DATA 0x00000000
+#define DDRSS0_PHY_516_DATA 0x00000000
+#define DDRSS0_PHY_517_DATA 0x01030000
+#define DDRSS0_PHY_518_DATA 0x00010000
+#define DDRSS0_PHY_519_DATA 0x01030004
+#define DDRSS0_PHY_520_DATA 0x01000000
+#define DDRSS0_PHY_521_DATA 0x00000000
+#define DDRSS0_PHY_522_DATA 0x00000000
+#define DDRSS0_PHY_523_DATA 0x01000001
+#define DDRSS0_PHY_524_DATA 0x00000200
+#define DDRSS0_PHY_525_DATA 0x000800C0
+#define DDRSS0_PHY_526_DATA 0x060100CC
+#define DDRSS0_PHY_527_DATA 0x00030066
+#define DDRSS0_PHY_528_DATA 0x00000000
+#define DDRSS0_PHY_529_DATA 0x00000301
+#define DDRSS0_PHY_530_DATA 0x0000AAAA
+#define DDRSS0_PHY_531_DATA 0x00005555
+#define DDRSS0_PHY_532_DATA 0x0000B5B5
+#define DDRSS0_PHY_533_DATA 0x00004A4A
+#define DDRSS0_PHY_534_DATA 0x00005656
+#define DDRSS0_PHY_535_DATA 0x0000A9A9
+#define DDRSS0_PHY_536_DATA 0x0000A9A9
+#define DDRSS0_PHY_537_DATA 0x0000B5B5
+#define DDRSS0_PHY_538_DATA 0x00000000
+#define DDRSS0_PHY_539_DATA 0x00000000
+#define DDRSS0_PHY_540_DATA 0x2A000000
+#define DDRSS0_PHY_541_DATA 0x00000808
+#define DDRSS0_PHY_542_DATA 0x0F000000
+#define DDRSS0_PHY_543_DATA 0x00000F08
+#define DDRSS0_PHY_544_DATA 0x10400000
+#define DDRSS0_PHY_545_DATA 0x0C002006
+#define DDRSS0_PHY_546_DATA 0x00000000
+#define DDRSS0_PHY_547_DATA 0x00000000
+#define DDRSS0_PHY_548_DATA 0x55555555
+#define DDRSS0_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_550_DATA 0x55555555
+#define DDRSS0_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_552_DATA 0x00005555
+#define DDRSS0_PHY_553_DATA 0x01000100
+#define DDRSS0_PHY_554_DATA 0x00800180
+#define DDRSS0_PHY_555_DATA 0x00000001
+#define DDRSS0_PHY_556_DATA 0x00000000
+#define DDRSS0_PHY_557_DATA 0x00000000
+#define DDRSS0_PHY_558_DATA 0x00000000
+#define DDRSS0_PHY_559_DATA 0x00000000
+#define DDRSS0_PHY_560_DATA 0x00000000
+#define DDRSS0_PHY_561_DATA 0x00000000
+#define DDRSS0_PHY_562_DATA 0x00000000
+#define DDRSS0_PHY_563_DATA 0x00000000
+#define DDRSS0_PHY_564_DATA 0x00000000
+#define DDRSS0_PHY_565_DATA 0x00000000
+#define DDRSS0_PHY_566_DATA 0x00000000
+#define DDRSS0_PHY_567_DATA 0x00000000
+#define DDRSS0_PHY_568_DATA 0x00000000
+#define DDRSS0_PHY_569_DATA 0x00000000
+#define DDRSS0_PHY_570_DATA 0x00000000
+#define DDRSS0_PHY_571_DATA 0x00000000
+#define DDRSS0_PHY_572_DATA 0x00000000
+#define DDRSS0_PHY_573_DATA 0x00000000
+#define DDRSS0_PHY_574_DATA 0x00000000
+#define DDRSS0_PHY_575_DATA 0x00000000
+#define DDRSS0_PHY_576_DATA 0x00000000
+#define DDRSS0_PHY_577_DATA 0x00000000
+#define DDRSS0_PHY_578_DATA 0x00000104
+#define DDRSS0_PHY_579_DATA 0x00000120
+#define DDRSS0_PHY_580_DATA 0x00000000
+#define DDRSS0_PHY_581_DATA 0x00000000
+#define DDRSS0_PHY_582_DATA 0x00000000
+#define DDRSS0_PHY_583_DATA 0x00000000
+#define DDRSS0_PHY_584_DATA 0x00000000
+#define DDRSS0_PHY_585_DATA 0x00000000
+#define DDRSS0_PHY_586_DATA 0x00000000
+#define DDRSS0_PHY_587_DATA 0x00000001
+#define DDRSS0_PHY_588_DATA 0x07FF0000
+#define DDRSS0_PHY_589_DATA 0x0080081F
+#define DDRSS0_PHY_590_DATA 0x00081020
+#define DDRSS0_PHY_591_DATA 0x04010000
+#define DDRSS0_PHY_592_DATA 0x00000000
+#define DDRSS0_PHY_593_DATA 0x00000000
+#define DDRSS0_PHY_594_DATA 0x00000000
+#define DDRSS0_PHY_595_DATA 0x00000100
+#define DDRSS0_PHY_596_DATA 0x01CC0C01
+#define DDRSS0_PHY_597_DATA 0x1003CC0C
+#define DDRSS0_PHY_598_DATA 0x20000140
+#define DDRSS0_PHY_599_DATA 0x07FF0200
+#define DDRSS0_PHY_600_DATA 0x0000DD01
+#define DDRSS0_PHY_601_DATA 0x10100303
+#define DDRSS0_PHY_602_DATA 0x10101010
+#define DDRSS0_PHY_603_DATA 0x10101010
+#define DDRSS0_PHY_604_DATA 0x00021010
+#define DDRSS0_PHY_605_DATA 0x00100010
+#define DDRSS0_PHY_606_DATA 0x00100010
+#define DDRSS0_PHY_607_DATA 0x00100010
+#define DDRSS0_PHY_608_DATA 0x00100010
+#define DDRSS0_PHY_609_DATA 0x00050010
+#define DDRSS0_PHY_610_DATA 0x51517041
+#define DDRSS0_PHY_611_DATA 0x31C06001
+#define DDRSS0_PHY_612_DATA 0x07AB01AB
+#define DDRSS0_PHY_613_DATA 0x00C0C001
+#define DDRSS0_PHY_614_DATA 0x0E0D0101
+#define DDRSS0_PHY_615_DATA 0x10001000
+#define DDRSS0_PHY_616_DATA 0x0C083E42
+#define DDRSS0_PHY_617_DATA 0x0F0C3701
+#define DDRSS0_PHY_618_DATA 0x01000140
+#define DDRSS0_PHY_619_DATA 0x0C000420
+#define DDRSS0_PHY_620_DATA 0x00000198
+#define DDRSS0_PHY_621_DATA 0x0A0000D0
+#define DDRSS0_PHY_622_DATA 0x00030200
+#define DDRSS0_PHY_623_DATA 0x02800000
+#define DDRSS0_PHY_624_DATA 0x80800000
+#define DDRSS0_PHY_625_DATA 0x000E2010
+#define DDRSS0_PHY_626_DATA 0x76543210
+#define DDRSS0_PHY_627_DATA 0x00000008
+#define DDRSS0_PHY_628_DATA 0x02800280
+#define DDRSS0_PHY_629_DATA 0x02800280
+#define DDRSS0_PHY_630_DATA 0x02800280
+#define DDRSS0_PHY_631_DATA 0x02800280
+#define DDRSS0_PHY_632_DATA 0x00000280
+#define DDRSS0_PHY_633_DATA 0x0000A000
+#define DDRSS0_PHY_634_DATA 0x00A000A0
+#define DDRSS0_PHY_635_DATA 0x00A000A0
+#define DDRSS0_PHY_636_DATA 0x00A000A0
+#define DDRSS0_PHY_637_DATA 0x00A000A0
+#define DDRSS0_PHY_638_DATA 0x00A000A0
+#define DDRSS0_PHY_639_DATA 0x00A000A0
+#define DDRSS0_PHY_640_DATA 0x00A000A0
+#define DDRSS0_PHY_641_DATA 0x00A000A0
+#define DDRSS0_PHY_642_DATA 0x01C200A0
+#define DDRSS0_PHY_643_DATA 0x01A00005
+#define DDRSS0_PHY_644_DATA 0x00000000
+#define DDRSS0_PHY_645_DATA 0x00000000
+#define DDRSS0_PHY_646_DATA 0x00080200
+#define DDRSS0_PHY_647_DATA 0x00000000
+#define DDRSS0_PHY_648_DATA 0x20202000
+#define DDRSS0_PHY_649_DATA 0x20202020
+#define DDRSS0_PHY_650_DATA 0xF0F02020
+#define DDRSS0_PHY_651_DATA 0x00000000
+#define DDRSS0_PHY_652_DATA 0x00000000
+#define DDRSS0_PHY_653_DATA 0x00000000
+#define DDRSS0_PHY_654_DATA 0x00000000
+#define DDRSS0_PHY_655_DATA 0x00000000
+#define DDRSS0_PHY_656_DATA 0x00000000
+#define DDRSS0_PHY_657_DATA 0x00000000
+#define DDRSS0_PHY_658_DATA 0x00000000
+#define DDRSS0_PHY_659_DATA 0x00000000
+#define DDRSS0_PHY_660_DATA 0x00000000
+#define DDRSS0_PHY_661_DATA 0x00000000
+#define DDRSS0_PHY_662_DATA 0x00000000
+#define DDRSS0_PHY_663_DATA 0x00000000
+#define DDRSS0_PHY_664_DATA 0x00000000
+#define DDRSS0_PHY_665_DATA 0x00000000
+#define DDRSS0_PHY_666_DATA 0x00000000
+#define DDRSS0_PHY_667_DATA 0x00000000
+#define DDRSS0_PHY_668_DATA 0x00000000
+#define DDRSS0_PHY_669_DATA 0x00000000
+#define DDRSS0_PHY_670_DATA 0x00000000
+#define DDRSS0_PHY_671_DATA 0x00000000
+#define DDRSS0_PHY_672_DATA 0x00000000
+#define DDRSS0_PHY_673_DATA 0x00000000
+#define DDRSS0_PHY_674_DATA 0x00000000
+#define DDRSS0_PHY_675_DATA 0x00000000
+#define DDRSS0_PHY_676_DATA 0x00000000
+#define DDRSS0_PHY_677_DATA 0x00000000
+#define DDRSS0_PHY_678_DATA 0x00000000
+#define DDRSS0_PHY_679_DATA 0x00000000
+#define DDRSS0_PHY_680_DATA 0x00000000
+#define DDRSS0_PHY_681_DATA 0x00000000
+#define DDRSS0_PHY_682_DATA 0x00000000
+#define DDRSS0_PHY_683_DATA 0x00000000
+#define DDRSS0_PHY_684_DATA 0x00000000
+#define DDRSS0_PHY_685_DATA 0x00000000
+#define DDRSS0_PHY_686_DATA 0x00000000
+#define DDRSS0_PHY_687_DATA 0x00000000
+#define DDRSS0_PHY_688_DATA 0x00000000
+#define DDRSS0_PHY_689_DATA 0x00000000
+#define DDRSS0_PHY_690_DATA 0x00000000
+#define DDRSS0_PHY_691_DATA 0x00000000
+#define DDRSS0_PHY_692_DATA 0x00000000
+#define DDRSS0_PHY_693_DATA 0x00000000
+#define DDRSS0_PHY_694_DATA 0x00000000
+#define DDRSS0_PHY_695_DATA 0x00000000
+#define DDRSS0_PHY_696_DATA 0x00000000
+#define DDRSS0_PHY_697_DATA 0x00000000
+#define DDRSS0_PHY_698_DATA 0x00000000
+#define DDRSS0_PHY_699_DATA 0x00000000
+#define DDRSS0_PHY_700_DATA 0x00000000
+#define DDRSS0_PHY_701_DATA 0x00000000
+#define DDRSS0_PHY_702_DATA 0x00000000
+#define DDRSS0_PHY_703_DATA 0x00000000
+#define DDRSS0_PHY_704_DATA 0x00000000
+#define DDRSS0_PHY_705_DATA 0x00000000
+#define DDRSS0_PHY_706_DATA 0x00000000
+#define DDRSS0_PHY_707_DATA 0x00000000
+#define DDRSS0_PHY_708_DATA 0x00000000
+#define DDRSS0_PHY_709_DATA 0x00000000
+#define DDRSS0_PHY_710_DATA 0x00000000
+#define DDRSS0_PHY_711_DATA 0x00000000
+#define DDRSS0_PHY_712_DATA 0x00000000
+#define DDRSS0_PHY_713_DATA 0x00000000
+#define DDRSS0_PHY_714_DATA 0x00000000
+#define DDRSS0_PHY_715_DATA 0x00000000
+#define DDRSS0_PHY_716_DATA 0x00000000
+#define DDRSS0_PHY_717_DATA 0x00000000
+#define DDRSS0_PHY_718_DATA 0x00000000
+#define DDRSS0_PHY_719_DATA 0x00000000
+#define DDRSS0_PHY_720_DATA 0x00000000
+#define DDRSS0_PHY_721_DATA 0x00000000
+#define DDRSS0_PHY_722_DATA 0x00000000
+#define DDRSS0_PHY_723_DATA 0x00000000
+#define DDRSS0_PHY_724_DATA 0x00000000
+#define DDRSS0_PHY_725_DATA 0x00000000
+#define DDRSS0_PHY_726_DATA 0x00000000
+#define DDRSS0_PHY_727_DATA 0x00000000
+#define DDRSS0_PHY_728_DATA 0x00000000
+#define DDRSS0_PHY_729_DATA 0x00000000
+#define DDRSS0_PHY_730_DATA 0x00000000
+#define DDRSS0_PHY_731_DATA 0x00000000
+#define DDRSS0_PHY_732_DATA 0x00000000
+#define DDRSS0_PHY_733_DATA 0x00000000
+#define DDRSS0_PHY_734_DATA 0x00000000
+#define DDRSS0_PHY_735_DATA 0x00000000
+#define DDRSS0_PHY_736_DATA 0x00000000
+#define DDRSS0_PHY_737_DATA 0x00000000
+#define DDRSS0_PHY_738_DATA 0x00000000
+#define DDRSS0_PHY_739_DATA 0x00000000
+#define DDRSS0_PHY_740_DATA 0x00000000
+#define DDRSS0_PHY_741_DATA 0x00000000
+#define DDRSS0_PHY_742_DATA 0x00000000
+#define DDRSS0_PHY_743_DATA 0x00000000
+#define DDRSS0_PHY_744_DATA 0x00000000
+#define DDRSS0_PHY_745_DATA 0x00000000
+#define DDRSS0_PHY_746_DATA 0x00000000
+#define DDRSS0_PHY_747_DATA 0x00000000
+#define DDRSS0_PHY_748_DATA 0x00000000
+#define DDRSS0_PHY_749_DATA 0x00000000
+#define DDRSS0_PHY_750_DATA 0x00000000
+#define DDRSS0_PHY_751_DATA 0x00000000
+#define DDRSS0_PHY_752_DATA 0x00000000
+#define DDRSS0_PHY_753_DATA 0x00000000
+#define DDRSS0_PHY_754_DATA 0x00000000
+#define DDRSS0_PHY_755_DATA 0x00000000
+#define DDRSS0_PHY_756_DATA 0x00000000
+#define DDRSS0_PHY_757_DATA 0x00000000
+#define DDRSS0_PHY_758_DATA 0x00000000
+#define DDRSS0_PHY_759_DATA 0x00000000
+#define DDRSS0_PHY_760_DATA 0x00000000
+#define DDRSS0_PHY_761_DATA 0x00000000
+#define DDRSS0_PHY_762_DATA 0x00000000
+#define DDRSS0_PHY_763_DATA 0x00000000
+#define DDRSS0_PHY_764_DATA 0x00000000
+#define DDRSS0_PHY_765_DATA 0x00000000
+#define DDRSS0_PHY_766_DATA 0x00000000
+#define DDRSS0_PHY_767_DATA 0x00000000
+#define DDRSS0_PHY_768_DATA 0x000004F0
+#define DDRSS0_PHY_769_DATA 0x00000000
+#define DDRSS0_PHY_770_DATA 0x00030200
+#define DDRSS0_PHY_771_DATA 0x00000000
+#define DDRSS0_PHY_772_DATA 0x00000000
+#define DDRSS0_PHY_773_DATA 0x01030000
+#define DDRSS0_PHY_774_DATA 0x00010000
+#define DDRSS0_PHY_775_DATA 0x01030004
+#define DDRSS0_PHY_776_DATA 0x01000000
+#define DDRSS0_PHY_777_DATA 0x00000000
+#define DDRSS0_PHY_778_DATA 0x00000000
+#define DDRSS0_PHY_779_DATA 0x01000001
+#define DDRSS0_PHY_780_DATA 0x00000200
+#define DDRSS0_PHY_781_DATA 0x000800C0
+#define DDRSS0_PHY_782_DATA 0x060100CC
+#define DDRSS0_PHY_783_DATA 0x00030066
+#define DDRSS0_PHY_784_DATA 0x00000000
+#define DDRSS0_PHY_785_DATA 0x00000301
+#define DDRSS0_PHY_786_DATA 0x0000AAAA
+#define DDRSS0_PHY_787_DATA 0x00005555
+#define DDRSS0_PHY_788_DATA 0x0000B5B5
+#define DDRSS0_PHY_789_DATA 0x00004A4A
+#define DDRSS0_PHY_790_DATA 0x00005656
+#define DDRSS0_PHY_791_DATA 0x0000A9A9
+#define DDRSS0_PHY_792_DATA 0x0000A9A9
+#define DDRSS0_PHY_793_DATA 0x0000B5B5
+#define DDRSS0_PHY_794_DATA 0x00000000
+#define DDRSS0_PHY_795_DATA 0x00000000
+#define DDRSS0_PHY_796_DATA 0x2A000000
+#define DDRSS0_PHY_797_DATA 0x00000808
+#define DDRSS0_PHY_798_DATA 0x0F000000
+#define DDRSS0_PHY_799_DATA 0x00000F08
+#define DDRSS0_PHY_800_DATA 0x10400000
+#define DDRSS0_PHY_801_DATA 0x0C002006
+#define DDRSS0_PHY_802_DATA 0x00000000
+#define DDRSS0_PHY_803_DATA 0x00000000
+#define DDRSS0_PHY_804_DATA 0x55555555
+#define DDRSS0_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_806_DATA 0x55555555
+#define DDRSS0_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_808_DATA 0x00005555
+#define DDRSS0_PHY_809_DATA 0x01000100
+#define DDRSS0_PHY_810_DATA 0x00800180
+#define DDRSS0_PHY_811_DATA 0x00000000
+#define DDRSS0_PHY_812_DATA 0x00000000
+#define DDRSS0_PHY_813_DATA 0x00000000
+#define DDRSS0_PHY_814_DATA 0x00000000
+#define DDRSS0_PHY_815_DATA 0x00000000
+#define DDRSS0_PHY_816_DATA 0x00000000
+#define DDRSS0_PHY_817_DATA 0x00000000
+#define DDRSS0_PHY_818_DATA 0x00000000
+#define DDRSS0_PHY_819_DATA 0x00000000
+#define DDRSS0_PHY_820_DATA 0x00000000
+#define DDRSS0_PHY_821_DATA 0x00000000
+#define DDRSS0_PHY_822_DATA 0x00000000
+#define DDRSS0_PHY_823_DATA 0x00000000
+#define DDRSS0_PHY_824_DATA 0x00000000
+#define DDRSS0_PHY_825_DATA 0x00000000
+#define DDRSS0_PHY_826_DATA 0x00000000
+#define DDRSS0_PHY_827_DATA 0x00000000
+#define DDRSS0_PHY_828_DATA 0x00000000
+#define DDRSS0_PHY_829_DATA 0x00000000
+#define DDRSS0_PHY_830_DATA 0x00000000
+#define DDRSS0_PHY_831_DATA 0x00000000
+#define DDRSS0_PHY_832_DATA 0x00000000
+#define DDRSS0_PHY_833_DATA 0x00000000
+#define DDRSS0_PHY_834_DATA 0x00000104
+#define DDRSS0_PHY_835_DATA 0x00000120
+#define DDRSS0_PHY_836_DATA 0x00000000
+#define DDRSS0_PHY_837_DATA 0x00000000
+#define DDRSS0_PHY_838_DATA 0x00000000
+#define DDRSS0_PHY_839_DATA 0x00000000
+#define DDRSS0_PHY_840_DATA 0x00000000
+#define DDRSS0_PHY_841_DATA 0x00000000
+#define DDRSS0_PHY_842_DATA 0x00000000
+#define DDRSS0_PHY_843_DATA 0x00000001
+#define DDRSS0_PHY_844_DATA 0x07FF0000
+#define DDRSS0_PHY_845_DATA 0x0080081F
+#define DDRSS0_PHY_846_DATA 0x00081020
+#define DDRSS0_PHY_847_DATA 0x04010000
+#define DDRSS0_PHY_848_DATA 0x00000000
+#define DDRSS0_PHY_849_DATA 0x00000000
+#define DDRSS0_PHY_850_DATA 0x00000000
+#define DDRSS0_PHY_851_DATA 0x00000100
+#define DDRSS0_PHY_852_DATA 0x01CC0C01
+#define DDRSS0_PHY_853_DATA 0x1003CC0C
+#define DDRSS0_PHY_854_DATA 0x20000140
+#define DDRSS0_PHY_855_DATA 0x07FF0200
+#define DDRSS0_PHY_856_DATA 0x0000DD01
+#define DDRSS0_PHY_857_DATA 0x10100303
+#define DDRSS0_PHY_858_DATA 0x10101010
+#define DDRSS0_PHY_859_DATA 0x10101010
+#define DDRSS0_PHY_860_DATA 0x00021010
+#define DDRSS0_PHY_861_DATA 0x00100010
+#define DDRSS0_PHY_862_DATA 0x00100010
+#define DDRSS0_PHY_863_DATA 0x00100010
+#define DDRSS0_PHY_864_DATA 0x00100010
+#define DDRSS0_PHY_865_DATA 0x00050010
+#define DDRSS0_PHY_866_DATA 0x51517041
+#define DDRSS0_PHY_867_DATA 0x31C06001
+#define DDRSS0_PHY_868_DATA 0x07AB01AB
+#define DDRSS0_PHY_869_DATA 0x00C0C001
+#define DDRSS0_PHY_870_DATA 0x0E0D0101
+#define DDRSS0_PHY_871_DATA 0x10001000
+#define DDRSS0_PHY_872_DATA 0x0C083E42
+#define DDRSS0_PHY_873_DATA 0x0F0C3701
+#define DDRSS0_PHY_874_DATA 0x01000140
+#define DDRSS0_PHY_875_DATA 0x0C000420
+#define DDRSS0_PHY_876_DATA 0x00000198
+#define DDRSS0_PHY_877_DATA 0x0A0000D0
+#define DDRSS0_PHY_878_DATA 0x00030200
+#define DDRSS0_PHY_879_DATA 0x02800000
+#define DDRSS0_PHY_880_DATA 0x80800000
+#define DDRSS0_PHY_881_DATA 0x000E2010
+#define DDRSS0_PHY_882_DATA 0x76543210
+#define DDRSS0_PHY_883_DATA 0x00000008
+#define DDRSS0_PHY_884_DATA 0x02800280
+#define DDRSS0_PHY_885_DATA 0x02800280
+#define DDRSS0_PHY_886_DATA 0x02800280
+#define DDRSS0_PHY_887_DATA 0x02800280
+#define DDRSS0_PHY_888_DATA 0x00000280
+#define DDRSS0_PHY_889_DATA 0x0000A000
+#define DDRSS0_PHY_890_DATA 0x00A000A0
+#define DDRSS0_PHY_891_DATA 0x00A000A0
+#define DDRSS0_PHY_892_DATA 0x00A000A0
+#define DDRSS0_PHY_893_DATA 0x00A000A0
+#define DDRSS0_PHY_894_DATA 0x00A000A0
+#define DDRSS0_PHY_895_DATA 0x00A000A0
+#define DDRSS0_PHY_896_DATA 0x00A000A0
+#define DDRSS0_PHY_897_DATA 0x00A000A0
+#define DDRSS0_PHY_898_DATA 0x01C200A0
+#define DDRSS0_PHY_899_DATA 0x01A00005
+#define DDRSS0_PHY_900_DATA 0x00000000
+#define DDRSS0_PHY_901_DATA 0x00000000
+#define DDRSS0_PHY_902_DATA 0x00080200
+#define DDRSS0_PHY_903_DATA 0x00000000
+#define DDRSS0_PHY_904_DATA 0x20202000
+#define DDRSS0_PHY_905_DATA 0x20202020
+#define DDRSS0_PHY_906_DATA 0xF0F02020
+#define DDRSS0_PHY_907_DATA 0x00000000
+#define DDRSS0_PHY_908_DATA 0x00000000
+#define DDRSS0_PHY_909_DATA 0x00000000
+#define DDRSS0_PHY_910_DATA 0x00000000
+#define DDRSS0_PHY_911_DATA 0x00000000
+#define DDRSS0_PHY_912_DATA 0x00000000
+#define DDRSS0_PHY_913_DATA 0x00000000
+#define DDRSS0_PHY_914_DATA 0x00000000
+#define DDRSS0_PHY_915_DATA 0x00000000
+#define DDRSS0_PHY_916_DATA 0x00000000
+#define DDRSS0_PHY_917_DATA 0x00000000
+#define DDRSS0_PHY_918_DATA 0x00000000
+#define DDRSS0_PHY_919_DATA 0x00000000
+#define DDRSS0_PHY_920_DATA 0x00000000
+#define DDRSS0_PHY_921_DATA 0x00000000
+#define DDRSS0_PHY_922_DATA 0x00000000
+#define DDRSS0_PHY_923_DATA 0x00000000
+#define DDRSS0_PHY_924_DATA 0x00000000
+#define DDRSS0_PHY_925_DATA 0x00000000
+#define DDRSS0_PHY_926_DATA 0x00000000
+#define DDRSS0_PHY_927_DATA 0x00000000
+#define DDRSS0_PHY_928_DATA 0x00000000
+#define DDRSS0_PHY_929_DATA 0x00000000
+#define DDRSS0_PHY_930_DATA 0x00000000
+#define DDRSS0_PHY_931_DATA 0x00000000
+#define DDRSS0_PHY_932_DATA 0x00000000
+#define DDRSS0_PHY_933_DATA 0x00000000
+#define DDRSS0_PHY_934_DATA 0x00000000
+#define DDRSS0_PHY_935_DATA 0x00000000
+#define DDRSS0_PHY_936_DATA 0x00000000
+#define DDRSS0_PHY_937_DATA 0x00000000
+#define DDRSS0_PHY_938_DATA 0x00000000
+#define DDRSS0_PHY_939_DATA 0x00000000
+#define DDRSS0_PHY_940_DATA 0x00000000
+#define DDRSS0_PHY_941_DATA 0x00000000
+#define DDRSS0_PHY_942_DATA 0x00000000
+#define DDRSS0_PHY_943_DATA 0x00000000
+#define DDRSS0_PHY_944_DATA 0x00000000
+#define DDRSS0_PHY_945_DATA 0x00000000
+#define DDRSS0_PHY_946_DATA 0x00000000
+#define DDRSS0_PHY_947_DATA 0x00000000
+#define DDRSS0_PHY_948_DATA 0x00000000
+#define DDRSS0_PHY_949_DATA 0x00000000
+#define DDRSS0_PHY_950_DATA 0x00000000
+#define DDRSS0_PHY_951_DATA 0x00000000
+#define DDRSS0_PHY_952_DATA 0x00000000
+#define DDRSS0_PHY_953_DATA 0x00000000
+#define DDRSS0_PHY_954_DATA 0x00000000
+#define DDRSS0_PHY_955_DATA 0x00000000
+#define DDRSS0_PHY_956_DATA 0x00000000
+#define DDRSS0_PHY_957_DATA 0x00000000
+#define DDRSS0_PHY_958_DATA 0x00000000
+#define DDRSS0_PHY_959_DATA 0x00000000
+#define DDRSS0_PHY_960_DATA 0x00000000
+#define DDRSS0_PHY_961_DATA 0x00000000
+#define DDRSS0_PHY_962_DATA 0x00000000
+#define DDRSS0_PHY_963_DATA 0x00000000
+#define DDRSS0_PHY_964_DATA 0x00000000
+#define DDRSS0_PHY_965_DATA 0x00000000
+#define DDRSS0_PHY_966_DATA 0x00000000
+#define DDRSS0_PHY_967_DATA 0x00000000
+#define DDRSS0_PHY_968_DATA 0x00000000
+#define DDRSS0_PHY_969_DATA 0x00000000
+#define DDRSS0_PHY_970_DATA 0x00000000
+#define DDRSS0_PHY_971_DATA 0x00000000
+#define DDRSS0_PHY_972_DATA 0x00000000
+#define DDRSS0_PHY_973_DATA 0x00000000
+#define DDRSS0_PHY_974_DATA 0x00000000
+#define DDRSS0_PHY_975_DATA 0x00000000
+#define DDRSS0_PHY_976_DATA 0x00000000
+#define DDRSS0_PHY_977_DATA 0x00000000
+#define DDRSS0_PHY_978_DATA 0x00000000
+#define DDRSS0_PHY_979_DATA 0x00000000
+#define DDRSS0_PHY_980_DATA 0x00000000
+#define DDRSS0_PHY_981_DATA 0x00000000
+#define DDRSS0_PHY_982_DATA 0x00000000
+#define DDRSS0_PHY_983_DATA 0x00000000
+#define DDRSS0_PHY_984_DATA 0x00000000
+#define DDRSS0_PHY_985_DATA 0x00000000
+#define DDRSS0_PHY_986_DATA 0x00000000
+#define DDRSS0_PHY_987_DATA 0x00000000
+#define DDRSS0_PHY_988_DATA 0x00000000
+#define DDRSS0_PHY_989_DATA 0x00000000
+#define DDRSS0_PHY_990_DATA 0x00000000
+#define DDRSS0_PHY_991_DATA 0x00000000
+#define DDRSS0_PHY_992_DATA 0x00000000
+#define DDRSS0_PHY_993_DATA 0x00000000
+#define DDRSS0_PHY_994_DATA 0x00000000
+#define DDRSS0_PHY_995_DATA 0x00000000
+#define DDRSS0_PHY_996_DATA 0x00000000
+#define DDRSS0_PHY_997_DATA 0x00000000
+#define DDRSS0_PHY_998_DATA 0x00000000
+#define DDRSS0_PHY_999_DATA 0x00000000
+#define DDRSS0_PHY_1000_DATA 0x00000000
+#define DDRSS0_PHY_1001_DATA 0x00000000
+#define DDRSS0_PHY_1002_DATA 0x00000000
+#define DDRSS0_PHY_1003_DATA 0x00000000
+#define DDRSS0_PHY_1004_DATA 0x00000000
+#define DDRSS0_PHY_1005_DATA 0x00000000
+#define DDRSS0_PHY_1006_DATA 0x00000000
+#define DDRSS0_PHY_1007_DATA 0x00000000
+#define DDRSS0_PHY_1008_DATA 0x00000000
+#define DDRSS0_PHY_1009_DATA 0x00000000
+#define DDRSS0_PHY_1010_DATA 0x00000000
+#define DDRSS0_PHY_1011_DATA 0x00000000
+#define DDRSS0_PHY_1012_DATA 0x00000000
+#define DDRSS0_PHY_1013_DATA 0x00000000
+#define DDRSS0_PHY_1014_DATA 0x00000000
+#define DDRSS0_PHY_1015_DATA 0x00000000
+#define DDRSS0_PHY_1016_DATA 0x00000000
+#define DDRSS0_PHY_1017_DATA 0x00000000
+#define DDRSS0_PHY_1018_DATA 0x00000000
+#define DDRSS0_PHY_1019_DATA 0x00000000
+#define DDRSS0_PHY_1020_DATA 0x00000000
+#define DDRSS0_PHY_1021_DATA 0x00000000
+#define DDRSS0_PHY_1022_DATA 0x00000000
+#define DDRSS0_PHY_1023_DATA 0x00000000
+#define DDRSS0_PHY_1024_DATA 0x00000000
+#define DDRSS0_PHY_1025_DATA 0x00000000
+#define DDRSS0_PHY_1026_DATA 0x00000000
+#define DDRSS0_PHY_1027_DATA 0x00000000
+#define DDRSS0_PHY_1028_DATA 0x00000000
+#define DDRSS0_PHY_1029_DATA 0x00000100
+#define DDRSS0_PHY_1030_DATA 0x00000200
+#define DDRSS0_PHY_1031_DATA 0x00000000
+#define DDRSS0_PHY_1032_DATA 0x00000000
+#define DDRSS0_PHY_1033_DATA 0x00000000
+#define DDRSS0_PHY_1034_DATA 0x00000000
+#define DDRSS0_PHY_1035_DATA 0x00400000
+#define DDRSS0_PHY_1036_DATA 0x00000080
+#define DDRSS0_PHY_1037_DATA 0x00DCBA98
+#define DDRSS0_PHY_1038_DATA 0x03000000
+#define DDRSS0_PHY_1039_DATA 0x00200000
+#define DDRSS0_PHY_1040_DATA 0x00000000
+#define DDRSS0_PHY_1041_DATA 0x00000000
+#define DDRSS0_PHY_1042_DATA 0x00000000
+#define DDRSS0_PHY_1043_DATA 0x00000000
+#define DDRSS0_PHY_1044_DATA 0x00000000
+#define DDRSS0_PHY_1045_DATA 0x0000002A
+#define DDRSS0_PHY_1046_DATA 0x00000015
+#define DDRSS0_PHY_1047_DATA 0x00000015
+#define DDRSS0_PHY_1048_DATA 0x0000002A
+#define DDRSS0_PHY_1049_DATA 0x00000033
+#define DDRSS0_PHY_1050_DATA 0x0000000C
+#define DDRSS0_PHY_1051_DATA 0x0000000C
+#define DDRSS0_PHY_1052_DATA 0x00000033
+#define DDRSS0_PHY_1053_DATA 0x00543210
+#define DDRSS0_PHY_1054_DATA 0x003F0000
+#define DDRSS0_PHY_1055_DATA 0x000F3F3F
+#define DDRSS0_PHY_1056_DATA 0x20202003
+#define DDRSS0_PHY_1057_DATA 0x00202020
+#define DDRSS0_PHY_1058_DATA 0x20008008
+#define DDRSS0_PHY_1059_DATA 0x00000810
+#define DDRSS0_PHY_1060_DATA 0x00000F00
+#define DDRSS0_PHY_1061_DATA 0x00000000
+#define DDRSS0_PHY_1062_DATA 0x00000000
+#define DDRSS0_PHY_1063_DATA 0x00000000
+#define DDRSS0_PHY_1064_DATA 0x000305CC
+#define DDRSS0_PHY_1065_DATA 0x00030000
+#define DDRSS0_PHY_1066_DATA 0x00000300
+#define DDRSS0_PHY_1067_DATA 0x00000300
+#define DDRSS0_PHY_1068_DATA 0x00000300
+#define DDRSS0_PHY_1069_DATA 0x00000300
+#define DDRSS0_PHY_1070_DATA 0x00000300
+#define DDRSS0_PHY_1071_DATA 0x42080010
+#define DDRSS0_PHY_1072_DATA 0x0000803E
+#define DDRSS0_PHY_1073_DATA 0x00000001
+#define DDRSS0_PHY_1074_DATA 0x01000102
+#define DDRSS0_PHY_1075_DATA 0x00008000
+#define DDRSS0_PHY_1076_DATA 0x00000000
+#define DDRSS0_PHY_1077_DATA 0x00000000
+#define DDRSS0_PHY_1078_DATA 0x00000000
+#define DDRSS0_PHY_1079_DATA 0x00000000
+#define DDRSS0_PHY_1080_DATA 0x00000000
+#define DDRSS0_PHY_1081_DATA 0x00000000
+#define DDRSS0_PHY_1082_DATA 0x00000000
+#define DDRSS0_PHY_1083_DATA 0x00000000
+#define DDRSS0_PHY_1084_DATA 0x00000000
+#define DDRSS0_PHY_1085_DATA 0x00000000
+#define DDRSS0_PHY_1086_DATA 0x00000000
+#define DDRSS0_PHY_1087_DATA 0x00000000
+#define DDRSS0_PHY_1088_DATA 0x00000000
+#define DDRSS0_PHY_1089_DATA 0x00000000
+#define DDRSS0_PHY_1090_DATA 0x00000000
+#define DDRSS0_PHY_1091_DATA 0x00000000
+#define DDRSS0_PHY_1092_DATA 0x00000000
+#define DDRSS0_PHY_1093_DATA 0x00000000
+#define DDRSS0_PHY_1094_DATA 0x00000000
+#define DDRSS0_PHY_1095_DATA 0x00000000
+#define DDRSS0_PHY_1096_DATA 0x00000000
+#define DDRSS0_PHY_1097_DATA 0x00000000
+#define DDRSS0_PHY_1098_DATA 0x00000000
+#define DDRSS0_PHY_1099_DATA 0x00000000
+#define DDRSS0_PHY_1100_DATA 0x00000000
+#define DDRSS0_PHY_1101_DATA 0x00000000
+#define DDRSS0_PHY_1102_DATA 0x00000000
+#define DDRSS0_PHY_1103_DATA 0x00000000
+#define DDRSS0_PHY_1104_DATA 0x00000000
+#define DDRSS0_PHY_1105_DATA 0x00000000
+#define DDRSS0_PHY_1106_DATA 0x00000000
+#define DDRSS0_PHY_1107_DATA 0x00000000
+#define DDRSS0_PHY_1108_DATA 0x00000000
+#define DDRSS0_PHY_1109_DATA 0x00000000
+#define DDRSS0_PHY_1110_DATA 0x00000000
+#define DDRSS0_PHY_1111_DATA 0x00000000
+#define DDRSS0_PHY_1112_DATA 0x00000000
+#define DDRSS0_PHY_1113_DATA 0x00000000
+#define DDRSS0_PHY_1114_DATA 0x00000000
+#define DDRSS0_PHY_1115_DATA 0x00000000
+#define DDRSS0_PHY_1116_DATA 0x00000000
+#define DDRSS0_PHY_1117_DATA 0x00000000
+#define DDRSS0_PHY_1118_DATA 0x00000000
+#define DDRSS0_PHY_1119_DATA 0x00000000
+#define DDRSS0_PHY_1120_DATA 0x00000000
+#define DDRSS0_PHY_1121_DATA 0x00000000
+#define DDRSS0_PHY_1122_DATA 0x00000000
+#define DDRSS0_PHY_1123_DATA 0x00000000
+#define DDRSS0_PHY_1124_DATA 0x00000000
+#define DDRSS0_PHY_1125_DATA 0x00000000
+#define DDRSS0_PHY_1126_DATA 0x00000000
+#define DDRSS0_PHY_1127_DATA 0x00000000
+#define DDRSS0_PHY_1128_DATA 0x00000000
+#define DDRSS0_PHY_1129_DATA 0x00000000
+#define DDRSS0_PHY_1130_DATA 0x00000000
+#define DDRSS0_PHY_1131_DATA 0x00000000
+#define DDRSS0_PHY_1132_DATA 0x00000000
+#define DDRSS0_PHY_1133_DATA 0x00000000
+#define DDRSS0_PHY_1134_DATA 0x00000000
+#define DDRSS0_PHY_1135_DATA 0x00000000
+#define DDRSS0_PHY_1136_DATA 0x00000000
+#define DDRSS0_PHY_1137_DATA 0x00000000
+#define DDRSS0_PHY_1138_DATA 0x00000000
+#define DDRSS0_PHY_1139_DATA 0x00000000
+#define DDRSS0_PHY_1140_DATA 0x00000000
+#define DDRSS0_PHY_1141_DATA 0x00000000
+#define DDRSS0_PHY_1142_DATA 0x00000000
+#define DDRSS0_PHY_1143_DATA 0x00000000
+#define DDRSS0_PHY_1144_DATA 0x00000000
+#define DDRSS0_PHY_1145_DATA 0x00000000
+#define DDRSS0_PHY_1146_DATA 0x00000000
+#define DDRSS0_PHY_1147_DATA 0x00000000
+#define DDRSS0_PHY_1148_DATA 0x00000000
+#define DDRSS0_PHY_1149_DATA 0x00000000
+#define DDRSS0_PHY_1150_DATA 0x00000000
+#define DDRSS0_PHY_1151_DATA 0x00000000
+#define DDRSS0_PHY_1152_DATA 0x00000000
+#define DDRSS0_PHY_1153_DATA 0x00000000
+#define DDRSS0_PHY_1154_DATA 0x00000000
+#define DDRSS0_PHY_1155_DATA 0x00000000
+#define DDRSS0_PHY_1156_DATA 0x00000000
+#define DDRSS0_PHY_1157_DATA 0x00000000
+#define DDRSS0_PHY_1158_DATA 0x00000000
+#define DDRSS0_PHY_1159_DATA 0x00000000
+#define DDRSS0_PHY_1160_DATA 0x00000000
+#define DDRSS0_PHY_1161_DATA 0x00000000
+#define DDRSS0_PHY_1162_DATA 0x00000000
+#define DDRSS0_PHY_1163_DATA 0x00000000
+#define DDRSS0_PHY_1164_DATA 0x00000000
+#define DDRSS0_PHY_1165_DATA 0x00000000
+#define DDRSS0_PHY_1166_DATA 0x00000000
+#define DDRSS0_PHY_1167_DATA 0x00000000
+#define DDRSS0_PHY_1168_DATA 0x00000000
+#define DDRSS0_PHY_1169_DATA 0x00000000
+#define DDRSS0_PHY_1170_DATA 0x00000000
+#define DDRSS0_PHY_1171_DATA 0x00000000
+#define DDRSS0_PHY_1172_DATA 0x00000000
+#define DDRSS0_PHY_1173_DATA 0x00000000
+#define DDRSS0_PHY_1174_DATA 0x00000000
+#define DDRSS0_PHY_1175_DATA 0x00000000
+#define DDRSS0_PHY_1176_DATA 0x00000000
+#define DDRSS0_PHY_1177_DATA 0x00000000
+#define DDRSS0_PHY_1178_DATA 0x00000000
+#define DDRSS0_PHY_1179_DATA 0x00000000
+#define DDRSS0_PHY_1180_DATA 0x00000000
+#define DDRSS0_PHY_1181_DATA 0x00000000
+#define DDRSS0_PHY_1182_DATA 0x00000000
+#define DDRSS0_PHY_1183_DATA 0x00000000
+#define DDRSS0_PHY_1184_DATA 0x00000000
+#define DDRSS0_PHY_1185_DATA 0x00000000
+#define DDRSS0_PHY_1186_DATA 0x00000000
+#define DDRSS0_PHY_1187_DATA 0x00000000
+#define DDRSS0_PHY_1188_DATA 0x00000000
+#define DDRSS0_PHY_1189_DATA 0x00000000
+#define DDRSS0_PHY_1190_DATA 0x00000000
+#define DDRSS0_PHY_1191_DATA 0x00000000
+#define DDRSS0_PHY_1192_DATA 0x00000000
+#define DDRSS0_PHY_1193_DATA 0x00000000
+#define DDRSS0_PHY_1194_DATA 0x00000000
+#define DDRSS0_PHY_1195_DATA 0x00000000
+#define DDRSS0_PHY_1196_DATA 0x00000000
+#define DDRSS0_PHY_1197_DATA 0x00000000
+#define DDRSS0_PHY_1198_DATA 0x00000000
+#define DDRSS0_PHY_1199_DATA 0x00000000
+#define DDRSS0_PHY_1200_DATA 0x00000000
+#define DDRSS0_PHY_1201_DATA 0x00000000
+#define DDRSS0_PHY_1202_DATA 0x00000000
+#define DDRSS0_PHY_1203_DATA 0x00000000
+#define DDRSS0_PHY_1204_DATA 0x00000000
+#define DDRSS0_PHY_1205_DATA 0x00000000
+#define DDRSS0_PHY_1206_DATA 0x00000000
+#define DDRSS0_PHY_1207_DATA 0x00000000
+#define DDRSS0_PHY_1208_DATA 0x00000000
+#define DDRSS0_PHY_1209_DATA 0x00000000
+#define DDRSS0_PHY_1210_DATA 0x00000000
+#define DDRSS0_PHY_1211_DATA 0x00000000
+#define DDRSS0_PHY_1212_DATA 0x00000000
+#define DDRSS0_PHY_1213_DATA 0x00000000
+#define DDRSS0_PHY_1214_DATA 0x00000000
+#define DDRSS0_PHY_1215_DATA 0x00000000
+#define DDRSS0_PHY_1216_DATA 0x00000000
+#define DDRSS0_PHY_1217_DATA 0x00000000
+#define DDRSS0_PHY_1218_DATA 0x00000000
+#define DDRSS0_PHY_1219_DATA 0x00000000
+#define DDRSS0_PHY_1220_DATA 0x00000000
+#define DDRSS0_PHY_1221_DATA 0x00000000
+#define DDRSS0_PHY_1222_DATA 0x00000000
+#define DDRSS0_PHY_1223_DATA 0x00000000
+#define DDRSS0_PHY_1224_DATA 0x00000000
+#define DDRSS0_PHY_1225_DATA 0x00000000
+#define DDRSS0_PHY_1226_DATA 0x00000000
+#define DDRSS0_PHY_1227_DATA 0x00000000
+#define DDRSS0_PHY_1228_DATA 0x00000000
+#define DDRSS0_PHY_1229_DATA 0x00000000
+#define DDRSS0_PHY_1230_DATA 0x00000000
+#define DDRSS0_PHY_1231_DATA 0x00000000
+#define DDRSS0_PHY_1232_DATA 0x00000000
+#define DDRSS0_PHY_1233_DATA 0x00000000
+#define DDRSS0_PHY_1234_DATA 0x00000000
+#define DDRSS0_PHY_1235_DATA 0x00000000
+#define DDRSS0_PHY_1236_DATA 0x00000000
+#define DDRSS0_PHY_1237_DATA 0x00000000
+#define DDRSS0_PHY_1238_DATA 0x00000000
+#define DDRSS0_PHY_1239_DATA 0x00000000
+#define DDRSS0_PHY_1240_DATA 0x00000000
+#define DDRSS0_PHY_1241_DATA 0x00000000
+#define DDRSS0_PHY_1242_DATA 0x00000000
+#define DDRSS0_PHY_1243_DATA 0x00000000
+#define DDRSS0_PHY_1244_DATA 0x00000000
+#define DDRSS0_PHY_1245_DATA 0x00000000
+#define DDRSS0_PHY_1246_DATA 0x00000000
+#define DDRSS0_PHY_1247_DATA 0x00000000
+#define DDRSS0_PHY_1248_DATA 0x00000000
+#define DDRSS0_PHY_1249_DATA 0x00000000
+#define DDRSS0_PHY_1250_DATA 0x00000000
+#define DDRSS0_PHY_1251_DATA 0x00000000
+#define DDRSS0_PHY_1252_DATA 0x00000000
+#define DDRSS0_PHY_1253_DATA 0x00000000
+#define DDRSS0_PHY_1254_DATA 0x00000000
+#define DDRSS0_PHY_1255_DATA 0x00000000
+#define DDRSS0_PHY_1256_DATA 0x00000000
+#define DDRSS0_PHY_1257_DATA 0x00000000
+#define DDRSS0_PHY_1258_DATA 0x00000000
+#define DDRSS0_PHY_1259_DATA 0x00000000
+#define DDRSS0_PHY_1260_DATA 0x00000000
+#define DDRSS0_PHY_1261_DATA 0x00000000
+#define DDRSS0_PHY_1262_DATA 0x00000000
+#define DDRSS0_PHY_1263_DATA 0x00000000
+#define DDRSS0_PHY_1264_DATA 0x00000000
+#define DDRSS0_PHY_1265_DATA 0x00000000
+#define DDRSS0_PHY_1266_DATA 0x00000000
+#define DDRSS0_PHY_1267_DATA 0x00000000
+#define DDRSS0_PHY_1268_DATA 0x00000000
+#define DDRSS0_PHY_1269_DATA 0x00000000
+#define DDRSS0_PHY_1270_DATA 0x00000000
+#define DDRSS0_PHY_1271_DATA 0x00000000
+#define DDRSS0_PHY_1272_DATA 0x00000000
+#define DDRSS0_PHY_1273_DATA 0x00000000
+#define DDRSS0_PHY_1274_DATA 0x00000000
+#define DDRSS0_PHY_1275_DATA 0x00000000
+#define DDRSS0_PHY_1276_DATA 0x00000000
+#define DDRSS0_PHY_1277_DATA 0x00000000
+#define DDRSS0_PHY_1278_DATA 0x00000000
+#define DDRSS0_PHY_1279_DATA 0x00000000
+#define DDRSS0_PHY_1280_DATA 0x00000000
+#define DDRSS0_PHY_1281_DATA 0x00010100
+#define DDRSS0_PHY_1282_DATA 0x00000000
+#define DDRSS0_PHY_1283_DATA 0x00000000
+#define DDRSS0_PHY_1284_DATA 0x00050000
+#define DDRSS0_PHY_1285_DATA 0x04000000
+#define DDRSS0_PHY_1286_DATA 0x00000055
+#define DDRSS0_PHY_1287_DATA 0x00000000
+#define DDRSS0_PHY_1288_DATA 0x00000000
+#define DDRSS0_PHY_1289_DATA 0x00000000
+#define DDRSS0_PHY_1290_DATA 0x00000000
+#define DDRSS0_PHY_1291_DATA 0x00002001
+#define DDRSS0_PHY_1292_DATA 0x0000400F
+#define DDRSS0_PHY_1293_DATA 0x50020028
+#define DDRSS0_PHY_1294_DATA 0x01010000
+#define DDRSS0_PHY_1295_DATA 0x80080001
+#define DDRSS0_PHY_1296_DATA 0x10200000
+#define DDRSS0_PHY_1297_DATA 0x00000008
+#define DDRSS0_PHY_1298_DATA 0x00000000
+#define DDRSS0_PHY_1299_DATA 0x01090E00
+#define DDRSS0_PHY_1300_DATA 0x00040101
+#define DDRSS0_PHY_1301_DATA 0x0000010F
+#define DDRSS0_PHY_1302_DATA 0x00000000
+#define DDRSS0_PHY_1303_DATA 0x00000064
+#define DDRSS0_PHY_1304_DATA 0x00000000
+#define DDRSS0_PHY_1305_DATA 0x01010000
+#define DDRSS0_PHY_1306_DATA 0x01080402
+#define DDRSS0_PHY_1307_DATA 0x01200F02
+#define DDRSS0_PHY_1308_DATA 0x00194280
+#define DDRSS0_PHY_1309_DATA 0x00000004
+#define DDRSS0_PHY_1310_DATA 0x00042000
+#define DDRSS0_PHY_1311_DATA 0x00000000
+#define DDRSS0_PHY_1312_DATA 0x00000000
+#define DDRSS0_PHY_1313_DATA 0x00000000
+#define DDRSS0_PHY_1314_DATA 0x00000000
+#define DDRSS0_PHY_1315_DATA 0x00000000
+#define DDRSS0_PHY_1316_DATA 0x00000000
+#define DDRSS0_PHY_1317_DATA 0x01000000
+#define DDRSS0_PHY_1318_DATA 0x00000705
+#define DDRSS0_PHY_1319_DATA 0x00000054
+#define DDRSS0_PHY_1320_DATA 0x00030820
+#define DDRSS0_PHY_1321_DATA 0x00010820
+#define DDRSS0_PHY_1322_DATA 0x00010820
+#define DDRSS0_PHY_1323_DATA 0x00010820
+#define DDRSS0_PHY_1324_DATA 0x00010820
+#define DDRSS0_PHY_1325_DATA 0x00010820
+#define DDRSS0_PHY_1326_DATA 0x00010820
+#define DDRSS0_PHY_1327_DATA 0x00010820
+#define DDRSS0_PHY_1328_DATA 0x00010820
+#define DDRSS0_PHY_1329_DATA 0x00000000
+#define DDRSS0_PHY_1330_DATA 0x00000074
+#define DDRSS0_PHY_1331_DATA 0x00000400
+#define DDRSS0_PHY_1332_DATA 0x00000108
+#define DDRSS0_PHY_1333_DATA 0x00000000
+#define DDRSS0_PHY_1334_DATA 0x00000000
+#define DDRSS0_PHY_1335_DATA 0x00000000
+#define DDRSS0_PHY_1336_DATA 0x00000000
+#define DDRSS0_PHY_1337_DATA 0x00000000
+#define DDRSS0_PHY_1338_DATA 0x03000000
+#define DDRSS0_PHY_1339_DATA 0x00000000
+#define DDRSS0_PHY_1340_DATA 0x00000000
+#define DDRSS0_PHY_1341_DATA 0x00000000
+#define DDRSS0_PHY_1342_DATA 0x04102006
+#define DDRSS0_PHY_1343_DATA 0x00041020
+#define DDRSS0_PHY_1344_DATA 0x01C98C98
+#define DDRSS0_PHY_1345_DATA 0x3F400000
+#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS0_PHY_1347_DATA 0x0000001F
+#define DDRSS0_PHY_1348_DATA 0x00000000
+#define DDRSS0_PHY_1349_DATA 0x00000000
+#define DDRSS0_PHY_1350_DATA 0x00000000
+#define DDRSS0_PHY_1351_DATA 0x00010000
+#define DDRSS0_PHY_1352_DATA 0x00000000
+#define DDRSS0_PHY_1353_DATA 0x00000000
+#define DDRSS0_PHY_1354_DATA 0x00000000
+#define DDRSS0_PHY_1355_DATA 0x00000000
+#define DDRSS0_PHY_1356_DATA 0x76543210
+#define DDRSS0_PHY_1357_DATA 0x00010198
+#define DDRSS0_PHY_1358_DATA 0x00000000
+#define DDRSS0_PHY_1359_DATA 0x00000000
+#define DDRSS0_PHY_1360_DATA 0x00000000
+#define DDRSS0_PHY_1361_DATA 0x00040700
+#define DDRSS0_PHY_1362_DATA 0x00000000
+#define DDRSS0_PHY_1363_DATA 0x00000000
+#define DDRSS0_PHY_1364_DATA 0x00000000
+#define DDRSS0_PHY_1365_DATA 0x00000000
+#define DDRSS0_PHY_1366_DATA 0x00000000
+#define DDRSS0_PHY_1367_DATA 0x00000002
+#define DDRSS0_PHY_1368_DATA 0x00000000
+#define DDRSS0_PHY_1369_DATA 0x00000000
+#define DDRSS0_PHY_1370_DATA 0x00000000
+#define DDRSS0_PHY_1371_DATA 0x00000000
+#define DDRSS0_PHY_1372_DATA 0x00000000
+#define DDRSS0_PHY_1373_DATA 0x00000000
+#define DDRSS0_PHY_1374_DATA 0x00080000
+#define DDRSS0_PHY_1375_DATA 0x000007FF
+#define DDRSS0_PHY_1376_DATA 0x00000000
+#define DDRSS0_PHY_1377_DATA 0x00000000
+#define DDRSS0_PHY_1378_DATA 0x00000000
+#define DDRSS0_PHY_1379_DATA 0x00000000
+#define DDRSS0_PHY_1380_DATA 0x00000000
+#define DDRSS0_PHY_1381_DATA 0x00000000
+#define DDRSS0_PHY_1382_DATA 0x000FFFFF
+#define DDRSS0_PHY_1383_DATA 0x000FFFFF
+#define DDRSS0_PHY_1384_DATA 0x0000FFFF
+#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS0_PHY_1386_DATA 0x030FFFFF
+#define DDRSS0_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS0_PHY_1388_DATA 0x0000FFFF
+#define DDRSS0_PHY_1389_DATA 0x00000000
+#define DDRSS0_PHY_1390_DATA 0x00000000
+#define DDRSS0_PHY_1391_DATA 0x00000000
+#define DDRSS0_PHY_1392_DATA 0x00000000
+#define DDRSS0_PHY_1393_DATA 0x0001F7C0
+#define DDRSS0_PHY_1394_DATA 0x00000003
+#define DDRSS0_PHY_1395_DATA 0x00000000
+#define DDRSS0_PHY_1396_DATA 0x00001142
+#define DDRSS0_PHY_1397_DATA 0x040207AB
+#define DDRSS0_PHY_1398_DATA 0x01000080
+#define DDRSS0_PHY_1399_DATA 0x03900390
+#define DDRSS0_PHY_1400_DATA 0x03900390
+#define DDRSS0_PHY_1401_DATA 0x00000390
+#define DDRSS0_PHY_1402_DATA 0x00000390
+#define DDRSS0_PHY_1403_DATA 0x00000390
+#define DDRSS0_PHY_1404_DATA 0x00000390
+#define DDRSS0_PHY_1405_DATA 0x00000005
+#define DDRSS0_PHY_1406_DATA 0x01813FCC
+#define DDRSS0_PHY_1407_DATA 0x000000CC
+#define DDRSS0_PHY_1408_DATA 0x0C000DFF
+#define DDRSS0_PHY_1409_DATA 0x30000DFF
+#define DDRSS0_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1411_DATA 0x000100F0
+#define DDRSS0_PHY_1412_DATA 0x780DFFCC
+#define DDRSS0_PHY_1413_DATA 0x00007E31
+#define DDRSS0_PHY_1414_DATA 0x000CBF11
+#define DDRSS0_PHY_1415_DATA 0x01990010
+#define DDRSS0_PHY_1416_DATA 0x000CBF11
+#define DDRSS0_PHY_1417_DATA 0x01990010
+#define DDRSS0_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1419_DATA 0x00EF00F0
+#define DDRSS0_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1421_DATA 0x01FF00F0
+#define DDRSS0_PHY_1422_DATA 0x20040006
+
+#define DDRSS1_CTL_00_DATA 0x00000B00
+#define DDRSS1_CTL_01_DATA 0x00000000
+#define DDRSS1_CTL_02_DATA 0x00000000
+#define DDRSS1_CTL_03_DATA 0x00000000
+#define DDRSS1_CTL_04_DATA 0x00000000
+#define DDRSS1_CTL_05_DATA 0x00000000
+#define DDRSS1_CTL_06_DATA 0x00000000
+#define DDRSS1_CTL_07_DATA 0x00002AF8
+#define DDRSS1_CTL_08_DATA 0x0001ADAF
+#define DDRSS1_CTL_09_DATA 0x00000005
+#define DDRSS1_CTL_10_DATA 0x0000006E
+#define DDRSS1_CTL_11_DATA 0x000681C8
+#define DDRSS1_CTL_12_DATA 0x004111C9
+#define DDRSS1_CTL_13_DATA 0x00000005
+#define DDRSS1_CTL_14_DATA 0x000010A9
+#define DDRSS1_CTL_15_DATA 0x000681C8
+#define DDRSS1_CTL_16_DATA 0x004111C9
+#define DDRSS1_CTL_17_DATA 0x00000005
+#define DDRSS1_CTL_18_DATA 0x000010A9
+#define DDRSS1_CTL_19_DATA 0x01010000
+#define DDRSS1_CTL_20_DATA 0x01011001
+#define DDRSS1_CTL_21_DATA 0x02010000
+#define DDRSS1_CTL_22_DATA 0x00020100
+#define DDRSS1_CTL_23_DATA 0x0000000B
+#define DDRSS1_CTL_24_DATA 0x0000001C
+#define DDRSS1_CTL_25_DATA 0x00000000
+#define DDRSS1_CTL_26_DATA 0x00000000
+#define DDRSS1_CTL_27_DATA 0x03020200
+#define DDRSS1_CTL_28_DATA 0x00005656
+#define DDRSS1_CTL_29_DATA 0x00100000
+#define DDRSS1_CTL_30_DATA 0x00000000
+#define DDRSS1_CTL_31_DATA 0x00000000
+#define DDRSS1_CTL_32_DATA 0x00000000
+#define DDRSS1_CTL_33_DATA 0x00000000
+#define DDRSS1_CTL_34_DATA 0x040C0000
+#define DDRSS1_CTL_35_DATA 0x12501250
+#define DDRSS1_CTL_36_DATA 0x00050804
+#define DDRSS1_CTL_37_DATA 0x09040008
+#define DDRSS1_CTL_38_DATA 0x15000204
+#define DDRSS1_CTL_39_DATA 0x1760008B
+#define DDRSS1_CTL_40_DATA 0x1500422B
+#define DDRSS1_CTL_41_DATA 0x1760008B
+#define DDRSS1_CTL_42_DATA 0x2000422B
+#define DDRSS1_CTL_43_DATA 0x000A0A09
+#define DDRSS1_CTL_44_DATA 0x040003C5
+#define DDRSS1_CTL_45_DATA 0x1E161104
+#define DDRSS1_CTL_46_DATA 0x1000922C
+#define DDRSS1_CTL_47_DATA 0x1E161110
+#define DDRSS1_CTL_48_DATA 0x1000922C
+#define DDRSS1_CTL_49_DATA 0x02030410
+#define DDRSS1_CTL_50_DATA 0x2C060500
+#define DDRSS1_CTL_51_DATA 0x08292C29
+#define DDRSS1_CTL_52_DATA 0x14000E0A
+#define DDRSS1_CTL_53_DATA 0x04010A0A
+#define DDRSS1_CTL_54_DATA 0x01010004
+#define DDRSS1_CTL_55_DATA 0x0454540A
+#define DDRSS1_CTL_56_DATA 0x04313104
+#define DDRSS1_CTL_57_DATA 0x00003131
+#define DDRSS1_CTL_58_DATA 0x00010100
+#define DDRSS1_CTL_59_DATA 0x03010000
+#define DDRSS1_CTL_60_DATA 0x00001508
+#define DDRSS1_CTL_61_DATA 0x00000068
+#define DDRSS1_CTL_62_DATA 0x0000032B
+#define DDRSS1_CTL_63_DATA 0x00001035
+#define DDRSS1_CTL_64_DATA 0x0000032B
+#define DDRSS1_CTL_65_DATA 0x00001035
+#define DDRSS1_CTL_66_DATA 0x00000005
+#define DDRSS1_CTL_67_DATA 0x00050000
+#define DDRSS1_CTL_68_DATA 0x00CB0005
+#define DDRSS1_CTL_69_DATA 0x00CB0200
+#define DDRSS1_CTL_70_DATA 0x00400200
+#define DDRSS1_CTL_71_DATA 0x00120103
+#define DDRSS1_CTL_72_DATA 0x00100005
+#define DDRSS1_CTL_73_DATA 0x2F080010
+#define DDRSS1_CTL_74_DATA 0x0505012F
+#define DDRSS1_CTL_75_DATA 0x0401030A
+#define DDRSS1_CTL_76_DATA 0x041E100B
+#define DDRSS1_CTL_77_DATA 0x100B0401
+#define DDRSS1_CTL_78_DATA 0x0001041E
+#define DDRSS1_CTL_79_DATA 0x00160016
+#define DDRSS1_CTL_80_DATA 0x033B033B
+#define DDRSS1_CTL_81_DATA 0x033B033B
+#define DDRSS1_CTL_82_DATA 0x03050505
+#define DDRSS1_CTL_83_DATA 0x03010303
+#define DDRSS1_CTL_84_DATA 0x200B100B
+#define DDRSS1_CTL_85_DATA 0x04041004
+#define DDRSS1_CTL_86_DATA 0x200B100B
+#define DDRSS1_CTL_87_DATA 0x04041004
+#define DDRSS1_CTL_88_DATA 0x03010000
+#define DDRSS1_CTL_89_DATA 0x00010000
+#define DDRSS1_CTL_90_DATA 0x00000000
+#define DDRSS1_CTL_91_DATA 0x00000000
+#define DDRSS1_CTL_92_DATA 0x01000000
+#define DDRSS1_CTL_93_DATA 0x80104002
+#define DDRSS1_CTL_94_DATA 0x00000000
+#define DDRSS1_CTL_95_DATA 0x00040005
+#define DDRSS1_CTL_96_DATA 0x00000000
+#define DDRSS1_CTL_97_DATA 0x00050000
+#define DDRSS1_CTL_98_DATA 0x00000004
+#define DDRSS1_CTL_99_DATA 0x00000000
+#define DDRSS1_CTL_100_DATA 0x00040005
+#define DDRSS1_CTL_101_DATA 0x00000000
+#define DDRSS1_CTL_102_DATA 0x000018C0
+#define DDRSS1_CTL_103_DATA 0x000018C0
+#define DDRSS1_CTL_104_DATA 0x000018C0
+#define DDRSS1_CTL_105_DATA 0x000018C0
+#define DDRSS1_CTL_106_DATA 0x000018C0
+#define DDRSS1_CTL_107_DATA 0x00000000
+#define DDRSS1_CTL_108_DATA 0x000002B5
+#define DDRSS1_CTL_109_DATA 0x00040D40
+#define DDRSS1_CTL_110_DATA 0x00040D40
+#define DDRSS1_CTL_111_DATA 0x00040D40
+#define DDRSS1_CTL_112_DATA 0x00040D40
+#define DDRSS1_CTL_113_DATA 0x00040D40
+#define DDRSS1_CTL_114_DATA 0x00000000
+#define DDRSS1_CTL_115_DATA 0x00007173
+#define DDRSS1_CTL_116_DATA 0x00040D40
+#define DDRSS1_CTL_117_DATA 0x00040D40
+#define DDRSS1_CTL_118_DATA 0x00040D40
+#define DDRSS1_CTL_119_DATA 0x00040D40
+#define DDRSS1_CTL_120_DATA 0x00040D40
+#define DDRSS1_CTL_121_DATA 0x00000000
+#define DDRSS1_CTL_122_DATA 0x00007173
+#define DDRSS1_CTL_123_DATA 0x00000000
+#define DDRSS1_CTL_124_DATA 0x00000000
+#define DDRSS1_CTL_125_DATA 0x00000000
+#define DDRSS1_CTL_126_DATA 0x00000000
+#define DDRSS1_CTL_127_DATA 0x00000000
+#define DDRSS1_CTL_128_DATA 0x00000000
+#define DDRSS1_CTL_129_DATA 0x00000000
+#define DDRSS1_CTL_130_DATA 0x00000000
+#define DDRSS1_CTL_131_DATA 0x0B030500
+#define DDRSS1_CTL_132_DATA 0x00040B04
+#define DDRSS1_CTL_133_DATA 0x0A090000
+#define DDRSS1_CTL_134_DATA 0x0A090701
+#define DDRSS1_CTL_135_DATA 0x0900000E
+#define DDRSS1_CTL_136_DATA 0x0907010A
+#define DDRSS1_CTL_137_DATA 0x00000E0A
+#define DDRSS1_CTL_138_DATA 0x07010A09
+#define DDRSS1_CTL_139_DATA 0x000E0A09
+#define DDRSS1_CTL_140_DATA 0x07000401
+#define DDRSS1_CTL_141_DATA 0x00000000
+#define DDRSS1_CTL_142_DATA 0x00000000
+#define DDRSS1_CTL_143_DATA 0x00000000
+#define DDRSS1_CTL_144_DATA 0x00000000
+#define DDRSS1_CTL_145_DATA 0x00000000
+#define DDRSS1_CTL_146_DATA 0x00000000
+#define DDRSS1_CTL_147_DATA 0x00000000
+#define DDRSS1_CTL_148_DATA 0x08080000
+#define DDRSS1_CTL_149_DATA 0x01000000
+#define DDRSS1_CTL_150_DATA 0x800000C0
+#define DDRSS1_CTL_151_DATA 0x800000C0
+#define DDRSS1_CTL_152_DATA 0x800000C0
+#define DDRSS1_CTL_153_DATA 0x00000000
+#define DDRSS1_CTL_154_DATA 0x00001500
+#define DDRSS1_CTL_155_DATA 0x00000000
+#define DDRSS1_CTL_156_DATA 0x00000001
+#define DDRSS1_CTL_157_DATA 0x00000002
+#define DDRSS1_CTL_158_DATA 0x0000100E
+#define DDRSS1_CTL_159_DATA 0x00000000
+#define DDRSS1_CTL_160_DATA 0x00000000
+#define DDRSS1_CTL_161_DATA 0x00000000
+#define DDRSS1_CTL_162_DATA 0x00000000
+#define DDRSS1_CTL_163_DATA 0x00000000
+#define DDRSS1_CTL_164_DATA 0x000B0000
+#define DDRSS1_CTL_165_DATA 0x000E0006
+#define DDRSS1_CTL_166_DATA 0x000E0404
+#define DDRSS1_CTL_167_DATA 0x00D601AB
+#define DDRSS1_CTL_168_DATA 0x10100216
+#define DDRSS1_CTL_169_DATA 0x01AB0216
+#define DDRSS1_CTL_170_DATA 0x021600D6
+#define DDRSS1_CTL_171_DATA 0x02161010
+#define DDRSS1_CTL_172_DATA 0x00000000
+#define DDRSS1_CTL_173_DATA 0x00000000
+#define DDRSS1_CTL_174_DATA 0x00000000
+#define DDRSS1_CTL_175_DATA 0x3FF40084
+#define DDRSS1_CTL_176_DATA 0xF3003FF4
+#define DDRSS1_CTL_177_DATA 0x0000F3F3
+#define DDRSS1_CTL_178_DATA 0x35000000
+#define DDRSS1_CTL_179_DATA 0x27270035
+#define DDRSS1_CTL_180_DATA 0x0F0F0000
+#define DDRSS1_CTL_181_DATA 0x16000000
+#define DDRSS1_CTL_182_DATA 0x00841616
+#define DDRSS1_CTL_183_DATA 0x3FF43FF4
+#define DDRSS1_CTL_184_DATA 0xF3F3F300
+#define DDRSS1_CTL_185_DATA 0x00000000
+#define DDRSS1_CTL_186_DATA 0x00353500
+#define DDRSS1_CTL_187_DATA 0x00002727
+#define DDRSS1_CTL_188_DATA 0x00000F0F
+#define DDRSS1_CTL_189_DATA 0x16161600
+#define DDRSS1_CTL_190_DATA 0x00000020
+#define DDRSS1_CTL_191_DATA 0x01000000
+#define DDRSS1_CTL_192_DATA 0x00000001
+#define DDRSS1_CTL_193_DATA 0x00000000
+#define DDRSS1_CTL_194_DATA 0x01000000
+#define DDRSS1_CTL_195_DATA 0x00000001
+#define DDRSS1_CTL_196_DATA 0x00000000
+#define DDRSS1_CTL_197_DATA 0x00000000
+#define DDRSS1_CTL_198_DATA 0x00000000
+#define DDRSS1_CTL_199_DATA 0x00000000
+#define DDRSS1_CTL_200_DATA 0x00000000
+#define DDRSS1_CTL_201_DATA 0x00000000
+#define DDRSS1_CTL_202_DATA 0x00000000
+#define DDRSS1_CTL_203_DATA 0x00000000
+#define DDRSS1_CTL_204_DATA 0x00000000
+#define DDRSS1_CTL_205_DATA 0x00000000
+#define DDRSS1_CTL_206_DATA 0x02000000
+#define DDRSS1_CTL_207_DATA 0x01080101
+#define DDRSS1_CTL_208_DATA 0x00000000
+#define DDRSS1_CTL_209_DATA 0x00000000
+#define DDRSS1_CTL_210_DATA 0x00000000
+#define DDRSS1_CTL_211_DATA 0x00000000
+#define DDRSS1_CTL_212_DATA 0x00000000
+#define DDRSS1_CTL_213_DATA 0x00000000
+#define DDRSS1_CTL_214_DATA 0x00000000
+#define DDRSS1_CTL_215_DATA 0x00000000
+#define DDRSS1_CTL_216_DATA 0x00000000
+#define DDRSS1_CTL_217_DATA 0x00000000
+#define DDRSS1_CTL_218_DATA 0x00000000
+#define DDRSS1_CTL_219_DATA 0x00000000
+#define DDRSS1_CTL_220_DATA 0x00000000
+#define DDRSS1_CTL_221_DATA 0x00000000
+#define DDRSS1_CTL_222_DATA 0x00001000
+#define DDRSS1_CTL_223_DATA 0x006403E8
+#define DDRSS1_CTL_224_DATA 0x00000000
+#define DDRSS1_CTL_225_DATA 0x00000000
+#define DDRSS1_CTL_226_DATA 0x00000000
+#define DDRSS1_CTL_227_DATA 0x15110000
+#define DDRSS1_CTL_228_DATA 0x00040C18
+#define DDRSS1_CTL_229_DATA 0xF000C000
+#define DDRSS1_CTL_230_DATA 0x0000F000
+#define DDRSS1_CTL_231_DATA 0x00000000
+#define DDRSS1_CTL_232_DATA 0x00000000
+#define DDRSS1_CTL_233_DATA 0xC0000000
+#define DDRSS1_CTL_234_DATA 0xF000F000
+#define DDRSS1_CTL_235_DATA 0x00000000
+#define DDRSS1_CTL_236_DATA 0x00000000
+#define DDRSS1_CTL_237_DATA 0x00000000
+#define DDRSS1_CTL_238_DATA 0xF000C000
+#define DDRSS1_CTL_239_DATA 0x0000F000
+#define DDRSS1_CTL_240_DATA 0x00000000
+#define DDRSS1_CTL_241_DATA 0x00000000
+#define DDRSS1_CTL_242_DATA 0x00030000
+#define DDRSS1_CTL_243_DATA 0x00000000
+#define DDRSS1_CTL_244_DATA 0x00000000
+#define DDRSS1_CTL_245_DATA 0x00000000
+#define DDRSS1_CTL_246_DATA 0x00000000
+#define DDRSS1_CTL_247_DATA 0x00000000
+#define DDRSS1_CTL_248_DATA 0x00000000
+#define DDRSS1_CTL_249_DATA 0x00000000
+#define DDRSS1_CTL_250_DATA 0x00000000
+#define DDRSS1_CTL_251_DATA 0x00000000
+#define DDRSS1_CTL_252_DATA 0x00000000
+#define DDRSS1_CTL_253_DATA 0x00000000
+#define DDRSS1_CTL_254_DATA 0x00000000
+#define DDRSS1_CTL_255_DATA 0x00000000
+#define DDRSS1_CTL_256_DATA 0x00000000
+#define DDRSS1_CTL_257_DATA 0x01000200
+#define DDRSS1_CTL_258_DATA 0x00370040
+#define DDRSS1_CTL_259_DATA 0x00020008
+#define DDRSS1_CTL_260_DATA 0x00400100
+#define DDRSS1_CTL_261_DATA 0x00400855
+#define DDRSS1_CTL_262_DATA 0x01000200
+#define DDRSS1_CTL_263_DATA 0x08550040
+#define DDRSS1_CTL_264_DATA 0x00000040
+#define DDRSS1_CTL_265_DATA 0x006B0003
+#define DDRSS1_CTL_266_DATA 0x0100006B
+#define DDRSS1_CTL_267_DATA 0x03030303
+#define DDRSS1_CTL_268_DATA 0x00000000
+#define DDRSS1_CTL_269_DATA 0x00000202
+#define DDRSS1_CTL_270_DATA 0x00001FFF
+#define DDRSS1_CTL_271_DATA 0x3FFF2000
+#define DDRSS1_CTL_272_DATA 0x03FF0000
+#define DDRSS1_CTL_273_DATA 0x000103FF
+#define DDRSS1_CTL_274_DATA 0x0FFF0B00
+#define DDRSS1_CTL_275_DATA 0x01010001
+#define DDRSS1_CTL_276_DATA 0x01010101
+#define DDRSS1_CTL_277_DATA 0x01180101
+#define DDRSS1_CTL_278_DATA 0x00030000
+#define DDRSS1_CTL_279_DATA 0x00000000
+#define DDRSS1_CTL_280_DATA 0x00000000
+#define DDRSS1_CTL_281_DATA 0x00000000
+#define DDRSS1_CTL_282_DATA 0x00000000
+#define DDRSS1_CTL_283_DATA 0x00000000
+#define DDRSS1_CTL_284_DATA 0x00000000
+#define DDRSS1_CTL_285_DATA 0x00000000
+#define DDRSS1_CTL_286_DATA 0x00040101
+#define DDRSS1_CTL_287_DATA 0x04010100
+#define DDRSS1_CTL_288_DATA 0x00000000
+#define DDRSS1_CTL_289_DATA 0x00000000
+#define DDRSS1_CTL_290_DATA 0x03030300
+#define DDRSS1_CTL_291_DATA 0x00010101
+#define DDRSS1_CTL_292_DATA 0x00000000
+#define DDRSS1_CTL_293_DATA 0x00000000
+#define DDRSS1_CTL_294_DATA 0x00000000
+#define DDRSS1_CTL_295_DATA 0x00000000
+#define DDRSS1_CTL_296_DATA 0x00000000
+#define DDRSS1_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_298_DATA 0x00000FFF
+#define DDRSS1_CTL_299_DATA 0x00000000
+#define DDRSS1_CTL_300_DATA 0x00000000
+#define DDRSS1_CTL_301_DATA 0x00000000
+#define DDRSS1_CTL_302_DATA 0x00000000
+#define DDRSS1_CTL_303_DATA 0x00000000
+#define DDRSS1_CTL_304_DATA 0x00000000
+#define DDRSS1_CTL_305_DATA 0x00000000
+#define DDRSS1_CTL_306_DATA 0x00000000
+#define DDRSS1_CTL_307_DATA 0x00000000
+#define DDRSS1_CTL_308_DATA 0x00000000
+#define DDRSS1_CTL_309_DATA 0x00000000
+#define DDRSS1_CTL_310_DATA 0x00000000
+#define DDRSS1_CTL_311_DATA 0x00000000
+#define DDRSS1_CTL_312_DATA 0x00000000
+#define DDRSS1_CTL_313_DATA 0x01000000
+#define DDRSS1_CTL_314_DATA 0x00020201
+#define DDRSS1_CTL_315_DATA 0x01000101
+#define DDRSS1_CTL_316_DATA 0x01010001
+#define DDRSS1_CTL_317_DATA 0x00010101
+#define DDRSS1_CTL_318_DATA 0x050A0A03
+#define DDRSS1_CTL_319_DATA 0x10082323
+#define DDRSS1_CTL_320_DATA 0x00090310
+#define DDRSS1_CTL_321_DATA 0x0B0C030F
+#define DDRSS1_CTL_322_DATA 0x0B0C0306
+#define DDRSS1_CTL_323_DATA 0x0C090006
+#define DDRSS1_CTL_324_DATA 0x0100000C
+#define DDRSS1_CTL_325_DATA 0x08040801
+#define DDRSS1_CTL_326_DATA 0x00000004
+#define DDRSS1_CTL_327_DATA 0x00000000
+#define DDRSS1_CTL_328_DATA 0x00010000
+#define DDRSS1_CTL_329_DATA 0x00280D00
+#define DDRSS1_CTL_330_DATA 0x00000001
+#define DDRSS1_CTL_331_DATA 0x00030001
+#define DDRSS1_CTL_332_DATA 0x00000000
+#define DDRSS1_CTL_333_DATA 0x00000000
+#define DDRSS1_CTL_334_DATA 0x00000000
+#define DDRSS1_CTL_335_DATA 0x00000000
+#define DDRSS1_CTL_336_DATA 0x00000000
+#define DDRSS1_CTL_337_DATA 0x00000000
+#define DDRSS1_CTL_338_DATA 0x00000000
+#define DDRSS1_CTL_339_DATA 0x00000000
+#define DDRSS1_CTL_340_DATA 0x01000000
+#define DDRSS1_CTL_341_DATA 0x00000001
+#define DDRSS1_CTL_342_DATA 0x00010100
+#define DDRSS1_CTL_343_DATA 0x03030000
+#define DDRSS1_CTL_344_DATA 0x00000000
+#define DDRSS1_CTL_345_DATA 0x00000000
+#define DDRSS1_CTL_346_DATA 0x00000000
+#define DDRSS1_CTL_347_DATA 0x00000000
+#define DDRSS1_CTL_348_DATA 0x00000000
+#define DDRSS1_CTL_349_DATA 0x00000000
+#define DDRSS1_CTL_350_DATA 0x00000000
+#define DDRSS1_CTL_351_DATA 0x00000000
+#define DDRSS1_CTL_352_DATA 0x00000000
+#define DDRSS1_CTL_353_DATA 0x00000000
+#define DDRSS1_CTL_354_DATA 0x00000000
+#define DDRSS1_CTL_355_DATA 0x00000000
+#define DDRSS1_CTL_356_DATA 0x00000000
+#define DDRSS1_CTL_357_DATA 0x00000000
+#define DDRSS1_CTL_358_DATA 0x00000000
+#define DDRSS1_CTL_359_DATA 0x00000000
+#define DDRSS1_CTL_360_DATA 0x000556AA
+#define DDRSS1_CTL_361_DATA 0x000AAAAA
+#define DDRSS1_CTL_362_DATA 0x000AA955
+#define DDRSS1_CTL_363_DATA 0x00055555
+#define DDRSS1_CTL_364_DATA 0x000B3133
+#define DDRSS1_CTL_365_DATA 0x0004CD33
+#define DDRSS1_CTL_366_DATA 0x0004CECC
+#define DDRSS1_CTL_367_DATA 0x000B32CC
+#define DDRSS1_CTL_368_DATA 0x00010300
+#define DDRSS1_CTL_369_DATA 0x03000100
+#define DDRSS1_CTL_370_DATA 0x00000000
+#define DDRSS1_CTL_371_DATA 0x00000000
+#define DDRSS1_CTL_372_DATA 0x00000000
+#define DDRSS1_CTL_373_DATA 0x00000000
+#define DDRSS1_CTL_374_DATA 0x00000000
+#define DDRSS1_CTL_375_DATA 0x00000000
+#define DDRSS1_CTL_376_DATA 0x00000000
+#define DDRSS1_CTL_377_DATA 0x00010000
+#define DDRSS1_CTL_378_DATA 0x00000404
+#define DDRSS1_CTL_379_DATA 0x00000000
+#define DDRSS1_CTL_380_DATA 0x00000000
+#define DDRSS1_CTL_381_DATA 0x00000000
+#define DDRSS1_CTL_382_DATA 0x00000000
+#define DDRSS1_CTL_383_DATA 0x00000000
+#define DDRSS1_CTL_384_DATA 0x00000000
+#define DDRSS1_CTL_385_DATA 0x00000000
+#define DDRSS1_CTL_386_DATA 0x00000000
+#define DDRSS1_CTL_387_DATA 0x3A3A1B00
+#define DDRSS1_CTL_388_DATA 0x000A0000
+#define DDRSS1_CTL_389_DATA 0x000000C6
+#define DDRSS1_CTL_390_DATA 0x00000200
+#define DDRSS1_CTL_391_DATA 0x00000200
+#define DDRSS1_CTL_392_DATA 0x00000200
+#define DDRSS1_CTL_393_DATA 0x00000200
+#define DDRSS1_CTL_394_DATA 0x00000270
+#define DDRSS1_CTL_395_DATA 0x000007BC
+#define DDRSS1_CTL_396_DATA 0x00000204
+#define DDRSS1_CTL_397_DATA 0x0000206A
+#define DDRSS1_CTL_398_DATA 0x00000200
+#define DDRSS1_CTL_399_DATA 0x00000200
+#define DDRSS1_CTL_400_DATA 0x00000200
+#define DDRSS1_CTL_401_DATA 0x00000200
+#define DDRSS1_CTL_402_DATA 0x0000613E
+#define DDRSS1_CTL_403_DATA 0x00014424
+#define DDRSS1_CTL_404_DATA 0x00000E19
+#define DDRSS1_CTL_405_DATA 0x0000206A
+#define DDRSS1_CTL_406_DATA 0x00000200
+#define DDRSS1_CTL_407_DATA 0x00000200
+#define DDRSS1_CTL_408_DATA 0x00000200
+#define DDRSS1_CTL_409_DATA 0x00000200
+#define DDRSS1_CTL_410_DATA 0x0000613E
+#define DDRSS1_CTL_411_DATA 0x00014424
+#define DDRSS1_CTL_412_DATA 0x02020E19
+#define DDRSS1_CTL_413_DATA 0x03030202
+#define DDRSS1_CTL_414_DATA 0x00000022
+#define DDRSS1_CTL_415_DATA 0x00000000
+#define DDRSS1_CTL_416_DATA 0x00000000
+#define DDRSS1_CTL_417_DATA 0x00001403
+#define DDRSS1_CTL_418_DATA 0x000007D0
+#define DDRSS1_CTL_419_DATA 0x00000000
+#define DDRSS1_CTL_420_DATA 0x00000000
+#define DDRSS1_CTL_421_DATA 0x00030000
+#define DDRSS1_CTL_422_DATA 0x0007001F
+#define DDRSS1_CTL_423_DATA 0x001B0033
+#define DDRSS1_CTL_424_DATA 0x001B0033
+#define DDRSS1_CTL_425_DATA 0x00000000
+#define DDRSS1_CTL_426_DATA 0x00000000
+#define DDRSS1_CTL_427_DATA 0x02000000
+#define DDRSS1_CTL_428_DATA 0x01000404
+#define DDRSS1_CTL_429_DATA 0x0B220B22
+#define DDRSS1_CTL_430_DATA 0x00000105
+#define DDRSS1_CTL_431_DATA 0x00010101
+#define DDRSS1_CTL_432_DATA 0x00010101
+#define DDRSS1_CTL_433_DATA 0x00010001
+#define DDRSS1_CTL_434_DATA 0x00000101
+#define DDRSS1_CTL_435_DATA 0x02000201
+#define DDRSS1_CTL_436_DATA 0x02010000
+#define DDRSS1_CTL_437_DATA 0x00000200
+#define DDRSS1_CTL_438_DATA 0x28060000
+#define DDRSS1_CTL_439_DATA 0x00000128
+#define DDRSS1_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_442_DATA 0x00000000
+#define DDRSS1_CTL_443_DATA 0x00000000
+#define DDRSS1_CTL_444_DATA 0x00000000
+#define DDRSS1_CTL_445_DATA 0x00000000
+#define DDRSS1_CTL_446_DATA 0x00000000
+#define DDRSS1_CTL_447_DATA 0x00000000
+#define DDRSS1_CTL_448_DATA 0x00000000
+#define DDRSS1_CTL_449_DATA 0x00000000
+#define DDRSS1_CTL_450_DATA 0x00000000
+#define DDRSS1_CTL_451_DATA 0x00000000
+#define DDRSS1_CTL_452_DATA 0x00000000
+#define DDRSS1_CTL_453_DATA 0x00000000
+#define DDRSS1_CTL_454_DATA 0x00000000
+#define DDRSS1_CTL_455_DATA 0x00000000
+#define DDRSS1_CTL_456_DATA 0x00000000
+#define DDRSS1_CTL_457_DATA 0x00000000
+#define DDRSS1_CTL_458_DATA 0x00000000
+
+#define DDRSS1_PI_00_DATA 0x00000B00
+#define DDRSS1_PI_01_DATA 0x00000000
+#define DDRSS1_PI_02_DATA 0x00000000
+#define DDRSS1_PI_03_DATA 0x00000000
+#define DDRSS1_PI_04_DATA 0x00000000
+#define DDRSS1_PI_05_DATA 0x00000101
+#define DDRSS1_PI_06_DATA 0x00640000
+#define DDRSS1_PI_07_DATA 0x00000001
+#define DDRSS1_PI_08_DATA 0x00000000
+#define DDRSS1_PI_09_DATA 0x00000000
+#define DDRSS1_PI_10_DATA 0x00000000
+#define DDRSS1_PI_11_DATA 0x00000000
+#define DDRSS1_PI_12_DATA 0x00000003
+#define DDRSS1_PI_13_DATA 0x00010001
+#define DDRSS1_PI_14_DATA 0x0800000F
+#define DDRSS1_PI_15_DATA 0x00000103
+#define DDRSS1_PI_16_DATA 0x00000005
+#define DDRSS1_PI_17_DATA 0x00000000
+#define DDRSS1_PI_18_DATA 0x00000000
+#define DDRSS1_PI_19_DATA 0x00000000
+#define DDRSS1_PI_20_DATA 0x00000000
+#define DDRSS1_PI_21_DATA 0x00000000
+#define DDRSS1_PI_22_DATA 0x00000000
+#define DDRSS1_PI_23_DATA 0x00000000
+#define DDRSS1_PI_24_DATA 0x00000000
+#define DDRSS1_PI_25_DATA 0x00000000
+#define DDRSS1_PI_26_DATA 0x00010100
+#define DDRSS1_PI_27_DATA 0x00280A00
+#define DDRSS1_PI_28_DATA 0x00000000
+#define DDRSS1_PI_29_DATA 0x0F000000
+#define DDRSS1_PI_30_DATA 0x00003200
+#define DDRSS1_PI_31_DATA 0x00000000
+#define DDRSS1_PI_32_DATA 0x00000000
+#define DDRSS1_PI_33_DATA 0x01010102
+#define DDRSS1_PI_34_DATA 0x00000000
+#define DDRSS1_PI_35_DATA 0x000000AA
+#define DDRSS1_PI_36_DATA 0x00000055
+#define DDRSS1_PI_37_DATA 0x000000B5
+#define DDRSS1_PI_38_DATA 0x0000004A
+#define DDRSS1_PI_39_DATA 0x00000056
+#define DDRSS1_PI_40_DATA 0x000000A9
+#define DDRSS1_PI_41_DATA 0x000000A9
+#define DDRSS1_PI_42_DATA 0x000000B5
+#define DDRSS1_PI_43_DATA 0x00000000
+#define DDRSS1_PI_44_DATA 0x00000000
+#define DDRSS1_PI_45_DATA 0x000F0F00
+#define DDRSS1_PI_46_DATA 0x0000001B
+#define DDRSS1_PI_47_DATA 0x000007D0
+#define DDRSS1_PI_48_DATA 0x00000300
+#define DDRSS1_PI_49_DATA 0x00000000
+#define DDRSS1_PI_50_DATA 0x00000000
+#define DDRSS1_PI_51_DATA 0x01000000
+#define DDRSS1_PI_52_DATA 0x00010101
+#define DDRSS1_PI_53_DATA 0x00000000
+#define DDRSS1_PI_54_DATA 0x00030000
+#define DDRSS1_PI_55_DATA 0x0F000000
+#define DDRSS1_PI_56_DATA 0x00000017
+#define DDRSS1_PI_57_DATA 0x00000000
+#define DDRSS1_PI_58_DATA 0x00000000
+#define DDRSS1_PI_59_DATA 0x00000000
+#define DDRSS1_PI_60_DATA 0x0A0A140A
+#define DDRSS1_PI_61_DATA 0x10020201
+#define DDRSS1_PI_62_DATA 0x00020805
+#define DDRSS1_PI_63_DATA 0x01000404
+#define DDRSS1_PI_64_DATA 0x00000000
+#define DDRSS1_PI_65_DATA 0x00000000
+#define DDRSS1_PI_66_DATA 0x00000100
+#define DDRSS1_PI_67_DATA 0x0002020F
+#define DDRSS1_PI_68_DATA 0x00340000
+#define DDRSS1_PI_69_DATA 0x00000000
+#define DDRSS1_PI_70_DATA 0x00000000
+#define DDRSS1_PI_71_DATA 0x0000FFFF
+#define DDRSS1_PI_72_DATA 0x01000000
+#define DDRSS1_PI_73_DATA 0x00080000
+#define DDRSS1_PI_74_DATA 0x02000200
+#define DDRSS1_PI_75_DATA 0x01000100
+#define DDRSS1_PI_76_DATA 0x01000000
+#define DDRSS1_PI_77_DATA 0x02000200
+#define DDRSS1_PI_78_DATA 0x00000200
+#define DDRSS1_PI_79_DATA 0x00000000
+#define DDRSS1_PI_80_DATA 0x00000000
+#define DDRSS1_PI_81_DATA 0x00000000
+#define DDRSS1_PI_82_DATA 0x00000000
+#define DDRSS1_PI_83_DATA 0x00000000
+#define DDRSS1_PI_84_DATA 0x00000000
+#define DDRSS1_PI_85_DATA 0x00000000
+#define DDRSS1_PI_86_DATA 0x00000000
+#define DDRSS1_PI_87_DATA 0x00000000
+#define DDRSS1_PI_88_DATA 0x00000000
+#define DDRSS1_PI_89_DATA 0x00000000
+#define DDRSS1_PI_90_DATA 0x00000000
+#define DDRSS1_PI_91_DATA 0x00000400
+#define DDRSS1_PI_92_DATA 0x02010000
+#define DDRSS1_PI_93_DATA 0x00080003
+#define DDRSS1_PI_94_DATA 0x00080000
+#define DDRSS1_PI_95_DATA 0x00000001
+#define DDRSS1_PI_96_DATA 0x00000000
+#define DDRSS1_PI_97_DATA 0x0000AA00
+#define DDRSS1_PI_98_DATA 0x00000000
+#define DDRSS1_PI_99_DATA 0x00000000
+#define DDRSS1_PI_100_DATA 0x00010000
+#define DDRSS1_PI_101_DATA 0x00000000
+#define DDRSS1_PI_102_DATA 0x00000000
+#define DDRSS1_PI_103_DATA 0x00000000
+#define DDRSS1_PI_104_DATA 0x00000000
+#define DDRSS1_PI_105_DATA 0x00000000
+#define DDRSS1_PI_106_DATA 0x00000000
+#define DDRSS1_PI_107_DATA 0x00000000
+#define DDRSS1_PI_108_DATA 0x00000000
+#define DDRSS1_PI_109_DATA 0x00000000
+#define DDRSS1_PI_110_DATA 0x00000000
+#define DDRSS1_PI_111_DATA 0x00000000
+#define DDRSS1_PI_112_DATA 0x00000000
+#define DDRSS1_PI_113_DATA 0x00000000
+#define DDRSS1_PI_114_DATA 0x00000000
+#define DDRSS1_PI_115_DATA 0x00000000
+#define DDRSS1_PI_116_DATA 0x00000000
+#define DDRSS1_PI_117_DATA 0x00000000
+#define DDRSS1_PI_118_DATA 0x00000000
+#define DDRSS1_PI_119_DATA 0x00000000
+#define DDRSS1_PI_120_DATA 0x00000000
+#define DDRSS1_PI_121_DATA 0x00000000
+#define DDRSS1_PI_122_DATA 0x00000000
+#define DDRSS1_PI_123_DATA 0x00000000
+#define DDRSS1_PI_124_DATA 0x00000000
+#define DDRSS1_PI_125_DATA 0x00000008
+#define DDRSS1_PI_126_DATA 0x00000000
+#define DDRSS1_PI_127_DATA 0x00000000
+#define DDRSS1_PI_128_DATA 0x00000000
+#define DDRSS1_PI_129_DATA 0x00000000
+#define DDRSS1_PI_130_DATA 0x00000000
+#define DDRSS1_PI_131_DATA 0x00000000
+#define DDRSS1_PI_132_DATA 0x00000000
+#define DDRSS1_PI_133_DATA 0x00000000
+#define DDRSS1_PI_134_DATA 0x00000002
+#define DDRSS1_PI_135_DATA 0x00000000
+#define DDRSS1_PI_136_DATA 0x00000000
+#define DDRSS1_PI_137_DATA 0x0000000A
+#define DDRSS1_PI_138_DATA 0x00000019
+#define DDRSS1_PI_139_DATA 0x00000100
+#define DDRSS1_PI_140_DATA 0x00000000
+#define DDRSS1_PI_141_DATA 0x00000000
+#define DDRSS1_PI_142_DATA 0x00000000
+#define DDRSS1_PI_143_DATA 0x00000000
+#define DDRSS1_PI_144_DATA 0x01000000
+#define DDRSS1_PI_145_DATA 0x00010003
+#define DDRSS1_PI_146_DATA 0x02000101
+#define DDRSS1_PI_147_DATA 0x01030001
+#define DDRSS1_PI_148_DATA 0x00010400
+#define DDRSS1_PI_149_DATA 0x06000105
+#define DDRSS1_PI_150_DATA 0x01070001
+#define DDRSS1_PI_151_DATA 0x00000000
+#define DDRSS1_PI_152_DATA 0x00000000
+#define DDRSS1_PI_153_DATA 0x00000000
+#define DDRSS1_PI_154_DATA 0x00010001
+#define DDRSS1_PI_155_DATA 0x00000000
+#define DDRSS1_PI_156_DATA 0x00000000
+#define DDRSS1_PI_157_DATA 0x00000000
+#define DDRSS1_PI_158_DATA 0x00000000
+#define DDRSS1_PI_159_DATA 0x00000401
+#define DDRSS1_PI_160_DATA 0x00000000
+#define DDRSS1_PI_161_DATA 0x05010000
+#define DDRSS1_PI_162_DATA 0x00000001
+#define DDRSS1_PI_163_DATA 0x2B2B0201
+#define DDRSS1_PI_164_DATA 0x00000034
+#define DDRSS1_PI_165_DATA 0x00000068
+#define DDRSS1_PI_166_DATA 0x00020068
+#define DDRSS1_PI_167_DATA 0x02000200
+#define DDRSS1_PI_168_DATA 0x50120C04
+#define DDRSS1_PI_169_DATA 0x00155012
+#define DDRSS1_PI_170_DATA 0x00000068
+#define DDRSS1_PI_171_DATA 0x0000032B
+#define DDRSS1_PI_172_DATA 0x00001035
+#define DDRSS1_PI_173_DATA 0x0000032B
+#define DDRSS1_PI_174_DATA 0x04001035
+#define DDRSS1_PI_175_DATA 0x01010404
+#define DDRSS1_PI_176_DATA 0x00001500
+#define DDRSS1_PI_177_DATA 0x00150015
+#define DDRSS1_PI_178_DATA 0x01000100
+#define DDRSS1_PI_179_DATA 0x00000100
+#define DDRSS1_PI_180_DATA 0x00000000
+#define DDRSS1_PI_181_DATA 0x01010101
+#define DDRSS1_PI_182_DATA 0x00000000
+#define DDRSS1_PI_183_DATA 0x00000000
+#define DDRSS1_PI_184_DATA 0x00000000
+#define DDRSS1_PI_185_DATA 0x19040000
+#define DDRSS1_PI_186_DATA 0x0E0E0219
+#define DDRSS1_PI_187_DATA 0x00040402
+#define DDRSS1_PI_188_DATA 0x000D0035
+#define DDRSS1_PI_189_DATA 0x00218049
+#define DDRSS1_PI_190_DATA 0x00218049
+#define DDRSS1_PI_191_DATA 0x01000101
+#define DDRSS1_PI_192_DATA 0x0004000E
+#define DDRSS1_PI_193_DATA 0x00040216
+#define DDRSS1_PI_194_DATA 0x01000216
+#define DDRSS1_PI_195_DATA 0x000F000F
+#define DDRSS1_PI_196_DATA 0x02170100
+#define DDRSS1_PI_197_DATA 0x01000217
+#define DDRSS1_PI_198_DATA 0x02170217
+#define DDRSS1_PI_199_DATA 0x2F1B3200
+#define DDRSS1_PI_200_DATA 0x01012F1B
+#define DDRSS1_PI_201_DATA 0x0A070601
+#define DDRSS1_PI_202_DATA 0x1F130A0D
+#define DDRSS1_PI_203_DATA 0x1F130A14
+#define DDRSS1_PI_204_DATA 0x0000C014
+#define DDRSS1_PI_205_DATA 0x00C01000
+#define DDRSS1_PI_206_DATA 0x00C01000
+#define DDRSS1_PI_207_DATA 0x00021000
+#define DDRSS1_PI_208_DATA 0x0024000E
+#define DDRSS1_PI_209_DATA 0x00240216
+#define DDRSS1_PI_210_DATA 0x00110216
+#define DDRSS1_PI_211_DATA 0x32000056
+#define DDRSS1_PI_212_DATA 0x00000101
+#define DDRSS1_PI_213_DATA 0x005F0036
+#define DDRSS1_PI_214_DATA 0x03013212
+#define DDRSS1_PI_215_DATA 0x00003600
+#define DDRSS1_PI_216_DATA 0x3212005F
+#define DDRSS1_PI_217_DATA 0x09000001
+#define DDRSS1_PI_218_DATA 0x06010504
+#define DDRSS1_PI_219_DATA 0x04000364
+#define DDRSS1_PI_220_DATA 0x0A032001
+#define DDRSS1_PI_221_DATA 0x2C31110A
+#define DDRSS1_PI_222_DATA 0x00002918
+#define DDRSS1_PI_223_DATA 0x6000838E
+#define DDRSS1_PI_224_DATA 0x1E202008
+#define DDRSS1_PI_225_DATA 0x2C311116
+#define DDRSS1_PI_226_DATA 0x00002918
+#define DDRSS1_PI_227_DATA 0x6000838E
+#define DDRSS1_PI_228_DATA 0x1E202008
+#define DDRSS1_PI_229_DATA 0x0000C616
+#define DDRSS1_PI_230_DATA 0x000007BC
+#define DDRSS1_PI_231_DATA 0x0000206A
+#define DDRSS1_PI_232_DATA 0x00014424
+#define DDRSS1_PI_233_DATA 0x0000206A
+#define DDRSS1_PI_234_DATA 0x00014424
+#define DDRSS1_PI_235_DATA 0x033B0016
+#define DDRSS1_PI_236_DATA 0x0303033B
+#define DDRSS1_PI_237_DATA 0x002AF803
+#define DDRSS1_PI_238_DATA 0x0001ADAF
+#define DDRSS1_PI_239_DATA 0x00000005
+#define DDRSS1_PI_240_DATA 0x0000006E
+#define DDRSS1_PI_241_DATA 0x00000016
+#define DDRSS1_PI_242_DATA 0x000681C8
+#define DDRSS1_PI_243_DATA 0x0001ADAF
+#define DDRSS1_PI_244_DATA 0x00000005
+#define DDRSS1_PI_245_DATA 0x000010A9
+#define DDRSS1_PI_246_DATA 0x0000033B
+#define DDRSS1_PI_247_DATA 0x000681C8
+#define DDRSS1_PI_248_DATA 0x0001ADAF
+#define DDRSS1_PI_249_DATA 0x00000005
+#define DDRSS1_PI_250_DATA 0x000010A9
+#define DDRSS1_PI_251_DATA 0x0100033B
+#define DDRSS1_PI_252_DATA 0x00370040
+#define DDRSS1_PI_253_DATA 0x00010008
+#define DDRSS1_PI_254_DATA 0x08550040
+#define DDRSS1_PI_255_DATA 0x00010040
+#define DDRSS1_PI_256_DATA 0x08550040
+#define DDRSS1_PI_257_DATA 0x00000340
+#define DDRSS1_PI_258_DATA 0x006B006B
+#define DDRSS1_PI_259_DATA 0x08040404
+#define DDRSS1_PI_260_DATA 0x00000055
+#define DDRSS1_PI_261_DATA 0x55083C5A
+#define DDRSS1_PI_262_DATA 0x5A000000
+#define DDRSS1_PI_263_DATA 0x0055083C
+#define DDRSS1_PI_264_DATA 0x3C5A0000
+#define DDRSS1_PI_265_DATA 0x00005508
+#define DDRSS1_PI_266_DATA 0x0C3C5A00
+#define DDRSS1_PI_267_DATA 0x080F0E0D
+#define DDRSS1_PI_268_DATA 0x000B0A09
+#define DDRSS1_PI_269_DATA 0x00030201
+#define DDRSS1_PI_270_DATA 0x01000000
+#define DDRSS1_PI_271_DATA 0x04020201
+#define DDRSS1_PI_272_DATA 0x00080804
+#define DDRSS1_PI_273_DATA 0x00000000
+#define DDRSS1_PI_274_DATA 0x00000000
+#define DDRSS1_PI_275_DATA 0x00F30084
+#define DDRSS1_PI_276_DATA 0x00160000
+#define DDRSS1_PI_277_DATA 0x35F33FF4
+#define DDRSS1_PI_278_DATA 0x00160F27
+#define DDRSS1_PI_279_DATA 0x35F33FF4
+#define DDRSS1_PI_280_DATA 0x00160F27
+#define DDRSS1_PI_281_DATA 0x00F30084
+#define DDRSS1_PI_282_DATA 0x00160000
+#define DDRSS1_PI_283_DATA 0x35F33FF4
+#define DDRSS1_PI_284_DATA 0x00160F27
+#define DDRSS1_PI_285_DATA 0x35F33FF4
+#define DDRSS1_PI_286_DATA 0x00160F27
+#define DDRSS1_PI_287_DATA 0x00F30084
+#define DDRSS1_PI_288_DATA 0x00160000
+#define DDRSS1_PI_289_DATA 0x35F33FF4
+#define DDRSS1_PI_290_DATA 0x00160F27
+#define DDRSS1_PI_291_DATA 0x35F33FF4
+#define DDRSS1_PI_292_DATA 0x00160F27
+#define DDRSS1_PI_293_DATA 0x00F30084
+#define DDRSS1_PI_294_DATA 0x00160000
+#define DDRSS1_PI_295_DATA 0x35F33FF4
+#define DDRSS1_PI_296_DATA 0x00160F27
+#define DDRSS1_PI_297_DATA 0x35F33FF4
+#define DDRSS1_PI_298_DATA 0x00160F27
+#define DDRSS1_PI_299_DATA 0x00000000
+
+#define DDRSS1_PHY_00_DATA 0x000004F0
+#define DDRSS1_PHY_01_DATA 0x00000000
+#define DDRSS1_PHY_02_DATA 0x00030200
+#define DDRSS1_PHY_03_DATA 0x00000000
+#define DDRSS1_PHY_04_DATA 0x00000000
+#define DDRSS1_PHY_05_DATA 0x01030000
+#define DDRSS1_PHY_06_DATA 0x00010000
+#define DDRSS1_PHY_07_DATA 0x01030004
+#define DDRSS1_PHY_08_DATA 0x01000000
+#define DDRSS1_PHY_09_DATA 0x00000000
+#define DDRSS1_PHY_10_DATA 0x00000000
+#define DDRSS1_PHY_11_DATA 0x01000001
+#define DDRSS1_PHY_12_DATA 0x00000200
+#define DDRSS1_PHY_13_DATA 0x000800C0
+#define DDRSS1_PHY_14_DATA 0x060100CC
+#define DDRSS1_PHY_15_DATA 0x00030066
+#define DDRSS1_PHY_16_DATA 0x00000000
+#define DDRSS1_PHY_17_DATA 0x00000301
+#define DDRSS1_PHY_18_DATA 0x0000AAAA
+#define DDRSS1_PHY_19_DATA 0x00005555
+#define DDRSS1_PHY_20_DATA 0x0000B5B5
+#define DDRSS1_PHY_21_DATA 0x00004A4A
+#define DDRSS1_PHY_22_DATA 0x00005656
+#define DDRSS1_PHY_23_DATA 0x0000A9A9
+#define DDRSS1_PHY_24_DATA 0x0000A9A9
+#define DDRSS1_PHY_25_DATA 0x0000B5B5
+#define DDRSS1_PHY_26_DATA 0x00000000
+#define DDRSS1_PHY_27_DATA 0x00000000
+#define DDRSS1_PHY_28_DATA 0x2A000000
+#define DDRSS1_PHY_29_DATA 0x00000808
+#define DDRSS1_PHY_30_DATA 0x0F000000
+#define DDRSS1_PHY_31_DATA 0x00000F08
+#define DDRSS1_PHY_32_DATA 0x10400000
+#define DDRSS1_PHY_33_DATA 0x0C002006
+#define DDRSS1_PHY_34_DATA 0x00000000
+#define DDRSS1_PHY_35_DATA 0x00000000
+#define DDRSS1_PHY_36_DATA 0x55555555
+#define DDRSS1_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_38_DATA 0x55555555
+#define DDRSS1_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_40_DATA 0x00005555
+#define DDRSS1_PHY_41_DATA 0x01000100
+#define DDRSS1_PHY_42_DATA 0x00800180
+#define DDRSS1_PHY_43_DATA 0x00000001
+#define DDRSS1_PHY_44_DATA 0x00000000
+#define DDRSS1_PHY_45_DATA 0x00000000
+#define DDRSS1_PHY_46_DATA 0x00000000
+#define DDRSS1_PHY_47_DATA 0x00000000
+#define DDRSS1_PHY_48_DATA 0x00000000
+#define DDRSS1_PHY_49_DATA 0x00000000
+#define DDRSS1_PHY_50_DATA 0x00000000
+#define DDRSS1_PHY_51_DATA 0x00000000
+#define DDRSS1_PHY_52_DATA 0x00000000
+#define DDRSS1_PHY_53_DATA 0x00000000
+#define DDRSS1_PHY_54_DATA 0x00000000
+#define DDRSS1_PHY_55_DATA 0x00000000
+#define DDRSS1_PHY_56_DATA 0x00000000
+#define DDRSS1_PHY_57_DATA 0x00000000
+#define DDRSS1_PHY_58_DATA 0x00000000
+#define DDRSS1_PHY_59_DATA 0x00000000
+#define DDRSS1_PHY_60_DATA 0x00000000
+#define DDRSS1_PHY_61_DATA 0x00000000
+#define DDRSS1_PHY_62_DATA 0x00000000
+#define DDRSS1_PHY_63_DATA 0x00000000
+#define DDRSS1_PHY_64_DATA 0x00000000
+#define DDRSS1_PHY_65_DATA 0x00000000
+#define DDRSS1_PHY_66_DATA 0x00000104
+#define DDRSS1_PHY_67_DATA 0x00000120
+#define DDRSS1_PHY_68_DATA 0x00000000
+#define DDRSS1_PHY_69_DATA 0x00000000
+#define DDRSS1_PHY_70_DATA 0x00000000
+#define DDRSS1_PHY_71_DATA 0x00000000
+#define DDRSS1_PHY_72_DATA 0x00000000
+#define DDRSS1_PHY_73_DATA 0x00000000
+#define DDRSS1_PHY_74_DATA 0x00000000
+#define DDRSS1_PHY_75_DATA 0x00000001
+#define DDRSS1_PHY_76_DATA 0x07FF0000
+#define DDRSS1_PHY_77_DATA 0x0080081F
+#define DDRSS1_PHY_78_DATA 0x00081020
+#define DDRSS1_PHY_79_DATA 0x04010000
+#define DDRSS1_PHY_80_DATA 0x00000000
+#define DDRSS1_PHY_81_DATA 0x00000000
+#define DDRSS1_PHY_82_DATA 0x00000000
+#define DDRSS1_PHY_83_DATA 0x00000100
+#define DDRSS1_PHY_84_DATA 0x01CC0C01
+#define DDRSS1_PHY_85_DATA 0x1003CC0C
+#define DDRSS1_PHY_86_DATA 0x20000140
+#define DDRSS1_PHY_87_DATA 0x07FF0200
+#define DDRSS1_PHY_88_DATA 0x0000DD01
+#define DDRSS1_PHY_89_DATA 0x10100303
+#define DDRSS1_PHY_90_DATA 0x10101010
+#define DDRSS1_PHY_91_DATA 0x10101010
+#define DDRSS1_PHY_92_DATA 0x00021010
+#define DDRSS1_PHY_93_DATA 0x00100010
+#define DDRSS1_PHY_94_DATA 0x00100010
+#define DDRSS1_PHY_95_DATA 0x00100010
+#define DDRSS1_PHY_96_DATA 0x00100010
+#define DDRSS1_PHY_97_DATA 0x00050010
+#define DDRSS1_PHY_98_DATA 0x51517041
+#define DDRSS1_PHY_99_DATA 0x31C06001
+#define DDRSS1_PHY_100_DATA 0x07AB01AB
+#define DDRSS1_PHY_101_DATA 0x00C0C001
+#define DDRSS1_PHY_102_DATA 0x0E0D0101
+#define DDRSS1_PHY_103_DATA 0x10001000
+#define DDRSS1_PHY_104_DATA 0x0C083E42
+#define DDRSS1_PHY_105_DATA 0x0F0C3701
+#define DDRSS1_PHY_106_DATA 0x01000140
+#define DDRSS1_PHY_107_DATA 0x0C000420
+#define DDRSS1_PHY_108_DATA 0x00000198
+#define DDRSS1_PHY_109_DATA 0x0A0000D0
+#define DDRSS1_PHY_110_DATA 0x00030200
+#define DDRSS1_PHY_111_DATA 0x02800000
+#define DDRSS1_PHY_112_DATA 0x80800000
+#define DDRSS1_PHY_113_DATA 0x000E2010
+#define DDRSS1_PHY_114_DATA 0x76543210
+#define DDRSS1_PHY_115_DATA 0x00000008
+#define DDRSS1_PHY_116_DATA 0x02800280
+#define DDRSS1_PHY_117_DATA 0x02800280
+#define DDRSS1_PHY_118_DATA 0x02800280
+#define DDRSS1_PHY_119_DATA 0x02800280
+#define DDRSS1_PHY_120_DATA 0x00000280
+#define DDRSS1_PHY_121_DATA 0x0000A000
+#define DDRSS1_PHY_122_DATA 0x00A000A0
+#define DDRSS1_PHY_123_DATA 0x00A000A0
+#define DDRSS1_PHY_124_DATA 0x00A000A0
+#define DDRSS1_PHY_125_DATA 0x00A000A0
+#define DDRSS1_PHY_126_DATA 0x00A000A0
+#define DDRSS1_PHY_127_DATA 0x00A000A0
+#define DDRSS1_PHY_128_DATA 0x00A000A0
+#define DDRSS1_PHY_129_DATA 0x00A000A0
+#define DDRSS1_PHY_130_DATA 0x01C200A0
+#define DDRSS1_PHY_131_DATA 0x01A00005
+#define DDRSS1_PHY_132_DATA 0x00000000
+#define DDRSS1_PHY_133_DATA 0x00000000
+#define DDRSS1_PHY_134_DATA 0x00080200
+#define DDRSS1_PHY_135_DATA 0x00000000
+#define DDRSS1_PHY_136_DATA 0x20202000
+#define DDRSS1_PHY_137_DATA 0x20202020
+#define DDRSS1_PHY_138_DATA 0xF0F02020
+#define DDRSS1_PHY_139_DATA 0x00000000
+#define DDRSS1_PHY_140_DATA 0x00000000
+#define DDRSS1_PHY_141_DATA 0x00000000
+#define DDRSS1_PHY_142_DATA 0x00000000
+#define DDRSS1_PHY_143_DATA 0x00000000
+#define DDRSS1_PHY_144_DATA 0x00000000
+#define DDRSS1_PHY_145_DATA 0x00000000
+#define DDRSS1_PHY_146_DATA 0x00000000
+#define DDRSS1_PHY_147_DATA 0x00000000
+#define DDRSS1_PHY_148_DATA 0x00000000
+#define DDRSS1_PHY_149_DATA 0x00000000
+#define DDRSS1_PHY_150_DATA 0x00000000
+#define DDRSS1_PHY_151_DATA 0x00000000
+#define DDRSS1_PHY_152_DATA 0x00000000
+#define DDRSS1_PHY_153_DATA 0x00000000
+#define DDRSS1_PHY_154_DATA 0x00000000
+#define DDRSS1_PHY_155_DATA 0x00000000
+#define DDRSS1_PHY_156_DATA 0x00000000
+#define DDRSS1_PHY_157_DATA 0x00000000
+#define DDRSS1_PHY_158_DATA 0x00000000
+#define DDRSS1_PHY_159_DATA 0x00000000
+#define DDRSS1_PHY_160_DATA 0x00000000
+#define DDRSS1_PHY_161_DATA 0x00000000
+#define DDRSS1_PHY_162_DATA 0x00000000
+#define DDRSS1_PHY_163_DATA 0x00000000
+#define DDRSS1_PHY_164_DATA 0x00000000
+#define DDRSS1_PHY_165_DATA 0x00000000
+#define DDRSS1_PHY_166_DATA 0x00000000
+#define DDRSS1_PHY_167_DATA 0x00000000
+#define DDRSS1_PHY_168_DATA 0x00000000
+#define DDRSS1_PHY_169_DATA 0x00000000
+#define DDRSS1_PHY_170_DATA 0x00000000
+#define DDRSS1_PHY_171_DATA 0x00000000
+#define DDRSS1_PHY_172_DATA 0x00000000
+#define DDRSS1_PHY_173_DATA 0x00000000
+#define DDRSS1_PHY_174_DATA 0x00000000
+#define DDRSS1_PHY_175_DATA 0x00000000
+#define DDRSS1_PHY_176_DATA 0x00000000
+#define DDRSS1_PHY_177_DATA 0x00000000
+#define DDRSS1_PHY_178_DATA 0x00000000
+#define DDRSS1_PHY_179_DATA 0x00000000
+#define DDRSS1_PHY_180_DATA 0x00000000
+#define DDRSS1_PHY_181_DATA 0x00000000
+#define DDRSS1_PHY_182_DATA 0x00000000
+#define DDRSS1_PHY_183_DATA 0x00000000
+#define DDRSS1_PHY_184_DATA 0x00000000
+#define DDRSS1_PHY_185_DATA 0x00000000
+#define DDRSS1_PHY_186_DATA 0x00000000
+#define DDRSS1_PHY_187_DATA 0x00000000
+#define DDRSS1_PHY_188_DATA 0x00000000
+#define DDRSS1_PHY_189_DATA 0x00000000
+#define DDRSS1_PHY_190_DATA 0x00000000
+#define DDRSS1_PHY_191_DATA 0x00000000
+#define DDRSS1_PHY_192_DATA 0x00000000
+#define DDRSS1_PHY_193_DATA 0x00000000
+#define DDRSS1_PHY_194_DATA 0x00000000
+#define DDRSS1_PHY_195_DATA 0x00000000
+#define DDRSS1_PHY_196_DATA 0x00000000
+#define DDRSS1_PHY_197_DATA 0x00000000
+#define DDRSS1_PHY_198_DATA 0x00000000
+#define DDRSS1_PHY_199_DATA 0x00000000
+#define DDRSS1_PHY_200_DATA 0x00000000
+#define DDRSS1_PHY_201_DATA 0x00000000
+#define DDRSS1_PHY_202_DATA 0x00000000
+#define DDRSS1_PHY_203_DATA 0x00000000
+#define DDRSS1_PHY_204_DATA 0x00000000
+#define DDRSS1_PHY_205_DATA 0x00000000
+#define DDRSS1_PHY_206_DATA 0x00000000
+#define DDRSS1_PHY_207_DATA 0x00000000
+#define DDRSS1_PHY_208_DATA 0x00000000
+#define DDRSS1_PHY_209_DATA 0x00000000
+#define DDRSS1_PHY_210_DATA 0x00000000
+#define DDRSS1_PHY_211_DATA 0x00000000
+#define DDRSS1_PHY_212_DATA 0x00000000
+#define DDRSS1_PHY_213_DATA 0x00000000
+#define DDRSS1_PHY_214_DATA 0x00000000
+#define DDRSS1_PHY_215_DATA 0x00000000
+#define DDRSS1_PHY_216_DATA 0x00000000
+#define DDRSS1_PHY_217_DATA 0x00000000
+#define DDRSS1_PHY_218_DATA 0x00000000
+#define DDRSS1_PHY_219_DATA 0x00000000
+#define DDRSS1_PHY_220_DATA 0x00000000
+#define DDRSS1_PHY_221_DATA 0x00000000
+#define DDRSS1_PHY_222_DATA 0x00000000
+#define DDRSS1_PHY_223_DATA 0x00000000
+#define DDRSS1_PHY_224_DATA 0x00000000
+#define DDRSS1_PHY_225_DATA 0x00000000
+#define DDRSS1_PHY_226_DATA 0x00000000
+#define DDRSS1_PHY_227_DATA 0x00000000
+#define DDRSS1_PHY_228_DATA 0x00000000
+#define DDRSS1_PHY_229_DATA 0x00000000
+#define DDRSS1_PHY_230_DATA 0x00000000
+#define DDRSS1_PHY_231_DATA 0x00000000
+#define DDRSS1_PHY_232_DATA 0x00000000
+#define DDRSS1_PHY_233_DATA 0x00000000
+#define DDRSS1_PHY_234_DATA 0x00000000
+#define DDRSS1_PHY_235_DATA 0x00000000
+#define DDRSS1_PHY_236_DATA 0x00000000
+#define DDRSS1_PHY_237_DATA 0x00000000
+#define DDRSS1_PHY_238_DATA 0x00000000
+#define DDRSS1_PHY_239_DATA 0x00000000
+#define DDRSS1_PHY_240_DATA 0x00000000
+#define DDRSS1_PHY_241_DATA 0x00000000
+#define DDRSS1_PHY_242_DATA 0x00000000
+#define DDRSS1_PHY_243_DATA 0x00000000
+#define DDRSS1_PHY_244_DATA 0x00000000
+#define DDRSS1_PHY_245_DATA 0x00000000
+#define DDRSS1_PHY_246_DATA 0x00000000
+#define DDRSS1_PHY_247_DATA 0x00000000
+#define DDRSS1_PHY_248_DATA 0x00000000
+#define DDRSS1_PHY_249_DATA 0x00000000
+#define DDRSS1_PHY_250_DATA 0x00000000
+#define DDRSS1_PHY_251_DATA 0x00000000
+#define DDRSS1_PHY_252_DATA 0x00000000
+#define DDRSS1_PHY_253_DATA 0x00000000
+#define DDRSS1_PHY_254_DATA 0x00000000
+#define DDRSS1_PHY_255_DATA 0x00000000
+#define DDRSS1_PHY_256_DATA 0x000004F0
+#define DDRSS1_PHY_257_DATA 0x00000000
+#define DDRSS1_PHY_258_DATA 0x00030200
+#define DDRSS1_PHY_259_DATA 0x00000000
+#define DDRSS1_PHY_260_DATA 0x00000000
+#define DDRSS1_PHY_261_DATA 0x01030000
+#define DDRSS1_PHY_262_DATA 0x00010000
+#define DDRSS1_PHY_263_DATA 0x01030004
+#define DDRSS1_PHY_264_DATA 0x01000000
+#define DDRSS1_PHY_265_DATA 0x00000000
+#define DDRSS1_PHY_266_DATA 0x00000000
+#define DDRSS1_PHY_267_DATA 0x01000001
+#define DDRSS1_PHY_268_DATA 0x00000200
+#define DDRSS1_PHY_269_DATA 0x000800C0
+#define DDRSS1_PHY_270_DATA 0x060100CC
+#define DDRSS1_PHY_271_DATA 0x00030066
+#define DDRSS1_PHY_272_DATA 0x00000000
+#define DDRSS1_PHY_273_DATA 0x00000301
+#define DDRSS1_PHY_274_DATA 0x0000AAAA
+#define DDRSS1_PHY_275_DATA 0x00005555
+#define DDRSS1_PHY_276_DATA 0x0000B5B5
+#define DDRSS1_PHY_277_DATA 0x00004A4A
+#define DDRSS1_PHY_278_DATA 0x00005656
+#define DDRSS1_PHY_279_DATA 0x0000A9A9
+#define DDRSS1_PHY_280_DATA 0x0000A9A9
+#define DDRSS1_PHY_281_DATA 0x0000B5B5
+#define DDRSS1_PHY_282_DATA 0x00000000
+#define DDRSS1_PHY_283_DATA 0x00000000
+#define DDRSS1_PHY_284_DATA 0x2A000000
+#define DDRSS1_PHY_285_DATA 0x00000808
+#define DDRSS1_PHY_286_DATA 0x0F000000
+#define DDRSS1_PHY_287_DATA 0x00000F08
+#define DDRSS1_PHY_288_DATA 0x10400000
+#define DDRSS1_PHY_289_DATA 0x0C002006
+#define DDRSS1_PHY_290_DATA 0x00000000
+#define DDRSS1_PHY_291_DATA 0x00000000
+#define DDRSS1_PHY_292_DATA 0x55555555
+#define DDRSS1_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_294_DATA 0x55555555
+#define DDRSS1_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_296_DATA 0x00005555
+#define DDRSS1_PHY_297_DATA 0x01000100
+#define DDRSS1_PHY_298_DATA 0x00800180
+#define DDRSS1_PHY_299_DATA 0x00000000
+#define DDRSS1_PHY_300_DATA 0x00000000
+#define DDRSS1_PHY_301_DATA 0x00000000
+#define DDRSS1_PHY_302_DATA 0x00000000
+#define DDRSS1_PHY_303_DATA 0x00000000
+#define DDRSS1_PHY_304_DATA 0x00000000
+#define DDRSS1_PHY_305_DATA 0x00000000
+#define DDRSS1_PHY_306_DATA 0x00000000
+#define DDRSS1_PHY_307_DATA 0x00000000
+#define DDRSS1_PHY_308_DATA 0x00000000
+#define DDRSS1_PHY_309_DATA 0x00000000
+#define DDRSS1_PHY_310_DATA 0x00000000
+#define DDRSS1_PHY_311_DATA 0x00000000
+#define DDRSS1_PHY_312_DATA 0x00000000
+#define DDRSS1_PHY_313_DATA 0x00000000
+#define DDRSS1_PHY_314_DATA 0x00000000
+#define DDRSS1_PHY_315_DATA 0x00000000
+#define DDRSS1_PHY_316_DATA 0x00000000
+#define DDRSS1_PHY_317_DATA 0x00000000
+#define DDRSS1_PHY_318_DATA 0x00000000
+#define DDRSS1_PHY_319_DATA 0x00000000
+#define DDRSS1_PHY_320_DATA 0x00000000
+#define DDRSS1_PHY_321_DATA 0x00000000
+#define DDRSS1_PHY_322_DATA 0x00000104
+#define DDRSS1_PHY_323_DATA 0x00000120
+#define DDRSS1_PHY_324_DATA 0x00000000
+#define DDRSS1_PHY_325_DATA 0x00000000
+#define DDRSS1_PHY_326_DATA 0x00000000
+#define DDRSS1_PHY_327_DATA 0x00000000
+#define DDRSS1_PHY_328_DATA 0x00000000
+#define DDRSS1_PHY_329_DATA 0x00000000
+#define DDRSS1_PHY_330_DATA 0x00000000
+#define DDRSS1_PHY_331_DATA 0x00000001
+#define DDRSS1_PHY_332_DATA 0x07FF0000
+#define DDRSS1_PHY_333_DATA 0x0080081F
+#define DDRSS1_PHY_334_DATA 0x00081020
+#define DDRSS1_PHY_335_DATA 0x04010000
+#define DDRSS1_PHY_336_DATA 0x00000000
+#define DDRSS1_PHY_337_DATA 0x00000000
+#define DDRSS1_PHY_338_DATA 0x00000000
+#define DDRSS1_PHY_339_DATA 0x00000100
+#define DDRSS1_PHY_340_DATA 0x01CC0C01
+#define DDRSS1_PHY_341_DATA 0x1003CC0C
+#define DDRSS1_PHY_342_DATA 0x20000140
+#define DDRSS1_PHY_343_DATA 0x07FF0200
+#define DDRSS1_PHY_344_DATA 0x0000DD01
+#define DDRSS1_PHY_345_DATA 0x10100303
+#define DDRSS1_PHY_346_DATA 0x10101010
+#define DDRSS1_PHY_347_DATA 0x10101010
+#define DDRSS1_PHY_348_DATA 0x00021010
+#define DDRSS1_PHY_349_DATA 0x00100010
+#define DDRSS1_PHY_350_DATA 0x00100010
+#define DDRSS1_PHY_351_DATA 0x00100010
+#define DDRSS1_PHY_352_DATA 0x00100010
+#define DDRSS1_PHY_353_DATA 0x00050010
+#define DDRSS1_PHY_354_DATA 0x51517041
+#define DDRSS1_PHY_355_DATA 0x31C06001
+#define DDRSS1_PHY_356_DATA 0x07AB01AB
+#define DDRSS1_PHY_357_DATA 0x00C0C001
+#define DDRSS1_PHY_358_DATA 0x0E0D0101
+#define DDRSS1_PHY_359_DATA 0x10001000
+#define DDRSS1_PHY_360_DATA 0x0C083E42
+#define DDRSS1_PHY_361_DATA 0x0F0C3701
+#define DDRSS1_PHY_362_DATA 0x01000140
+#define DDRSS1_PHY_363_DATA 0x0C000420
+#define DDRSS1_PHY_364_DATA 0x00000198
+#define DDRSS1_PHY_365_DATA 0x0A0000D0
+#define DDRSS1_PHY_366_DATA 0x00030200
+#define DDRSS1_PHY_367_DATA 0x02800000
+#define DDRSS1_PHY_368_DATA 0x80800000
+#define DDRSS1_PHY_369_DATA 0x000E2010
+#define DDRSS1_PHY_370_DATA 0x76543210
+#define DDRSS1_PHY_371_DATA 0x00000008
+#define DDRSS1_PHY_372_DATA 0x02800280
+#define DDRSS1_PHY_373_DATA 0x02800280
+#define DDRSS1_PHY_374_DATA 0x02800280
+#define DDRSS1_PHY_375_DATA 0x02800280
+#define DDRSS1_PHY_376_DATA 0x00000280
+#define DDRSS1_PHY_377_DATA 0x0000A000
+#define DDRSS1_PHY_378_DATA 0x00A000A0
+#define DDRSS1_PHY_379_DATA 0x00A000A0
+#define DDRSS1_PHY_380_DATA 0x00A000A0
+#define DDRSS1_PHY_381_DATA 0x00A000A0
+#define DDRSS1_PHY_382_DATA 0x00A000A0
+#define DDRSS1_PHY_383_DATA 0x00A000A0
+#define DDRSS1_PHY_384_DATA 0x00A000A0
+#define DDRSS1_PHY_385_DATA 0x00A000A0
+#define DDRSS1_PHY_386_DATA 0x01C200A0
+#define DDRSS1_PHY_387_DATA 0x01A00005
+#define DDRSS1_PHY_388_DATA 0x00000000
+#define DDRSS1_PHY_389_DATA 0x00000000
+#define DDRSS1_PHY_390_DATA 0x00080200
+#define DDRSS1_PHY_391_DATA 0x00000000
+#define DDRSS1_PHY_392_DATA 0x20202000
+#define DDRSS1_PHY_393_DATA 0x20202020
+#define DDRSS1_PHY_394_DATA 0xF0F02020
+#define DDRSS1_PHY_395_DATA 0x00000000
+#define DDRSS1_PHY_396_DATA 0x00000000
+#define DDRSS1_PHY_397_DATA 0x00000000
+#define DDRSS1_PHY_398_DATA 0x00000000
+#define DDRSS1_PHY_399_DATA 0x00000000
+#define DDRSS1_PHY_400_DATA 0x00000000
+#define DDRSS1_PHY_401_DATA 0x00000000
+#define DDRSS1_PHY_402_DATA 0x00000000
+#define DDRSS1_PHY_403_DATA 0x00000000
+#define DDRSS1_PHY_404_DATA 0x00000000
+#define DDRSS1_PHY_405_DATA 0x00000000
+#define DDRSS1_PHY_406_DATA 0x00000000
+#define DDRSS1_PHY_407_DATA 0x00000000
+#define DDRSS1_PHY_408_DATA 0x00000000
+#define DDRSS1_PHY_409_DATA 0x00000000
+#define DDRSS1_PHY_410_DATA 0x00000000
+#define DDRSS1_PHY_411_DATA 0x00000000
+#define DDRSS1_PHY_412_DATA 0x00000000
+#define DDRSS1_PHY_413_DATA 0x00000000
+#define DDRSS1_PHY_414_DATA 0x00000000
+#define DDRSS1_PHY_415_DATA 0x00000000
+#define DDRSS1_PHY_416_DATA 0x00000000
+#define DDRSS1_PHY_417_DATA 0x00000000
+#define DDRSS1_PHY_418_DATA 0x00000000
+#define DDRSS1_PHY_419_DATA 0x00000000
+#define DDRSS1_PHY_420_DATA 0x00000000
+#define DDRSS1_PHY_421_DATA 0x00000000
+#define DDRSS1_PHY_422_DATA 0x00000000
+#define DDRSS1_PHY_423_DATA 0x00000000
+#define DDRSS1_PHY_424_DATA 0x00000000
+#define DDRSS1_PHY_425_DATA 0x00000000
+#define DDRSS1_PHY_426_DATA 0x00000000
+#define DDRSS1_PHY_427_DATA 0x00000000
+#define DDRSS1_PHY_428_DATA 0x00000000
+#define DDRSS1_PHY_429_DATA 0x00000000
+#define DDRSS1_PHY_430_DATA 0x00000000
+#define DDRSS1_PHY_431_DATA 0x00000000
+#define DDRSS1_PHY_432_DATA 0x00000000
+#define DDRSS1_PHY_433_DATA 0x00000000
+#define DDRSS1_PHY_434_DATA 0x00000000
+#define DDRSS1_PHY_435_DATA 0x00000000
+#define DDRSS1_PHY_436_DATA 0x00000000
+#define DDRSS1_PHY_437_DATA 0x00000000
+#define DDRSS1_PHY_438_DATA 0x00000000
+#define DDRSS1_PHY_439_DATA 0x00000000
+#define DDRSS1_PHY_440_DATA 0x00000000
+#define DDRSS1_PHY_441_DATA 0x00000000
+#define DDRSS1_PHY_442_DATA 0x00000000
+#define DDRSS1_PHY_443_DATA 0x00000000
+#define DDRSS1_PHY_444_DATA 0x00000000
+#define DDRSS1_PHY_445_DATA 0x00000000
+#define DDRSS1_PHY_446_DATA 0x00000000
+#define DDRSS1_PHY_447_DATA 0x00000000
+#define DDRSS1_PHY_448_DATA 0x00000000
+#define DDRSS1_PHY_449_DATA 0x00000000
+#define DDRSS1_PHY_450_DATA 0x00000000
+#define DDRSS1_PHY_451_DATA 0x00000000
+#define DDRSS1_PHY_452_DATA 0x00000000
+#define DDRSS1_PHY_453_DATA 0x00000000
+#define DDRSS1_PHY_454_DATA 0x00000000
+#define DDRSS1_PHY_455_DATA 0x00000000
+#define DDRSS1_PHY_456_DATA 0x00000000
+#define DDRSS1_PHY_457_DATA 0x00000000
+#define DDRSS1_PHY_458_DATA 0x00000000
+#define DDRSS1_PHY_459_DATA 0x00000000
+#define DDRSS1_PHY_460_DATA 0x00000000
+#define DDRSS1_PHY_461_DATA 0x00000000
+#define DDRSS1_PHY_462_DATA 0x00000000
+#define DDRSS1_PHY_463_DATA 0x00000000
+#define DDRSS1_PHY_464_DATA 0x00000000
+#define DDRSS1_PHY_465_DATA 0x00000000
+#define DDRSS1_PHY_466_DATA 0x00000000
+#define DDRSS1_PHY_467_DATA 0x00000000
+#define DDRSS1_PHY_468_DATA 0x00000000
+#define DDRSS1_PHY_469_DATA 0x00000000
+#define DDRSS1_PHY_470_DATA 0x00000000
+#define DDRSS1_PHY_471_DATA 0x00000000
+#define DDRSS1_PHY_472_DATA 0x00000000
+#define DDRSS1_PHY_473_DATA 0x00000000
+#define DDRSS1_PHY_474_DATA 0x00000000
+#define DDRSS1_PHY_475_DATA 0x00000000
+#define DDRSS1_PHY_476_DATA 0x00000000
+#define DDRSS1_PHY_477_DATA 0x00000000
+#define DDRSS1_PHY_478_DATA 0x00000000
+#define DDRSS1_PHY_479_DATA 0x00000000
+#define DDRSS1_PHY_480_DATA 0x00000000
+#define DDRSS1_PHY_481_DATA 0x00000000
+#define DDRSS1_PHY_482_DATA 0x00000000
+#define DDRSS1_PHY_483_DATA 0x00000000
+#define DDRSS1_PHY_484_DATA 0x00000000
+#define DDRSS1_PHY_485_DATA 0x00000000
+#define DDRSS1_PHY_486_DATA 0x00000000
+#define DDRSS1_PHY_487_DATA 0x00000000
+#define DDRSS1_PHY_488_DATA 0x00000000
+#define DDRSS1_PHY_489_DATA 0x00000000
+#define DDRSS1_PHY_490_DATA 0x00000000
+#define DDRSS1_PHY_491_DATA 0x00000000
+#define DDRSS1_PHY_492_DATA 0x00000000
+#define DDRSS1_PHY_493_DATA 0x00000000
+#define DDRSS1_PHY_494_DATA 0x00000000
+#define DDRSS1_PHY_495_DATA 0x00000000
+#define DDRSS1_PHY_496_DATA 0x00000000
+#define DDRSS1_PHY_497_DATA 0x00000000
+#define DDRSS1_PHY_498_DATA 0x00000000
+#define DDRSS1_PHY_499_DATA 0x00000000
+#define DDRSS1_PHY_500_DATA 0x00000000
+#define DDRSS1_PHY_501_DATA 0x00000000
+#define DDRSS1_PHY_502_DATA 0x00000000
+#define DDRSS1_PHY_503_DATA 0x00000000
+#define DDRSS1_PHY_504_DATA 0x00000000
+#define DDRSS1_PHY_505_DATA 0x00000000
+#define DDRSS1_PHY_506_DATA 0x00000000
+#define DDRSS1_PHY_507_DATA 0x00000000
+#define DDRSS1_PHY_508_DATA 0x00000000
+#define DDRSS1_PHY_509_DATA 0x00000000
+#define DDRSS1_PHY_510_DATA 0x00000000
+#define DDRSS1_PHY_511_DATA 0x00000000
+#define DDRSS1_PHY_512_DATA 0x000004F0
+#define DDRSS1_PHY_513_DATA 0x00000000
+#define DDRSS1_PHY_514_DATA 0x00030200
+#define DDRSS1_PHY_515_DATA 0x00000000
+#define DDRSS1_PHY_516_DATA 0x00000000
+#define DDRSS1_PHY_517_DATA 0x01030000
+#define DDRSS1_PHY_518_DATA 0x00010000
+#define DDRSS1_PHY_519_DATA 0x01030004
+#define DDRSS1_PHY_520_DATA 0x01000000
+#define DDRSS1_PHY_521_DATA 0x00000000
+#define DDRSS1_PHY_522_DATA 0x00000000
+#define DDRSS1_PHY_523_DATA 0x01000001
+#define DDRSS1_PHY_524_DATA 0x00000200
+#define DDRSS1_PHY_525_DATA 0x000800C0
+#define DDRSS1_PHY_526_DATA 0x060100CC
+#define DDRSS1_PHY_527_DATA 0x00030066
+#define DDRSS1_PHY_528_DATA 0x00000000
+#define DDRSS1_PHY_529_DATA 0x00000301
+#define DDRSS1_PHY_530_DATA 0x0000AAAA
+#define DDRSS1_PHY_531_DATA 0x00005555
+#define DDRSS1_PHY_532_DATA 0x0000B5B5
+#define DDRSS1_PHY_533_DATA 0x00004A4A
+#define DDRSS1_PHY_534_DATA 0x00005656
+#define DDRSS1_PHY_535_DATA 0x0000A9A9
+#define DDRSS1_PHY_536_DATA 0x0000A9A9
+#define DDRSS1_PHY_537_DATA 0x0000B5B5
+#define DDRSS1_PHY_538_DATA 0x00000000
+#define DDRSS1_PHY_539_DATA 0x00000000
+#define DDRSS1_PHY_540_DATA 0x2A000000
+#define DDRSS1_PHY_541_DATA 0x00000808
+#define DDRSS1_PHY_542_DATA 0x0F000000
+#define DDRSS1_PHY_543_DATA 0x00000F08
+#define DDRSS1_PHY_544_DATA 0x10400000
+#define DDRSS1_PHY_545_DATA 0x0C002006
+#define DDRSS1_PHY_546_DATA 0x00000000
+#define DDRSS1_PHY_547_DATA 0x00000000
+#define DDRSS1_PHY_548_DATA 0x55555555
+#define DDRSS1_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_550_DATA 0x55555555
+#define DDRSS1_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_552_DATA 0x00005555
+#define DDRSS1_PHY_553_DATA 0x01000100
+#define DDRSS1_PHY_554_DATA 0x00800180
+#define DDRSS1_PHY_555_DATA 0x00000001
+#define DDRSS1_PHY_556_DATA 0x00000000
+#define DDRSS1_PHY_557_DATA 0x00000000
+#define DDRSS1_PHY_558_DATA 0x00000000
+#define DDRSS1_PHY_559_DATA 0x00000000
+#define DDRSS1_PHY_560_DATA 0x00000000
+#define DDRSS1_PHY_561_DATA 0x00000000
+#define DDRSS1_PHY_562_DATA 0x00000000
+#define DDRSS1_PHY_563_DATA 0x00000000
+#define DDRSS1_PHY_564_DATA 0x00000000
+#define DDRSS1_PHY_565_DATA 0x00000000
+#define DDRSS1_PHY_566_DATA 0x00000000
+#define DDRSS1_PHY_567_DATA 0x00000000
+#define DDRSS1_PHY_568_DATA 0x00000000
+#define DDRSS1_PHY_569_DATA 0x00000000
+#define DDRSS1_PHY_570_DATA 0x00000000
+#define DDRSS1_PHY_571_DATA 0x00000000
+#define DDRSS1_PHY_572_DATA 0x00000000
+#define DDRSS1_PHY_573_DATA 0x00000000
+#define DDRSS1_PHY_574_DATA 0x00000000
+#define DDRSS1_PHY_575_DATA 0x00000000
+#define DDRSS1_PHY_576_DATA 0x00000000
+#define DDRSS1_PHY_577_DATA 0x00000000
+#define DDRSS1_PHY_578_DATA 0x00000104
+#define DDRSS1_PHY_579_DATA 0x00000120
+#define DDRSS1_PHY_580_DATA 0x00000000
+#define DDRSS1_PHY_581_DATA 0x00000000
+#define DDRSS1_PHY_582_DATA 0x00000000
+#define DDRSS1_PHY_583_DATA 0x00000000
+#define DDRSS1_PHY_584_DATA 0x00000000
+#define DDRSS1_PHY_585_DATA 0x00000000
+#define DDRSS1_PHY_586_DATA 0x00000000
+#define DDRSS1_PHY_587_DATA 0x00000001
+#define DDRSS1_PHY_588_DATA 0x07FF0000
+#define DDRSS1_PHY_589_DATA 0x0080081F
+#define DDRSS1_PHY_590_DATA 0x00081020
+#define DDRSS1_PHY_591_DATA 0x04010000
+#define DDRSS1_PHY_592_DATA 0x00000000
+#define DDRSS1_PHY_593_DATA 0x00000000
+#define DDRSS1_PHY_594_DATA 0x00000000
+#define DDRSS1_PHY_595_DATA 0x00000100
+#define DDRSS1_PHY_596_DATA 0x01CC0C01
+#define DDRSS1_PHY_597_DATA 0x1003CC0C
+#define DDRSS1_PHY_598_DATA 0x20000140
+#define DDRSS1_PHY_599_DATA 0x07FF0200
+#define DDRSS1_PHY_600_DATA 0x0000DD01
+#define DDRSS1_PHY_601_DATA 0x10100303
+#define DDRSS1_PHY_602_DATA 0x10101010
+#define DDRSS1_PHY_603_DATA 0x10101010
+#define DDRSS1_PHY_604_DATA 0x00021010
+#define DDRSS1_PHY_605_DATA 0x00100010
+#define DDRSS1_PHY_606_DATA 0x00100010
+#define DDRSS1_PHY_607_DATA 0x00100010
+#define DDRSS1_PHY_608_DATA 0x00100010
+#define DDRSS1_PHY_609_DATA 0x00050010
+#define DDRSS1_PHY_610_DATA 0x51517041
+#define DDRSS1_PHY_611_DATA 0x31C06001
+#define DDRSS1_PHY_612_DATA 0x07AB01AB
+#define DDRSS1_PHY_613_DATA 0x00C0C001
+#define DDRSS1_PHY_614_DATA 0x0E0D0101
+#define DDRSS1_PHY_615_DATA 0x10001000
+#define DDRSS1_PHY_616_DATA 0x0C083E42
+#define DDRSS1_PHY_617_DATA 0x0F0C3701
+#define DDRSS1_PHY_618_DATA 0x01000140
+#define DDRSS1_PHY_619_DATA 0x0C000420
+#define DDRSS1_PHY_620_DATA 0x00000198
+#define DDRSS1_PHY_621_DATA 0x0A0000D0
+#define DDRSS1_PHY_622_DATA 0x00030200
+#define DDRSS1_PHY_623_DATA 0x02800000
+#define DDRSS1_PHY_624_DATA 0x80800000
+#define DDRSS1_PHY_625_DATA 0x000E2010
+#define DDRSS1_PHY_626_DATA 0x76543210
+#define DDRSS1_PHY_627_DATA 0x00000008
+#define DDRSS1_PHY_628_DATA 0x02800280
+#define DDRSS1_PHY_629_DATA 0x02800280
+#define DDRSS1_PHY_630_DATA 0x02800280
+#define DDRSS1_PHY_631_DATA 0x02800280
+#define DDRSS1_PHY_632_DATA 0x00000280
+#define DDRSS1_PHY_633_DATA 0x0000A000
+#define DDRSS1_PHY_634_DATA 0x00A000A0
+#define DDRSS1_PHY_635_DATA 0x00A000A0
+#define DDRSS1_PHY_636_DATA 0x00A000A0
+#define DDRSS1_PHY_637_DATA 0x00A000A0
+#define DDRSS1_PHY_638_DATA 0x00A000A0
+#define DDRSS1_PHY_639_DATA 0x00A000A0
+#define DDRSS1_PHY_640_DATA 0x00A000A0
+#define DDRSS1_PHY_641_DATA 0x00A000A0
+#define DDRSS1_PHY_642_DATA 0x01C200A0
+#define DDRSS1_PHY_643_DATA 0x01A00005
+#define DDRSS1_PHY_644_DATA 0x00000000
+#define DDRSS1_PHY_645_DATA 0x00000000
+#define DDRSS1_PHY_646_DATA 0x00080200
+#define DDRSS1_PHY_647_DATA 0x00000000
+#define DDRSS1_PHY_648_DATA 0x20202000
+#define DDRSS1_PHY_649_DATA 0x20202020
+#define DDRSS1_PHY_650_DATA 0xF0F02020
+#define DDRSS1_PHY_651_DATA 0x00000000
+#define DDRSS1_PHY_652_DATA 0x00000000
+#define DDRSS1_PHY_653_DATA 0x00000000
+#define DDRSS1_PHY_654_DATA 0x00000000
+#define DDRSS1_PHY_655_DATA 0x00000000
+#define DDRSS1_PHY_656_DATA 0x00000000
+#define DDRSS1_PHY_657_DATA 0x00000000
+#define DDRSS1_PHY_658_DATA 0x00000000
+#define DDRSS1_PHY_659_DATA 0x00000000
+#define DDRSS1_PHY_660_DATA 0x00000000
+#define DDRSS1_PHY_661_DATA 0x00000000
+#define DDRSS1_PHY_662_DATA 0x00000000
+#define DDRSS1_PHY_663_DATA 0x00000000
+#define DDRSS1_PHY_664_DATA 0x00000000
+#define DDRSS1_PHY_665_DATA 0x00000000
+#define DDRSS1_PHY_666_DATA 0x00000000
+#define DDRSS1_PHY_667_DATA 0x00000000
+#define DDRSS1_PHY_668_DATA 0x00000000
+#define DDRSS1_PHY_669_DATA 0x00000000
+#define DDRSS1_PHY_670_DATA 0x00000000
+#define DDRSS1_PHY_671_DATA 0x00000000
+#define DDRSS1_PHY_672_DATA 0x00000000
+#define DDRSS1_PHY_673_DATA 0x00000000
+#define DDRSS1_PHY_674_DATA 0x00000000
+#define DDRSS1_PHY_675_DATA 0x00000000
+#define DDRSS1_PHY_676_DATA 0x00000000
+#define DDRSS1_PHY_677_DATA 0x00000000
+#define DDRSS1_PHY_678_DATA 0x00000000
+#define DDRSS1_PHY_679_DATA 0x00000000
+#define DDRSS1_PHY_680_DATA 0x00000000
+#define DDRSS1_PHY_681_DATA 0x00000000
+#define DDRSS1_PHY_682_DATA 0x00000000
+#define DDRSS1_PHY_683_DATA 0x00000000
+#define DDRSS1_PHY_684_DATA 0x00000000
+#define DDRSS1_PHY_685_DATA 0x00000000
+#define DDRSS1_PHY_686_DATA 0x00000000
+#define DDRSS1_PHY_687_DATA 0x00000000
+#define DDRSS1_PHY_688_DATA 0x00000000
+#define DDRSS1_PHY_689_DATA 0x00000000
+#define DDRSS1_PHY_690_DATA 0x00000000
+#define DDRSS1_PHY_691_DATA 0x00000000
+#define DDRSS1_PHY_692_DATA 0x00000000
+#define DDRSS1_PHY_693_DATA 0x00000000
+#define DDRSS1_PHY_694_DATA 0x00000000
+#define DDRSS1_PHY_695_DATA 0x00000000
+#define DDRSS1_PHY_696_DATA 0x00000000
+#define DDRSS1_PHY_697_DATA 0x00000000
+#define DDRSS1_PHY_698_DATA 0x00000000
+#define DDRSS1_PHY_699_DATA 0x00000000
+#define DDRSS1_PHY_700_DATA 0x00000000
+#define DDRSS1_PHY_701_DATA 0x00000000
+#define DDRSS1_PHY_702_DATA 0x00000000
+#define DDRSS1_PHY_703_DATA 0x00000000
+#define DDRSS1_PHY_704_DATA 0x00000000
+#define DDRSS1_PHY_705_DATA 0x00000000
+#define DDRSS1_PHY_706_DATA 0x00000000
+#define DDRSS1_PHY_707_DATA 0x00000000
+#define DDRSS1_PHY_708_DATA 0x00000000
+#define DDRSS1_PHY_709_DATA 0x00000000
+#define DDRSS1_PHY_710_DATA 0x00000000
+#define DDRSS1_PHY_711_DATA 0x00000000
+#define DDRSS1_PHY_712_DATA 0x00000000
+#define DDRSS1_PHY_713_DATA 0x00000000
+#define DDRSS1_PHY_714_DATA 0x00000000
+#define DDRSS1_PHY_715_DATA 0x00000000
+#define DDRSS1_PHY_716_DATA 0x00000000
+#define DDRSS1_PHY_717_DATA 0x00000000
+#define DDRSS1_PHY_718_DATA 0x00000000
+#define DDRSS1_PHY_719_DATA 0x00000000
+#define DDRSS1_PHY_720_DATA 0x00000000
+#define DDRSS1_PHY_721_DATA 0x00000000
+#define DDRSS1_PHY_722_DATA 0x00000000
+#define DDRSS1_PHY_723_DATA 0x00000000
+#define DDRSS1_PHY_724_DATA 0x00000000
+#define DDRSS1_PHY_725_DATA 0x00000000
+#define DDRSS1_PHY_726_DATA 0x00000000
+#define DDRSS1_PHY_727_DATA 0x00000000
+#define DDRSS1_PHY_728_DATA 0x00000000
+#define DDRSS1_PHY_729_DATA 0x00000000
+#define DDRSS1_PHY_730_DATA 0x00000000
+#define DDRSS1_PHY_731_DATA 0x00000000
+#define DDRSS1_PHY_732_DATA 0x00000000
+#define DDRSS1_PHY_733_DATA 0x00000000
+#define DDRSS1_PHY_734_DATA 0x00000000
+#define DDRSS1_PHY_735_DATA 0x00000000
+#define DDRSS1_PHY_736_DATA 0x00000000
+#define DDRSS1_PHY_737_DATA 0x00000000
+#define DDRSS1_PHY_738_DATA 0x00000000
+#define DDRSS1_PHY_739_DATA 0x00000000
+#define DDRSS1_PHY_740_DATA 0x00000000
+#define DDRSS1_PHY_741_DATA 0x00000000
+#define DDRSS1_PHY_742_DATA 0x00000000
+#define DDRSS1_PHY_743_DATA 0x00000000
+#define DDRSS1_PHY_744_DATA 0x00000000
+#define DDRSS1_PHY_745_DATA 0x00000000
+#define DDRSS1_PHY_746_DATA 0x00000000
+#define DDRSS1_PHY_747_DATA 0x00000000
+#define DDRSS1_PHY_748_DATA 0x00000000
+#define DDRSS1_PHY_749_DATA 0x00000000
+#define DDRSS1_PHY_750_DATA 0x00000000
+#define DDRSS1_PHY_751_DATA 0x00000000
+#define DDRSS1_PHY_752_DATA 0x00000000
+#define DDRSS1_PHY_753_DATA 0x00000000
+#define DDRSS1_PHY_754_DATA 0x00000000
+#define DDRSS1_PHY_755_DATA 0x00000000
+#define DDRSS1_PHY_756_DATA 0x00000000
+#define DDRSS1_PHY_757_DATA 0x00000000
+#define DDRSS1_PHY_758_DATA 0x00000000
+#define DDRSS1_PHY_759_DATA 0x00000000
+#define DDRSS1_PHY_760_DATA 0x00000000
+#define DDRSS1_PHY_761_DATA 0x00000000
+#define DDRSS1_PHY_762_DATA 0x00000000
+#define DDRSS1_PHY_763_DATA 0x00000000
+#define DDRSS1_PHY_764_DATA 0x00000000
+#define DDRSS1_PHY_765_DATA 0x00000000
+#define DDRSS1_PHY_766_DATA 0x00000000
+#define DDRSS1_PHY_767_DATA 0x00000000
+#define DDRSS1_PHY_768_DATA 0x000004F0
+#define DDRSS1_PHY_769_DATA 0x00000000
+#define DDRSS1_PHY_770_DATA 0x00030200
+#define DDRSS1_PHY_771_DATA 0x00000000
+#define DDRSS1_PHY_772_DATA 0x00000000
+#define DDRSS1_PHY_773_DATA 0x01030000
+#define DDRSS1_PHY_774_DATA 0x00010000
+#define DDRSS1_PHY_775_DATA 0x01030004
+#define DDRSS1_PHY_776_DATA 0x01000000
+#define DDRSS1_PHY_777_DATA 0x00000000
+#define DDRSS1_PHY_778_DATA 0x00000000
+#define DDRSS1_PHY_779_DATA 0x01000001
+#define DDRSS1_PHY_780_DATA 0x00000200
+#define DDRSS1_PHY_781_DATA 0x000800C0
+#define DDRSS1_PHY_782_DATA 0x060100CC
+#define DDRSS1_PHY_783_DATA 0x00030066
+#define DDRSS1_PHY_784_DATA 0x00000000
+#define DDRSS1_PHY_785_DATA 0x00000301
+#define DDRSS1_PHY_786_DATA 0x0000AAAA
+#define DDRSS1_PHY_787_DATA 0x00005555
+#define DDRSS1_PHY_788_DATA 0x0000B5B5
+#define DDRSS1_PHY_789_DATA 0x00004A4A
+#define DDRSS1_PHY_790_DATA 0x00005656
+#define DDRSS1_PHY_791_DATA 0x0000A9A9
+#define DDRSS1_PHY_792_DATA 0x0000A9A9
+#define DDRSS1_PHY_793_DATA 0x0000B5B5
+#define DDRSS1_PHY_794_DATA 0x00000000
+#define DDRSS1_PHY_795_DATA 0x00000000
+#define DDRSS1_PHY_796_DATA 0x2A000000
+#define DDRSS1_PHY_797_DATA 0x00000808
+#define DDRSS1_PHY_798_DATA 0x0F000000
+#define DDRSS1_PHY_799_DATA 0x00000F08
+#define DDRSS1_PHY_800_DATA 0x10400000
+#define DDRSS1_PHY_801_DATA 0x0C002006
+#define DDRSS1_PHY_802_DATA 0x00000000
+#define DDRSS1_PHY_803_DATA 0x00000000
+#define DDRSS1_PHY_804_DATA 0x55555555
+#define DDRSS1_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_806_DATA 0x55555555
+#define DDRSS1_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_808_DATA 0x00005555
+#define DDRSS1_PHY_809_DATA 0x01000100
+#define DDRSS1_PHY_810_DATA 0x00800180
+#define DDRSS1_PHY_811_DATA 0x00000000
+#define DDRSS1_PHY_812_DATA 0x00000000
+#define DDRSS1_PHY_813_DATA 0x00000000
+#define DDRSS1_PHY_814_DATA 0x00000000
+#define DDRSS1_PHY_815_DATA 0x00000000
+#define DDRSS1_PHY_816_DATA 0x00000000
+#define DDRSS1_PHY_817_DATA 0x00000000
+#define DDRSS1_PHY_818_DATA 0x00000000
+#define DDRSS1_PHY_819_DATA 0x00000000
+#define DDRSS1_PHY_820_DATA 0x00000000
+#define DDRSS1_PHY_821_DATA 0x00000000
+#define DDRSS1_PHY_822_DATA 0x00000000
+#define DDRSS1_PHY_823_DATA 0x00000000
+#define DDRSS1_PHY_824_DATA 0x00000000
+#define DDRSS1_PHY_825_DATA 0x00000000
+#define DDRSS1_PHY_826_DATA 0x00000000
+#define DDRSS1_PHY_827_DATA 0x00000000
+#define DDRSS1_PHY_828_DATA 0x00000000
+#define DDRSS1_PHY_829_DATA 0x00000000
+#define DDRSS1_PHY_830_DATA 0x00000000
+#define DDRSS1_PHY_831_DATA 0x00000000
+#define DDRSS1_PHY_832_DATA 0x00000000
+#define DDRSS1_PHY_833_DATA 0x00000000
+#define DDRSS1_PHY_834_DATA 0x00000104
+#define DDRSS1_PHY_835_DATA 0x00000120
+#define DDRSS1_PHY_836_DATA 0x00000000
+#define DDRSS1_PHY_837_DATA 0x00000000
+#define DDRSS1_PHY_838_DATA 0x00000000
+#define DDRSS1_PHY_839_DATA 0x00000000
+#define DDRSS1_PHY_840_DATA 0x00000000
+#define DDRSS1_PHY_841_DATA 0x00000000
+#define DDRSS1_PHY_842_DATA 0x00000000
+#define DDRSS1_PHY_843_DATA 0x00000001
+#define DDRSS1_PHY_844_DATA 0x07FF0000
+#define DDRSS1_PHY_845_DATA 0x0080081F
+#define DDRSS1_PHY_846_DATA 0x00081020
+#define DDRSS1_PHY_847_DATA 0x04010000
+#define DDRSS1_PHY_848_DATA 0x00000000
+#define DDRSS1_PHY_849_DATA 0x00000000
+#define DDRSS1_PHY_850_DATA 0x00000000
+#define DDRSS1_PHY_851_DATA 0x00000100
+#define DDRSS1_PHY_852_DATA 0x01CC0C01
+#define DDRSS1_PHY_853_DATA 0x1003CC0C
+#define DDRSS1_PHY_854_DATA 0x20000140
+#define DDRSS1_PHY_855_DATA 0x07FF0200
+#define DDRSS1_PHY_856_DATA 0x0000DD01
+#define DDRSS1_PHY_857_DATA 0x10100303
+#define DDRSS1_PHY_858_DATA 0x10101010
+#define DDRSS1_PHY_859_DATA 0x10101010
+#define DDRSS1_PHY_860_DATA 0x00021010
+#define DDRSS1_PHY_861_DATA 0x00100010
+#define DDRSS1_PHY_862_DATA 0x00100010
+#define DDRSS1_PHY_863_DATA 0x00100010
+#define DDRSS1_PHY_864_DATA 0x00100010
+#define DDRSS1_PHY_865_DATA 0x00050010
+#define DDRSS1_PHY_866_DATA 0x51517041
+#define DDRSS1_PHY_867_DATA 0x31C06001
+#define DDRSS1_PHY_868_DATA 0x07AB01AB
+#define DDRSS1_PHY_869_DATA 0x00C0C001
+#define DDRSS1_PHY_870_DATA 0x0E0D0101
+#define DDRSS1_PHY_871_DATA 0x10001000
+#define DDRSS1_PHY_872_DATA 0x0C083E42
+#define DDRSS1_PHY_873_DATA 0x0F0C3701
+#define DDRSS1_PHY_874_DATA 0x01000140
+#define DDRSS1_PHY_875_DATA 0x0C000420
+#define DDRSS1_PHY_876_DATA 0x00000198
+#define DDRSS1_PHY_877_DATA 0x0A0000D0
+#define DDRSS1_PHY_878_DATA 0x00030200
+#define DDRSS1_PHY_879_DATA 0x02800000
+#define DDRSS1_PHY_880_DATA 0x80800000
+#define DDRSS1_PHY_881_DATA 0x000E2010
+#define DDRSS1_PHY_882_DATA 0x76543210
+#define DDRSS1_PHY_883_DATA 0x00000008
+#define DDRSS1_PHY_884_DATA 0x02800280
+#define DDRSS1_PHY_885_DATA 0x02800280
+#define DDRSS1_PHY_886_DATA 0x02800280
+#define DDRSS1_PHY_887_DATA 0x02800280
+#define DDRSS1_PHY_888_DATA 0x00000280
+#define DDRSS1_PHY_889_DATA 0x0000A000
+#define DDRSS1_PHY_890_DATA 0x00A000A0
+#define DDRSS1_PHY_891_DATA 0x00A000A0
+#define DDRSS1_PHY_892_DATA 0x00A000A0
+#define DDRSS1_PHY_893_DATA 0x00A000A0
+#define DDRSS1_PHY_894_DATA 0x00A000A0
+#define DDRSS1_PHY_895_DATA 0x00A000A0
+#define DDRSS1_PHY_896_DATA 0x00A000A0
+#define DDRSS1_PHY_897_DATA 0x00A000A0
+#define DDRSS1_PHY_898_DATA 0x01C200A0
+#define DDRSS1_PHY_899_DATA 0x01A00005
+#define DDRSS1_PHY_900_DATA 0x00000000
+#define DDRSS1_PHY_901_DATA 0x00000000
+#define DDRSS1_PHY_902_DATA 0x00080200
+#define DDRSS1_PHY_903_DATA 0x00000000
+#define DDRSS1_PHY_904_DATA 0x20202000
+#define DDRSS1_PHY_905_DATA 0x20202020
+#define DDRSS1_PHY_906_DATA 0xF0F02020
+#define DDRSS1_PHY_907_DATA 0x00000000
+#define DDRSS1_PHY_908_DATA 0x00000000
+#define DDRSS1_PHY_909_DATA 0x00000000
+#define DDRSS1_PHY_910_DATA 0x00000000
+#define DDRSS1_PHY_911_DATA 0x00000000
+#define DDRSS1_PHY_912_DATA 0x00000000
+#define DDRSS1_PHY_913_DATA 0x00000000
+#define DDRSS1_PHY_914_DATA 0x00000000
+#define DDRSS1_PHY_915_DATA 0x00000000
+#define DDRSS1_PHY_916_DATA 0x00000000
+#define DDRSS1_PHY_917_DATA 0x00000000
+#define DDRSS1_PHY_918_DATA 0x00000000
+#define DDRSS1_PHY_919_DATA 0x00000000
+#define DDRSS1_PHY_920_DATA 0x00000000
+#define DDRSS1_PHY_921_DATA 0x00000000
+#define DDRSS1_PHY_922_DATA 0x00000000
+#define DDRSS1_PHY_923_DATA 0x00000000
+#define DDRSS1_PHY_924_DATA 0x00000000
+#define DDRSS1_PHY_925_DATA 0x00000000
+#define DDRSS1_PHY_926_DATA 0x00000000
+#define DDRSS1_PHY_927_DATA 0x00000000
+#define DDRSS1_PHY_928_DATA 0x00000000
+#define DDRSS1_PHY_929_DATA 0x00000000
+#define DDRSS1_PHY_930_DATA 0x00000000
+#define DDRSS1_PHY_931_DATA 0x00000000
+#define DDRSS1_PHY_932_DATA 0x00000000
+#define DDRSS1_PHY_933_DATA 0x00000000
+#define DDRSS1_PHY_934_DATA 0x00000000
+#define DDRSS1_PHY_935_DATA 0x00000000
+#define DDRSS1_PHY_936_DATA 0x00000000
+#define DDRSS1_PHY_937_DATA 0x00000000
+#define DDRSS1_PHY_938_DATA 0x00000000
+#define DDRSS1_PHY_939_DATA 0x00000000
+#define DDRSS1_PHY_940_DATA 0x00000000
+#define DDRSS1_PHY_941_DATA 0x00000000
+#define DDRSS1_PHY_942_DATA 0x00000000
+#define DDRSS1_PHY_943_DATA 0x00000000
+#define DDRSS1_PHY_944_DATA 0x00000000
+#define DDRSS1_PHY_945_DATA 0x00000000
+#define DDRSS1_PHY_946_DATA 0x00000000
+#define DDRSS1_PHY_947_DATA 0x00000000
+#define DDRSS1_PHY_948_DATA 0x00000000
+#define DDRSS1_PHY_949_DATA 0x00000000
+#define DDRSS1_PHY_950_DATA 0x00000000
+#define DDRSS1_PHY_951_DATA 0x00000000
+#define DDRSS1_PHY_952_DATA 0x00000000
+#define DDRSS1_PHY_953_DATA 0x00000000
+#define DDRSS1_PHY_954_DATA 0x00000000
+#define DDRSS1_PHY_955_DATA 0x00000000
+#define DDRSS1_PHY_956_DATA 0x00000000
+#define DDRSS1_PHY_957_DATA 0x00000000
+#define DDRSS1_PHY_958_DATA 0x00000000
+#define DDRSS1_PHY_959_DATA 0x00000000
+#define DDRSS1_PHY_960_DATA 0x00000000
+#define DDRSS1_PHY_961_DATA 0x00000000
+#define DDRSS1_PHY_962_DATA 0x00000000
+#define DDRSS1_PHY_963_DATA 0x00000000
+#define DDRSS1_PHY_964_DATA 0x00000000
+#define DDRSS1_PHY_965_DATA 0x00000000
+#define DDRSS1_PHY_966_DATA 0x00000000
+#define DDRSS1_PHY_967_DATA 0x00000000
+#define DDRSS1_PHY_968_DATA 0x00000000
+#define DDRSS1_PHY_969_DATA 0x00000000
+#define DDRSS1_PHY_970_DATA 0x00000000
+#define DDRSS1_PHY_971_DATA 0x00000000
+#define DDRSS1_PHY_972_DATA 0x00000000
+#define DDRSS1_PHY_973_DATA 0x00000000
+#define DDRSS1_PHY_974_DATA 0x00000000
+#define DDRSS1_PHY_975_DATA 0x00000000
+#define DDRSS1_PHY_976_DATA 0x00000000
+#define DDRSS1_PHY_977_DATA 0x00000000
+#define DDRSS1_PHY_978_DATA 0x00000000
+#define DDRSS1_PHY_979_DATA 0x00000000
+#define DDRSS1_PHY_980_DATA 0x00000000
+#define DDRSS1_PHY_981_DATA 0x00000000
+#define DDRSS1_PHY_982_DATA 0x00000000
+#define DDRSS1_PHY_983_DATA 0x00000000
+#define DDRSS1_PHY_984_DATA 0x00000000
+#define DDRSS1_PHY_985_DATA 0x00000000
+#define DDRSS1_PHY_986_DATA 0x00000000
+#define DDRSS1_PHY_987_DATA 0x00000000
+#define DDRSS1_PHY_988_DATA 0x00000000
+#define DDRSS1_PHY_989_DATA 0x00000000
+#define DDRSS1_PHY_990_DATA 0x00000000
+#define DDRSS1_PHY_991_DATA 0x00000000
+#define DDRSS1_PHY_992_DATA 0x00000000
+#define DDRSS1_PHY_993_DATA 0x00000000
+#define DDRSS1_PHY_994_DATA 0x00000000
+#define DDRSS1_PHY_995_DATA 0x00000000
+#define DDRSS1_PHY_996_DATA 0x00000000
+#define DDRSS1_PHY_997_DATA 0x00000000
+#define DDRSS1_PHY_998_DATA 0x00000000
+#define DDRSS1_PHY_999_DATA 0x00000000
+#define DDRSS1_PHY_1000_DATA 0x00000000
+#define DDRSS1_PHY_1001_DATA 0x00000000
+#define DDRSS1_PHY_1002_DATA 0x00000000
+#define DDRSS1_PHY_1003_DATA 0x00000000
+#define DDRSS1_PHY_1004_DATA 0x00000000
+#define DDRSS1_PHY_1005_DATA 0x00000000
+#define DDRSS1_PHY_1006_DATA 0x00000000
+#define DDRSS1_PHY_1007_DATA 0x00000000
+#define DDRSS1_PHY_1008_DATA 0x00000000
+#define DDRSS1_PHY_1009_DATA 0x00000000
+#define DDRSS1_PHY_1010_DATA 0x00000000
+#define DDRSS1_PHY_1011_DATA 0x00000000
+#define DDRSS1_PHY_1012_DATA 0x00000000
+#define DDRSS1_PHY_1013_DATA 0x00000000
+#define DDRSS1_PHY_1014_DATA 0x00000000
+#define DDRSS1_PHY_1015_DATA 0x00000000
+#define DDRSS1_PHY_1016_DATA 0x00000000
+#define DDRSS1_PHY_1017_DATA 0x00000000
+#define DDRSS1_PHY_1018_DATA 0x00000000
+#define DDRSS1_PHY_1019_DATA 0x00000000
+#define DDRSS1_PHY_1020_DATA 0x00000000
+#define DDRSS1_PHY_1021_DATA 0x00000000
+#define DDRSS1_PHY_1022_DATA 0x00000000
+#define DDRSS1_PHY_1023_DATA 0x00000000
+#define DDRSS1_PHY_1024_DATA 0x00000000
+#define DDRSS1_PHY_1025_DATA 0x00000000
+#define DDRSS1_PHY_1026_DATA 0x00000000
+#define DDRSS1_PHY_1027_DATA 0x00000000
+#define DDRSS1_PHY_1028_DATA 0x00000000
+#define DDRSS1_PHY_1029_DATA 0x00000100
+#define DDRSS1_PHY_1030_DATA 0x00000200
+#define DDRSS1_PHY_1031_DATA 0x00000000
+#define DDRSS1_PHY_1032_DATA 0x00000000
+#define DDRSS1_PHY_1033_DATA 0x00000000
+#define DDRSS1_PHY_1034_DATA 0x00000000
+#define DDRSS1_PHY_1035_DATA 0x00400000
+#define DDRSS1_PHY_1036_DATA 0x00000080
+#define DDRSS1_PHY_1037_DATA 0x00DCBA98
+#define DDRSS1_PHY_1038_DATA 0x03000000
+#define DDRSS1_PHY_1039_DATA 0x00200000
+#define DDRSS1_PHY_1040_DATA 0x00000000
+#define DDRSS1_PHY_1041_DATA 0x00000000
+#define DDRSS1_PHY_1042_DATA 0x00000000
+#define DDRSS1_PHY_1043_DATA 0x00000000
+#define DDRSS1_PHY_1044_DATA 0x00000000
+#define DDRSS1_PHY_1045_DATA 0x0000002A
+#define DDRSS1_PHY_1046_DATA 0x00000015
+#define DDRSS1_PHY_1047_DATA 0x00000015
+#define DDRSS1_PHY_1048_DATA 0x0000002A
+#define DDRSS1_PHY_1049_DATA 0x00000033
+#define DDRSS1_PHY_1050_DATA 0x0000000C
+#define DDRSS1_PHY_1051_DATA 0x0000000C
+#define DDRSS1_PHY_1052_DATA 0x00000033
+#define DDRSS1_PHY_1053_DATA 0x00543210
+#define DDRSS1_PHY_1054_DATA 0x003F0000
+#define DDRSS1_PHY_1055_DATA 0x000F3F3F
+#define DDRSS1_PHY_1056_DATA 0x20202003
+#define DDRSS1_PHY_1057_DATA 0x00202020
+#define DDRSS1_PHY_1058_DATA 0x20008008
+#define DDRSS1_PHY_1059_DATA 0x00000810
+#define DDRSS1_PHY_1060_DATA 0x00000F00
+#define DDRSS1_PHY_1061_DATA 0x00000000
+#define DDRSS1_PHY_1062_DATA 0x00000000
+#define DDRSS1_PHY_1063_DATA 0x00000000
+#define DDRSS1_PHY_1064_DATA 0x000305CC
+#define DDRSS1_PHY_1065_DATA 0x00030000
+#define DDRSS1_PHY_1066_DATA 0x00000300
+#define DDRSS1_PHY_1067_DATA 0x00000300
+#define DDRSS1_PHY_1068_DATA 0x00000300
+#define DDRSS1_PHY_1069_DATA 0x00000300
+#define DDRSS1_PHY_1070_DATA 0x00000300
+#define DDRSS1_PHY_1071_DATA 0x42080010
+#define DDRSS1_PHY_1072_DATA 0x0000803E
+#define DDRSS1_PHY_1073_DATA 0x00000001
+#define DDRSS1_PHY_1074_DATA 0x01000102
+#define DDRSS1_PHY_1075_DATA 0x00008000
+#define DDRSS1_PHY_1076_DATA 0x00000000
+#define DDRSS1_PHY_1077_DATA 0x00000000
+#define DDRSS1_PHY_1078_DATA 0x00000000
+#define DDRSS1_PHY_1079_DATA 0x00000000
+#define DDRSS1_PHY_1080_DATA 0x00000000
+#define DDRSS1_PHY_1081_DATA 0x00000000
+#define DDRSS1_PHY_1082_DATA 0x00000000
+#define DDRSS1_PHY_1083_DATA 0x00000000
+#define DDRSS1_PHY_1084_DATA 0x00000000
+#define DDRSS1_PHY_1085_DATA 0x00000000
+#define DDRSS1_PHY_1086_DATA 0x00000000
+#define DDRSS1_PHY_1087_DATA 0x00000000
+#define DDRSS1_PHY_1088_DATA 0x00000000
+#define DDRSS1_PHY_1089_DATA 0x00000000
+#define DDRSS1_PHY_1090_DATA 0x00000000
+#define DDRSS1_PHY_1091_DATA 0x00000000
+#define DDRSS1_PHY_1092_DATA 0x00000000
+#define DDRSS1_PHY_1093_DATA 0x00000000
+#define DDRSS1_PHY_1094_DATA 0x00000000
+#define DDRSS1_PHY_1095_DATA 0x00000000
+#define DDRSS1_PHY_1096_DATA 0x00000000
+#define DDRSS1_PHY_1097_DATA 0x00000000
+#define DDRSS1_PHY_1098_DATA 0x00000000
+#define DDRSS1_PHY_1099_DATA 0x00000000
+#define DDRSS1_PHY_1100_DATA 0x00000000
+#define DDRSS1_PHY_1101_DATA 0x00000000
+#define DDRSS1_PHY_1102_DATA 0x00000000
+#define DDRSS1_PHY_1103_DATA 0x00000000
+#define DDRSS1_PHY_1104_DATA 0x00000000
+#define DDRSS1_PHY_1105_DATA 0x00000000
+#define DDRSS1_PHY_1106_DATA 0x00000000
+#define DDRSS1_PHY_1107_DATA 0x00000000
+#define DDRSS1_PHY_1108_DATA 0x00000000
+#define DDRSS1_PHY_1109_DATA 0x00000000
+#define DDRSS1_PHY_1110_DATA 0x00000000
+#define DDRSS1_PHY_1111_DATA 0x00000000
+#define DDRSS1_PHY_1112_DATA 0x00000000
+#define DDRSS1_PHY_1113_DATA 0x00000000
+#define DDRSS1_PHY_1114_DATA 0x00000000
+#define DDRSS1_PHY_1115_DATA 0x00000000
+#define DDRSS1_PHY_1116_DATA 0x00000000
+#define DDRSS1_PHY_1117_DATA 0x00000000
+#define DDRSS1_PHY_1118_DATA 0x00000000
+#define DDRSS1_PHY_1119_DATA 0x00000000
+#define DDRSS1_PHY_1120_DATA 0x00000000
+#define DDRSS1_PHY_1121_DATA 0x00000000
+#define DDRSS1_PHY_1122_DATA 0x00000000
+#define DDRSS1_PHY_1123_DATA 0x00000000
+#define DDRSS1_PHY_1124_DATA 0x00000000
+#define DDRSS1_PHY_1125_DATA 0x00000000
+#define DDRSS1_PHY_1126_DATA 0x00000000
+#define DDRSS1_PHY_1127_DATA 0x00000000
+#define DDRSS1_PHY_1128_DATA 0x00000000
+#define DDRSS1_PHY_1129_DATA 0x00000000
+#define DDRSS1_PHY_1130_DATA 0x00000000
+#define DDRSS1_PHY_1131_DATA 0x00000000
+#define DDRSS1_PHY_1132_DATA 0x00000000
+#define DDRSS1_PHY_1133_DATA 0x00000000
+#define DDRSS1_PHY_1134_DATA 0x00000000
+#define DDRSS1_PHY_1135_DATA 0x00000000
+#define DDRSS1_PHY_1136_DATA 0x00000000
+#define DDRSS1_PHY_1137_DATA 0x00000000
+#define DDRSS1_PHY_1138_DATA 0x00000000
+#define DDRSS1_PHY_1139_DATA 0x00000000
+#define DDRSS1_PHY_1140_DATA 0x00000000
+#define DDRSS1_PHY_1141_DATA 0x00000000
+#define DDRSS1_PHY_1142_DATA 0x00000000
+#define DDRSS1_PHY_1143_DATA 0x00000000
+#define DDRSS1_PHY_1144_DATA 0x00000000
+#define DDRSS1_PHY_1145_DATA 0x00000000
+#define DDRSS1_PHY_1146_DATA 0x00000000
+#define DDRSS1_PHY_1147_DATA 0x00000000
+#define DDRSS1_PHY_1148_DATA 0x00000000
+#define DDRSS1_PHY_1149_DATA 0x00000000
+#define DDRSS1_PHY_1150_DATA 0x00000000
+#define DDRSS1_PHY_1151_DATA 0x00000000
+#define DDRSS1_PHY_1152_DATA 0x00000000
+#define DDRSS1_PHY_1153_DATA 0x00000000
+#define DDRSS1_PHY_1154_DATA 0x00000000
+#define DDRSS1_PHY_1155_DATA 0x00000000
+#define DDRSS1_PHY_1156_DATA 0x00000000
+#define DDRSS1_PHY_1157_DATA 0x00000000
+#define DDRSS1_PHY_1158_DATA 0x00000000
+#define DDRSS1_PHY_1159_DATA 0x00000000
+#define DDRSS1_PHY_1160_DATA 0x00000000
+#define DDRSS1_PHY_1161_DATA 0x00000000
+#define DDRSS1_PHY_1162_DATA 0x00000000
+#define DDRSS1_PHY_1163_DATA 0x00000000
+#define DDRSS1_PHY_1164_DATA 0x00000000
+#define DDRSS1_PHY_1165_DATA 0x00000000
+#define DDRSS1_PHY_1166_DATA 0x00000000
+#define DDRSS1_PHY_1167_DATA 0x00000000
+#define DDRSS1_PHY_1168_DATA 0x00000000
+#define DDRSS1_PHY_1169_DATA 0x00000000
+#define DDRSS1_PHY_1170_DATA 0x00000000
+#define DDRSS1_PHY_1171_DATA 0x00000000
+#define DDRSS1_PHY_1172_DATA 0x00000000
+#define DDRSS1_PHY_1173_DATA 0x00000000
+#define DDRSS1_PHY_1174_DATA 0x00000000
+#define DDRSS1_PHY_1175_DATA 0x00000000
+#define DDRSS1_PHY_1176_DATA 0x00000000
+#define DDRSS1_PHY_1177_DATA 0x00000000
+#define DDRSS1_PHY_1178_DATA 0x00000000
+#define DDRSS1_PHY_1179_DATA 0x00000000
+#define DDRSS1_PHY_1180_DATA 0x00000000
+#define DDRSS1_PHY_1181_DATA 0x00000000
+#define DDRSS1_PHY_1182_DATA 0x00000000
+#define DDRSS1_PHY_1183_DATA 0x00000000
+#define DDRSS1_PHY_1184_DATA 0x00000000
+#define DDRSS1_PHY_1185_DATA 0x00000000
+#define DDRSS1_PHY_1186_DATA 0x00000000
+#define DDRSS1_PHY_1187_DATA 0x00000000
+#define DDRSS1_PHY_1188_DATA 0x00000000
+#define DDRSS1_PHY_1189_DATA 0x00000000
+#define DDRSS1_PHY_1190_DATA 0x00000000
+#define DDRSS1_PHY_1191_DATA 0x00000000
+#define DDRSS1_PHY_1192_DATA 0x00000000
+#define DDRSS1_PHY_1193_DATA 0x00000000
+#define DDRSS1_PHY_1194_DATA 0x00000000
+#define DDRSS1_PHY_1195_DATA 0x00000000
+#define DDRSS1_PHY_1196_DATA 0x00000000
+#define DDRSS1_PHY_1197_DATA 0x00000000
+#define DDRSS1_PHY_1198_DATA 0x00000000
+#define DDRSS1_PHY_1199_DATA 0x00000000
+#define DDRSS1_PHY_1200_DATA 0x00000000
+#define DDRSS1_PHY_1201_DATA 0x00000000
+#define DDRSS1_PHY_1202_DATA 0x00000000
+#define DDRSS1_PHY_1203_DATA 0x00000000
+#define DDRSS1_PHY_1204_DATA 0x00000000
+#define DDRSS1_PHY_1205_DATA 0x00000000
+#define DDRSS1_PHY_1206_DATA 0x00000000
+#define DDRSS1_PHY_1207_DATA 0x00000000
+#define DDRSS1_PHY_1208_DATA 0x00000000
+#define DDRSS1_PHY_1209_DATA 0x00000000
+#define DDRSS1_PHY_1210_DATA 0x00000000
+#define DDRSS1_PHY_1211_DATA 0x00000000
+#define DDRSS1_PHY_1212_DATA 0x00000000
+#define DDRSS1_PHY_1213_DATA 0x00000000
+#define DDRSS1_PHY_1214_DATA 0x00000000
+#define DDRSS1_PHY_1215_DATA 0x00000000
+#define DDRSS1_PHY_1216_DATA 0x00000000
+#define DDRSS1_PHY_1217_DATA 0x00000000
+#define DDRSS1_PHY_1218_DATA 0x00000000
+#define DDRSS1_PHY_1219_DATA 0x00000000
+#define DDRSS1_PHY_1220_DATA 0x00000000
+#define DDRSS1_PHY_1221_DATA 0x00000000
+#define DDRSS1_PHY_1222_DATA 0x00000000
+#define DDRSS1_PHY_1223_DATA 0x00000000
+#define DDRSS1_PHY_1224_DATA 0x00000000
+#define DDRSS1_PHY_1225_DATA 0x00000000
+#define DDRSS1_PHY_1226_DATA 0x00000000
+#define DDRSS1_PHY_1227_DATA 0x00000000
+#define DDRSS1_PHY_1228_DATA 0x00000000
+#define DDRSS1_PHY_1229_DATA 0x00000000
+#define DDRSS1_PHY_1230_DATA 0x00000000
+#define DDRSS1_PHY_1231_DATA 0x00000000
+#define DDRSS1_PHY_1232_DATA 0x00000000
+#define DDRSS1_PHY_1233_DATA 0x00000000
+#define DDRSS1_PHY_1234_DATA 0x00000000
+#define DDRSS1_PHY_1235_DATA 0x00000000
+#define DDRSS1_PHY_1236_DATA 0x00000000
+#define DDRSS1_PHY_1237_DATA 0x00000000
+#define DDRSS1_PHY_1238_DATA 0x00000000
+#define DDRSS1_PHY_1239_DATA 0x00000000
+#define DDRSS1_PHY_1240_DATA 0x00000000
+#define DDRSS1_PHY_1241_DATA 0x00000000
+#define DDRSS1_PHY_1242_DATA 0x00000000
+#define DDRSS1_PHY_1243_DATA 0x00000000
+#define DDRSS1_PHY_1244_DATA 0x00000000
+#define DDRSS1_PHY_1245_DATA 0x00000000
+#define DDRSS1_PHY_1246_DATA 0x00000000
+#define DDRSS1_PHY_1247_DATA 0x00000000
+#define DDRSS1_PHY_1248_DATA 0x00000000
+#define DDRSS1_PHY_1249_DATA 0x00000000
+#define DDRSS1_PHY_1250_DATA 0x00000000
+#define DDRSS1_PHY_1251_DATA 0x00000000
+#define DDRSS1_PHY_1252_DATA 0x00000000
+#define DDRSS1_PHY_1253_DATA 0x00000000
+#define DDRSS1_PHY_1254_DATA 0x00000000
+#define DDRSS1_PHY_1255_DATA 0x00000000
+#define DDRSS1_PHY_1256_DATA 0x00000000
+#define DDRSS1_PHY_1257_DATA 0x00000000
+#define DDRSS1_PHY_1258_DATA 0x00000000
+#define DDRSS1_PHY_1259_DATA 0x00000000
+#define DDRSS1_PHY_1260_DATA 0x00000000
+#define DDRSS1_PHY_1261_DATA 0x00000000
+#define DDRSS1_PHY_1262_DATA 0x00000000
+#define DDRSS1_PHY_1263_DATA 0x00000000
+#define DDRSS1_PHY_1264_DATA 0x00000000
+#define DDRSS1_PHY_1265_DATA 0x00000000
+#define DDRSS1_PHY_1266_DATA 0x00000000
+#define DDRSS1_PHY_1267_DATA 0x00000000
+#define DDRSS1_PHY_1268_DATA 0x00000000
+#define DDRSS1_PHY_1269_DATA 0x00000000
+#define DDRSS1_PHY_1270_DATA 0x00000000
+#define DDRSS1_PHY_1271_DATA 0x00000000
+#define DDRSS1_PHY_1272_DATA 0x00000000
+#define DDRSS1_PHY_1273_DATA 0x00000000
+#define DDRSS1_PHY_1274_DATA 0x00000000
+#define DDRSS1_PHY_1275_DATA 0x00000000
+#define DDRSS1_PHY_1276_DATA 0x00000000
+#define DDRSS1_PHY_1277_DATA 0x00000000
+#define DDRSS1_PHY_1278_DATA 0x00000000
+#define DDRSS1_PHY_1279_DATA 0x00000000
+#define DDRSS1_PHY_1280_DATA 0x00000000
+#define DDRSS1_PHY_1281_DATA 0x00010100
+#define DDRSS1_PHY_1282_DATA 0x00000000
+#define DDRSS1_PHY_1283_DATA 0x00000000
+#define DDRSS1_PHY_1284_DATA 0x00050000
+#define DDRSS1_PHY_1285_DATA 0x04000000
+#define DDRSS1_PHY_1286_DATA 0x00000055
+#define DDRSS1_PHY_1287_DATA 0x00000000
+#define DDRSS1_PHY_1288_DATA 0x00000000
+#define DDRSS1_PHY_1289_DATA 0x00000000
+#define DDRSS1_PHY_1290_DATA 0x00000000
+#define DDRSS1_PHY_1291_DATA 0x00002001
+#define DDRSS1_PHY_1292_DATA 0x0000400F
+#define DDRSS1_PHY_1293_DATA 0x50020028
+#define DDRSS1_PHY_1294_DATA 0x01010000
+#define DDRSS1_PHY_1295_DATA 0x80080001
+#define DDRSS1_PHY_1296_DATA 0x10200000
+#define DDRSS1_PHY_1297_DATA 0x00000008
+#define DDRSS1_PHY_1298_DATA 0x00000000
+#define DDRSS1_PHY_1299_DATA 0x01090E00
+#define DDRSS1_PHY_1300_DATA 0x00040101
+#define DDRSS1_PHY_1301_DATA 0x0000010F
+#define DDRSS1_PHY_1302_DATA 0x00000000
+#define DDRSS1_PHY_1303_DATA 0x00000064
+#define DDRSS1_PHY_1304_DATA 0x00000000
+#define DDRSS1_PHY_1305_DATA 0x01010000
+#define DDRSS1_PHY_1306_DATA 0x01080402
+#define DDRSS1_PHY_1307_DATA 0x01200F02
+#define DDRSS1_PHY_1308_DATA 0x00194280
+#define DDRSS1_PHY_1309_DATA 0x00000004
+#define DDRSS1_PHY_1310_DATA 0x00042000
+#define DDRSS1_PHY_1311_DATA 0x00000000
+#define DDRSS1_PHY_1312_DATA 0x00000000
+#define DDRSS1_PHY_1313_DATA 0x00000000
+#define DDRSS1_PHY_1314_DATA 0x00000000
+#define DDRSS1_PHY_1315_DATA 0x00000000
+#define DDRSS1_PHY_1316_DATA 0x00000000
+#define DDRSS1_PHY_1317_DATA 0x01000000
+#define DDRSS1_PHY_1318_DATA 0x00000705
+#define DDRSS1_PHY_1319_DATA 0x00000054
+#define DDRSS1_PHY_1320_DATA 0x00030820
+#define DDRSS1_PHY_1321_DATA 0x00010820
+#define DDRSS1_PHY_1322_DATA 0x00010820
+#define DDRSS1_PHY_1323_DATA 0x00010820
+#define DDRSS1_PHY_1324_DATA 0x00010820
+#define DDRSS1_PHY_1325_DATA 0x00010820
+#define DDRSS1_PHY_1326_DATA 0x00010820
+#define DDRSS1_PHY_1327_DATA 0x00010820
+#define DDRSS1_PHY_1328_DATA 0x00010820
+#define DDRSS1_PHY_1329_DATA 0x00000000
+#define DDRSS1_PHY_1330_DATA 0x00000074
+#define DDRSS1_PHY_1331_DATA 0x00000400
+#define DDRSS1_PHY_1332_DATA 0x00000108
+#define DDRSS1_PHY_1333_DATA 0x00000000
+#define DDRSS1_PHY_1334_DATA 0x00000000
+#define DDRSS1_PHY_1335_DATA 0x00000000
+#define DDRSS1_PHY_1336_DATA 0x00000000
+#define DDRSS1_PHY_1337_DATA 0x00000000
+#define DDRSS1_PHY_1338_DATA 0x03000000
+#define DDRSS1_PHY_1339_DATA 0x00000000
+#define DDRSS1_PHY_1340_DATA 0x00000000
+#define DDRSS1_PHY_1341_DATA 0x00000000
+#define DDRSS1_PHY_1342_DATA 0x04102006
+#define DDRSS1_PHY_1343_DATA 0x00041020
+#define DDRSS1_PHY_1344_DATA 0x01C98C98
+#define DDRSS1_PHY_1345_DATA 0x3F400000
+#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS1_PHY_1347_DATA 0x0000001F
+#define DDRSS1_PHY_1348_DATA 0x00000000
+#define DDRSS1_PHY_1349_DATA 0x00000000
+#define DDRSS1_PHY_1350_DATA 0x00000000
+#define DDRSS1_PHY_1351_DATA 0x00010000
+#define DDRSS1_PHY_1352_DATA 0x00000000
+#define DDRSS1_PHY_1353_DATA 0x00000000
+#define DDRSS1_PHY_1354_DATA 0x00000000
+#define DDRSS1_PHY_1355_DATA 0x00000000
+#define DDRSS1_PHY_1356_DATA 0x76543210
+#define DDRSS1_PHY_1357_DATA 0x00010198
+#define DDRSS1_PHY_1358_DATA 0x00000000
+#define DDRSS1_PHY_1359_DATA 0x00000000
+#define DDRSS1_PHY_1360_DATA 0x00000000
+#define DDRSS1_PHY_1361_DATA 0x00040700
+#define DDRSS1_PHY_1362_DATA 0x00000000
+#define DDRSS1_PHY_1363_DATA 0x00000000
+#define DDRSS1_PHY_1364_DATA 0x00000000
+#define DDRSS1_PHY_1365_DATA 0x00000000
+#define DDRSS1_PHY_1366_DATA 0x00000000
+#define DDRSS1_PHY_1367_DATA 0x00000002
+#define DDRSS1_PHY_1368_DATA 0x00000000
+#define DDRSS1_PHY_1369_DATA 0x00000000
+#define DDRSS1_PHY_1370_DATA 0x00000000
+#define DDRSS1_PHY_1371_DATA 0x00000000
+#define DDRSS1_PHY_1372_DATA 0x00000000
+#define DDRSS1_PHY_1373_DATA 0x00000000
+#define DDRSS1_PHY_1374_DATA 0x00080000
+#define DDRSS1_PHY_1375_DATA 0x000007FF
+#define DDRSS1_PHY_1376_DATA 0x00000000
+#define DDRSS1_PHY_1377_DATA 0x00000000
+#define DDRSS1_PHY_1378_DATA 0x00000000
+#define DDRSS1_PHY_1379_DATA 0x00000000
+#define DDRSS1_PHY_1380_DATA 0x00000000
+#define DDRSS1_PHY_1381_DATA 0x00000000
+#define DDRSS1_PHY_1382_DATA 0x000FFFFF
+#define DDRSS1_PHY_1383_DATA 0x000FFFFF
+#define DDRSS1_PHY_1384_DATA 0x0000FFFF
+#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS1_PHY_1386_DATA 0x030FFFFF
+#define DDRSS1_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS1_PHY_1388_DATA 0x0000FFFF
+#define DDRSS1_PHY_1389_DATA 0x00000000
+#define DDRSS1_PHY_1390_DATA 0x00000000
+#define DDRSS1_PHY_1391_DATA 0x00000000
+#define DDRSS1_PHY_1392_DATA 0x00000000
+#define DDRSS1_PHY_1393_DATA 0x0001F7C0
+#define DDRSS1_PHY_1394_DATA 0x00000003
+#define DDRSS1_PHY_1395_DATA 0x00000000
+#define DDRSS1_PHY_1396_DATA 0x00001142
+#define DDRSS1_PHY_1397_DATA 0x040207AB
+#define DDRSS1_PHY_1398_DATA 0x01000080
+#define DDRSS1_PHY_1399_DATA 0x03900390
+#define DDRSS1_PHY_1400_DATA 0x03900390
+#define DDRSS1_PHY_1401_DATA 0x00000390
+#define DDRSS1_PHY_1402_DATA 0x00000390
+#define DDRSS1_PHY_1403_DATA 0x00000390
+#define DDRSS1_PHY_1404_DATA 0x00000390
+#define DDRSS1_PHY_1405_DATA 0x00000005
+#define DDRSS1_PHY_1406_DATA 0x01813FCC
+#define DDRSS1_PHY_1407_DATA 0x000000CC
+#define DDRSS1_PHY_1408_DATA 0x0C000DFF
+#define DDRSS1_PHY_1409_DATA 0x30000DFF
+#define DDRSS1_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1411_DATA 0x000100F0
+#define DDRSS1_PHY_1412_DATA 0x780DFFCC
+#define DDRSS1_PHY_1413_DATA 0x00007E31
+#define DDRSS1_PHY_1414_DATA 0x000CBF11
+#define DDRSS1_PHY_1415_DATA 0x01990010
+#define DDRSS1_PHY_1416_DATA 0x000CBF11
+#define DDRSS1_PHY_1417_DATA 0x01990010
+#define DDRSS1_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1419_DATA 0x00EF00F0
+#define DDRSS1_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1421_DATA 0x01FF00F0
+#define DDRSS1_PHY_1422_DATA 0x20040006
+
+#define DDRSS2_CTL_00_DATA 0x00000B00
+#define DDRSS2_CTL_01_DATA 0x00000000
+#define DDRSS2_CTL_02_DATA 0x00000000
+#define DDRSS2_CTL_03_DATA 0x00000000
+#define DDRSS2_CTL_04_DATA 0x00000000
+#define DDRSS2_CTL_05_DATA 0x00000000
+#define DDRSS2_CTL_06_DATA 0x00000000
+#define DDRSS2_CTL_07_DATA 0x00002AF8
+#define DDRSS2_CTL_08_DATA 0x0001ADAF
+#define DDRSS2_CTL_09_DATA 0x00000005
+#define DDRSS2_CTL_10_DATA 0x0000006E
+#define DDRSS2_CTL_11_DATA 0x000681C8
+#define DDRSS2_CTL_12_DATA 0x004111C9
+#define DDRSS2_CTL_13_DATA 0x00000005
+#define DDRSS2_CTL_14_DATA 0x000010A9
+#define DDRSS2_CTL_15_DATA 0x000681C8
+#define DDRSS2_CTL_16_DATA 0x004111C9
+#define DDRSS2_CTL_17_DATA 0x00000005
+#define DDRSS2_CTL_18_DATA 0x000010A9
+#define DDRSS2_CTL_19_DATA 0x01010000
+#define DDRSS2_CTL_20_DATA 0x01011001
+#define DDRSS2_CTL_21_DATA 0x02010000
+#define DDRSS2_CTL_22_DATA 0x00020100
+#define DDRSS2_CTL_23_DATA 0x0000000B
+#define DDRSS2_CTL_24_DATA 0x0000001C
+#define DDRSS2_CTL_25_DATA 0x00000000
+#define DDRSS2_CTL_26_DATA 0x00000000
+#define DDRSS2_CTL_27_DATA 0x03020200
+#define DDRSS2_CTL_28_DATA 0x00005656
+#define DDRSS2_CTL_29_DATA 0x00100000
+#define DDRSS2_CTL_30_DATA 0x00000000
+#define DDRSS2_CTL_31_DATA 0x00000000
+#define DDRSS2_CTL_32_DATA 0x00000000
+#define DDRSS2_CTL_33_DATA 0x00000000
+#define DDRSS2_CTL_34_DATA 0x040C0000
+#define DDRSS2_CTL_35_DATA 0x12501250
+#define DDRSS2_CTL_36_DATA 0x00050804
+#define DDRSS2_CTL_37_DATA 0x09040008
+#define DDRSS2_CTL_38_DATA 0x15000204
+#define DDRSS2_CTL_39_DATA 0x1760008B
+#define DDRSS2_CTL_40_DATA 0x1500422B
+#define DDRSS2_CTL_41_DATA 0x1760008B
+#define DDRSS2_CTL_42_DATA 0x2000422B
+#define DDRSS2_CTL_43_DATA 0x000A0A09
+#define DDRSS2_CTL_44_DATA 0x040003C5
+#define DDRSS2_CTL_45_DATA 0x1E161104
+#define DDRSS2_CTL_46_DATA 0x1000922C
+#define DDRSS2_CTL_47_DATA 0x1E161110
+#define DDRSS2_CTL_48_DATA 0x1000922C
+#define DDRSS2_CTL_49_DATA 0x02030410
+#define DDRSS2_CTL_50_DATA 0x2C060500
+#define DDRSS2_CTL_51_DATA 0x08292C29
+#define DDRSS2_CTL_52_DATA 0x14000E0A
+#define DDRSS2_CTL_53_DATA 0x04010A0A
+#define DDRSS2_CTL_54_DATA 0x01010004
+#define DDRSS2_CTL_55_DATA 0x0454540A
+#define DDRSS2_CTL_56_DATA 0x04313104
+#define DDRSS2_CTL_57_DATA 0x00003131
+#define DDRSS2_CTL_58_DATA 0x00010100
+#define DDRSS2_CTL_59_DATA 0x03010000
+#define DDRSS2_CTL_60_DATA 0x00001508
+#define DDRSS2_CTL_61_DATA 0x00000068
+#define DDRSS2_CTL_62_DATA 0x0000032B
+#define DDRSS2_CTL_63_DATA 0x00001035
+#define DDRSS2_CTL_64_DATA 0x0000032B
+#define DDRSS2_CTL_65_DATA 0x00001035
+#define DDRSS2_CTL_66_DATA 0x00000005
+#define DDRSS2_CTL_67_DATA 0x00050000
+#define DDRSS2_CTL_68_DATA 0x00CB0005
+#define DDRSS2_CTL_69_DATA 0x00CB0200
+#define DDRSS2_CTL_70_DATA 0x00400200
+#define DDRSS2_CTL_71_DATA 0x00120103
+#define DDRSS2_CTL_72_DATA 0x00100005
+#define DDRSS2_CTL_73_DATA 0x2F080010
+#define DDRSS2_CTL_74_DATA 0x0505012F
+#define DDRSS2_CTL_75_DATA 0x0401030A
+#define DDRSS2_CTL_76_DATA 0x041E100B
+#define DDRSS2_CTL_77_DATA 0x100B0401
+#define DDRSS2_CTL_78_DATA 0x0001041E
+#define DDRSS2_CTL_79_DATA 0x00160016
+#define DDRSS2_CTL_80_DATA 0x033B033B
+#define DDRSS2_CTL_81_DATA 0x033B033B
+#define DDRSS2_CTL_82_DATA 0x03050505
+#define DDRSS2_CTL_83_DATA 0x03010303
+#define DDRSS2_CTL_84_DATA 0x200B100B
+#define DDRSS2_CTL_85_DATA 0x04041004
+#define DDRSS2_CTL_86_DATA 0x200B100B
+#define DDRSS2_CTL_87_DATA 0x04041004
+#define DDRSS2_CTL_88_DATA 0x03010000
+#define DDRSS2_CTL_89_DATA 0x00010000
+#define DDRSS2_CTL_90_DATA 0x00000000
+#define DDRSS2_CTL_91_DATA 0x00000000
+#define DDRSS2_CTL_92_DATA 0x01000000
+#define DDRSS2_CTL_93_DATA 0x80104002
+#define DDRSS2_CTL_94_DATA 0x00000000
+#define DDRSS2_CTL_95_DATA 0x00040005
+#define DDRSS2_CTL_96_DATA 0x00000000
+#define DDRSS2_CTL_97_DATA 0x00050000
+#define DDRSS2_CTL_98_DATA 0x00000004
+#define DDRSS2_CTL_99_DATA 0x00000000
+#define DDRSS2_CTL_100_DATA 0x00040005
+#define DDRSS2_CTL_101_DATA 0x00000000
+#define DDRSS2_CTL_102_DATA 0x000018C0
+#define DDRSS2_CTL_103_DATA 0x000018C0
+#define DDRSS2_CTL_104_DATA 0x000018C0
+#define DDRSS2_CTL_105_DATA 0x000018C0
+#define DDRSS2_CTL_106_DATA 0x000018C0
+#define DDRSS2_CTL_107_DATA 0x00000000
+#define DDRSS2_CTL_108_DATA 0x000002B5
+#define DDRSS2_CTL_109_DATA 0x00040D40
+#define DDRSS2_CTL_110_DATA 0x00040D40
+#define DDRSS2_CTL_111_DATA 0x00040D40
+#define DDRSS2_CTL_112_DATA 0x00040D40
+#define DDRSS2_CTL_113_DATA 0x00040D40
+#define DDRSS2_CTL_114_DATA 0x00000000
+#define DDRSS2_CTL_115_DATA 0x00007173
+#define DDRSS2_CTL_116_DATA 0x00040D40
+#define DDRSS2_CTL_117_DATA 0x00040D40
+#define DDRSS2_CTL_118_DATA 0x00040D40
+#define DDRSS2_CTL_119_DATA 0x00040D40
+#define DDRSS2_CTL_120_DATA 0x00040D40
+#define DDRSS2_CTL_121_DATA 0x00000000
+#define DDRSS2_CTL_122_DATA 0x00007173
+#define DDRSS2_CTL_123_DATA 0x00000000
+#define DDRSS2_CTL_124_DATA 0x00000000
+#define DDRSS2_CTL_125_DATA 0x00000000
+#define DDRSS2_CTL_126_DATA 0x00000000
+#define DDRSS2_CTL_127_DATA 0x00000000
+#define DDRSS2_CTL_128_DATA 0x00000000
+#define DDRSS2_CTL_129_DATA 0x00000000
+#define DDRSS2_CTL_130_DATA 0x00000000
+#define DDRSS2_CTL_131_DATA 0x0B030500
+#define DDRSS2_CTL_132_DATA 0x00040B04
+#define DDRSS2_CTL_133_DATA 0x0A090000
+#define DDRSS2_CTL_134_DATA 0x0A090701
+#define DDRSS2_CTL_135_DATA 0x0900000E
+#define DDRSS2_CTL_136_DATA 0x0907010A
+#define DDRSS2_CTL_137_DATA 0x00000E0A
+#define DDRSS2_CTL_138_DATA 0x07010A09
+#define DDRSS2_CTL_139_DATA 0x000E0A09
+#define DDRSS2_CTL_140_DATA 0x07000401
+#define DDRSS2_CTL_141_DATA 0x00000000
+#define DDRSS2_CTL_142_DATA 0x00000000
+#define DDRSS2_CTL_143_DATA 0x00000000
+#define DDRSS2_CTL_144_DATA 0x00000000
+#define DDRSS2_CTL_145_DATA 0x00000000
+#define DDRSS2_CTL_146_DATA 0x00000000
+#define DDRSS2_CTL_147_DATA 0x00000000
+#define DDRSS2_CTL_148_DATA 0x08080000
+#define DDRSS2_CTL_149_DATA 0x01000000
+#define DDRSS2_CTL_150_DATA 0x800000C0
+#define DDRSS2_CTL_151_DATA 0x800000C0
+#define DDRSS2_CTL_152_DATA 0x800000C0
+#define DDRSS2_CTL_153_DATA 0x00000000
+#define DDRSS2_CTL_154_DATA 0x00001500
+#define DDRSS2_CTL_155_DATA 0x00000000
+#define DDRSS2_CTL_156_DATA 0x00000001
+#define DDRSS2_CTL_157_DATA 0x00000002
+#define DDRSS2_CTL_158_DATA 0x0000100E
+#define DDRSS2_CTL_159_DATA 0x00000000
+#define DDRSS2_CTL_160_DATA 0x00000000
+#define DDRSS2_CTL_161_DATA 0x00000000
+#define DDRSS2_CTL_162_DATA 0x00000000
+#define DDRSS2_CTL_163_DATA 0x00000000
+#define DDRSS2_CTL_164_DATA 0x000B0000
+#define DDRSS2_CTL_165_DATA 0x000E0006
+#define DDRSS2_CTL_166_DATA 0x000E0404
+#define DDRSS2_CTL_167_DATA 0x00D601AB
+#define DDRSS2_CTL_168_DATA 0x10100216
+#define DDRSS2_CTL_169_DATA 0x01AB0216
+#define DDRSS2_CTL_170_DATA 0x021600D6
+#define DDRSS2_CTL_171_DATA 0x02161010
+#define DDRSS2_CTL_172_DATA 0x00000000
+#define DDRSS2_CTL_173_DATA 0x00000000
+#define DDRSS2_CTL_174_DATA 0x00000000
+#define DDRSS2_CTL_175_DATA 0x3FF40084
+#define DDRSS2_CTL_176_DATA 0xF3003FF4
+#define DDRSS2_CTL_177_DATA 0x0000F3F3
+#define DDRSS2_CTL_178_DATA 0x35000000
+#define DDRSS2_CTL_179_DATA 0x27270035
+#define DDRSS2_CTL_180_DATA 0x0F0F0000
+#define DDRSS2_CTL_181_DATA 0x16000000
+#define DDRSS2_CTL_182_DATA 0x00841616
+#define DDRSS2_CTL_183_DATA 0x3FF43FF4
+#define DDRSS2_CTL_184_DATA 0xF3F3F300
+#define DDRSS2_CTL_185_DATA 0x00000000
+#define DDRSS2_CTL_186_DATA 0x00353500
+#define DDRSS2_CTL_187_DATA 0x00002727
+#define DDRSS2_CTL_188_DATA 0x00000F0F
+#define DDRSS2_CTL_189_DATA 0x16161600
+#define DDRSS2_CTL_190_DATA 0x00000020
+#define DDRSS2_CTL_191_DATA 0x01000000
+#define DDRSS2_CTL_192_DATA 0x00000001
+#define DDRSS2_CTL_193_DATA 0x00000000
+#define DDRSS2_CTL_194_DATA 0x01000000
+#define DDRSS2_CTL_195_DATA 0x00000001
+#define DDRSS2_CTL_196_DATA 0x00000000
+#define DDRSS2_CTL_197_DATA 0x00000000
+#define DDRSS2_CTL_198_DATA 0x00000000
+#define DDRSS2_CTL_199_DATA 0x00000000
+#define DDRSS2_CTL_200_DATA 0x00000000
+#define DDRSS2_CTL_201_DATA 0x00000000
+#define DDRSS2_CTL_202_DATA 0x00000000
+#define DDRSS2_CTL_203_DATA 0x00000000
+#define DDRSS2_CTL_204_DATA 0x00000000
+#define DDRSS2_CTL_205_DATA 0x00000000
+#define DDRSS2_CTL_206_DATA 0x02000000
+#define DDRSS2_CTL_207_DATA 0x01080101
+#define DDRSS2_CTL_208_DATA 0x00000000
+#define DDRSS2_CTL_209_DATA 0x00000000
+#define DDRSS2_CTL_210_DATA 0x00000000
+#define DDRSS2_CTL_211_DATA 0x00000000
+#define DDRSS2_CTL_212_DATA 0x00000000
+#define DDRSS2_CTL_213_DATA 0x00000000
+#define DDRSS2_CTL_214_DATA 0x00000000
+#define DDRSS2_CTL_215_DATA 0x00000000
+#define DDRSS2_CTL_216_DATA 0x00000000
+#define DDRSS2_CTL_217_DATA 0x00000000
+#define DDRSS2_CTL_218_DATA 0x00000000
+#define DDRSS2_CTL_219_DATA 0x00000000
+#define DDRSS2_CTL_220_DATA 0x00000000
+#define DDRSS2_CTL_221_DATA 0x00000000
+#define DDRSS2_CTL_222_DATA 0x00001000
+#define DDRSS2_CTL_223_DATA 0x006403E8
+#define DDRSS2_CTL_224_DATA 0x00000000
+#define DDRSS2_CTL_225_DATA 0x00000000
+#define DDRSS2_CTL_226_DATA 0x00000000
+#define DDRSS2_CTL_227_DATA 0x15110000
+#define DDRSS2_CTL_228_DATA 0x00040C18
+#define DDRSS2_CTL_229_DATA 0xF000C000
+#define DDRSS2_CTL_230_DATA 0x0000F000
+#define DDRSS2_CTL_231_DATA 0x00000000
+#define DDRSS2_CTL_232_DATA 0x00000000
+#define DDRSS2_CTL_233_DATA 0xC0000000
+#define DDRSS2_CTL_234_DATA 0xF000F000
+#define DDRSS2_CTL_235_DATA 0x00000000
+#define DDRSS2_CTL_236_DATA 0x00000000
+#define DDRSS2_CTL_237_DATA 0x00000000
+#define DDRSS2_CTL_238_DATA 0xF000C000
+#define DDRSS2_CTL_239_DATA 0x0000F000
+#define DDRSS2_CTL_240_DATA 0x00000000
+#define DDRSS2_CTL_241_DATA 0x00000000
+#define DDRSS2_CTL_242_DATA 0x00030000
+#define DDRSS2_CTL_243_DATA 0x00000000
+#define DDRSS2_CTL_244_DATA 0x00000000
+#define DDRSS2_CTL_245_DATA 0x00000000
+#define DDRSS2_CTL_246_DATA 0x00000000
+#define DDRSS2_CTL_247_DATA 0x00000000
+#define DDRSS2_CTL_248_DATA 0x00000000
+#define DDRSS2_CTL_249_DATA 0x00000000
+#define DDRSS2_CTL_250_DATA 0x00000000
+#define DDRSS2_CTL_251_DATA 0x00000000
+#define DDRSS2_CTL_252_DATA 0x00000000
+#define DDRSS2_CTL_253_DATA 0x00000000
+#define DDRSS2_CTL_254_DATA 0x00000000
+#define DDRSS2_CTL_255_DATA 0x00000000
+#define DDRSS2_CTL_256_DATA 0x00000000
+#define DDRSS2_CTL_257_DATA 0x01000200
+#define DDRSS2_CTL_258_DATA 0x00370040
+#define DDRSS2_CTL_259_DATA 0x00020008
+#define DDRSS2_CTL_260_DATA 0x00400100
+#define DDRSS2_CTL_261_DATA 0x00400855
+#define DDRSS2_CTL_262_DATA 0x01000200
+#define DDRSS2_CTL_263_DATA 0x08550040
+#define DDRSS2_CTL_264_DATA 0x00000040
+#define DDRSS2_CTL_265_DATA 0x006B0003
+#define DDRSS2_CTL_266_DATA 0x0100006B
+#define DDRSS2_CTL_267_DATA 0x03030303
+#define DDRSS2_CTL_268_DATA 0x00000000
+#define DDRSS2_CTL_269_DATA 0x00000202
+#define DDRSS2_CTL_270_DATA 0x00001FFF
+#define DDRSS2_CTL_271_DATA 0x3FFF2000
+#define DDRSS2_CTL_272_DATA 0x03FF0000
+#define DDRSS2_CTL_273_DATA 0x000103FF
+#define DDRSS2_CTL_274_DATA 0x0FFF0B00
+#define DDRSS2_CTL_275_DATA 0x01010001
+#define DDRSS2_CTL_276_DATA 0x01010101
+#define DDRSS2_CTL_277_DATA 0x01180101
+#define DDRSS2_CTL_278_DATA 0x00030000
+#define DDRSS2_CTL_279_DATA 0x00000000
+#define DDRSS2_CTL_280_DATA 0x00000000
+#define DDRSS2_CTL_281_DATA 0x00000000
+#define DDRSS2_CTL_282_DATA 0x00000000
+#define DDRSS2_CTL_283_DATA 0x00000000
+#define DDRSS2_CTL_284_DATA 0x00000000
+#define DDRSS2_CTL_285_DATA 0x00000000
+#define DDRSS2_CTL_286_DATA 0x00040101
+#define DDRSS2_CTL_287_DATA 0x04010100
+#define DDRSS2_CTL_288_DATA 0x00000000
+#define DDRSS2_CTL_289_DATA 0x00000000
+#define DDRSS2_CTL_290_DATA 0x03030300
+#define DDRSS2_CTL_291_DATA 0x00010101
+#define DDRSS2_CTL_292_DATA 0x00000000
+#define DDRSS2_CTL_293_DATA 0x00000000
+#define DDRSS2_CTL_294_DATA 0x00000000
+#define DDRSS2_CTL_295_DATA 0x00000000
+#define DDRSS2_CTL_296_DATA 0x00000000
+#define DDRSS2_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_298_DATA 0x00000FFF
+#define DDRSS2_CTL_299_DATA 0x00000000
+#define DDRSS2_CTL_300_DATA 0x00000000
+#define DDRSS2_CTL_301_DATA 0x00000000
+#define DDRSS2_CTL_302_DATA 0x00000000
+#define DDRSS2_CTL_303_DATA 0x00000000
+#define DDRSS2_CTL_304_DATA 0x00000000
+#define DDRSS2_CTL_305_DATA 0x00000000
+#define DDRSS2_CTL_306_DATA 0x00000000
+#define DDRSS2_CTL_307_DATA 0x00000000
+#define DDRSS2_CTL_308_DATA 0x00000000
+#define DDRSS2_CTL_309_DATA 0x00000000
+#define DDRSS2_CTL_310_DATA 0x00000000
+#define DDRSS2_CTL_311_DATA 0x00000000
+#define DDRSS2_CTL_312_DATA 0x00000000
+#define DDRSS2_CTL_313_DATA 0x01000000
+#define DDRSS2_CTL_314_DATA 0x00020201
+#define DDRSS2_CTL_315_DATA 0x01000101
+#define DDRSS2_CTL_316_DATA 0x01010001
+#define DDRSS2_CTL_317_DATA 0x00010101
+#define DDRSS2_CTL_318_DATA 0x050A0A03
+#define DDRSS2_CTL_319_DATA 0x10082323
+#define DDRSS2_CTL_320_DATA 0x00090310
+#define DDRSS2_CTL_321_DATA 0x0B0C030F
+#define DDRSS2_CTL_322_DATA 0x0B0C0306
+#define DDRSS2_CTL_323_DATA 0x0C090006
+#define DDRSS2_CTL_324_DATA 0x0100000C
+#define DDRSS2_CTL_325_DATA 0x08040801
+#define DDRSS2_CTL_326_DATA 0x00000004
+#define DDRSS2_CTL_327_DATA 0x00000000
+#define DDRSS2_CTL_328_DATA 0x00010000
+#define DDRSS2_CTL_329_DATA 0x00280D00
+#define DDRSS2_CTL_330_DATA 0x00000001
+#define DDRSS2_CTL_331_DATA 0x00030001
+#define DDRSS2_CTL_332_DATA 0x00000000
+#define DDRSS2_CTL_333_DATA 0x00000000
+#define DDRSS2_CTL_334_DATA 0x00000000
+#define DDRSS2_CTL_335_DATA 0x00000000
+#define DDRSS2_CTL_336_DATA 0x00000000
+#define DDRSS2_CTL_337_DATA 0x00000000
+#define DDRSS2_CTL_338_DATA 0x00000000
+#define DDRSS2_CTL_339_DATA 0x00000000
+#define DDRSS2_CTL_340_DATA 0x01000000
+#define DDRSS2_CTL_341_DATA 0x00000001
+#define DDRSS2_CTL_342_DATA 0x00010100
+#define DDRSS2_CTL_343_DATA 0x03030000
+#define DDRSS2_CTL_344_DATA 0x00000000
+#define DDRSS2_CTL_345_DATA 0x00000000
+#define DDRSS2_CTL_346_DATA 0x00000000
+#define DDRSS2_CTL_347_DATA 0x00000000
+#define DDRSS2_CTL_348_DATA 0x00000000
+#define DDRSS2_CTL_349_DATA 0x00000000
+#define DDRSS2_CTL_350_DATA 0x00000000
+#define DDRSS2_CTL_351_DATA 0x00000000
+#define DDRSS2_CTL_352_DATA 0x00000000
+#define DDRSS2_CTL_353_DATA 0x00000000
+#define DDRSS2_CTL_354_DATA 0x00000000
+#define DDRSS2_CTL_355_DATA 0x00000000
+#define DDRSS2_CTL_356_DATA 0x00000000
+#define DDRSS2_CTL_357_DATA 0x00000000
+#define DDRSS2_CTL_358_DATA 0x00000000
+#define DDRSS2_CTL_359_DATA 0x00000000
+#define DDRSS2_CTL_360_DATA 0x000556AA
+#define DDRSS2_CTL_361_DATA 0x000AAAAA
+#define DDRSS2_CTL_362_DATA 0x000AA955
+#define DDRSS2_CTL_363_DATA 0x00055555
+#define DDRSS2_CTL_364_DATA 0x000B3133
+#define DDRSS2_CTL_365_DATA 0x0004CD33
+#define DDRSS2_CTL_366_DATA 0x0004CECC
+#define DDRSS2_CTL_367_DATA 0x000B32CC
+#define DDRSS2_CTL_368_DATA 0x00010300
+#define DDRSS2_CTL_369_DATA 0x03000100
+#define DDRSS2_CTL_370_DATA 0x00000000
+#define DDRSS2_CTL_371_DATA 0x00000000
+#define DDRSS2_CTL_372_DATA 0x00000000
+#define DDRSS2_CTL_373_DATA 0x00000000
+#define DDRSS2_CTL_374_DATA 0x00000000
+#define DDRSS2_CTL_375_DATA 0x00000000
+#define DDRSS2_CTL_376_DATA 0x00000000
+#define DDRSS2_CTL_377_DATA 0x00010000
+#define DDRSS2_CTL_378_DATA 0x00000404
+#define DDRSS2_CTL_379_DATA 0x00000000
+#define DDRSS2_CTL_380_DATA 0x00000000
+#define DDRSS2_CTL_381_DATA 0x00000000
+#define DDRSS2_CTL_382_DATA 0x00000000
+#define DDRSS2_CTL_383_DATA 0x00000000
+#define DDRSS2_CTL_384_DATA 0x00000000
+#define DDRSS2_CTL_385_DATA 0x00000000
+#define DDRSS2_CTL_386_DATA 0x00000000
+#define DDRSS2_CTL_387_DATA 0x3A3A1B00
+#define DDRSS2_CTL_388_DATA 0x000A0000
+#define DDRSS2_CTL_389_DATA 0x000000C6
+#define DDRSS2_CTL_390_DATA 0x00000200
+#define DDRSS2_CTL_391_DATA 0x00000200
+#define DDRSS2_CTL_392_DATA 0x00000200
+#define DDRSS2_CTL_393_DATA 0x00000200
+#define DDRSS2_CTL_394_DATA 0x00000270
+#define DDRSS2_CTL_395_DATA 0x000007BC
+#define DDRSS2_CTL_396_DATA 0x00000204
+#define DDRSS2_CTL_397_DATA 0x0000206A
+#define DDRSS2_CTL_398_DATA 0x00000200
+#define DDRSS2_CTL_399_DATA 0x00000200
+#define DDRSS2_CTL_400_DATA 0x00000200
+#define DDRSS2_CTL_401_DATA 0x00000200
+#define DDRSS2_CTL_402_DATA 0x0000613E
+#define DDRSS2_CTL_403_DATA 0x00014424
+#define DDRSS2_CTL_404_DATA 0x00000E19
+#define DDRSS2_CTL_405_DATA 0x0000206A
+#define DDRSS2_CTL_406_DATA 0x00000200
+#define DDRSS2_CTL_407_DATA 0x00000200
+#define DDRSS2_CTL_408_DATA 0x00000200
+#define DDRSS2_CTL_409_DATA 0x00000200
+#define DDRSS2_CTL_410_DATA 0x0000613E
+#define DDRSS2_CTL_411_DATA 0x00014424
+#define DDRSS2_CTL_412_DATA 0x02020E19
+#define DDRSS2_CTL_413_DATA 0x03030202
+#define DDRSS2_CTL_414_DATA 0x00000022
+#define DDRSS2_CTL_415_DATA 0x00000000
+#define DDRSS2_CTL_416_DATA 0x00000000
+#define DDRSS2_CTL_417_DATA 0x00001403
+#define DDRSS2_CTL_418_DATA 0x000007D0
+#define DDRSS2_CTL_419_DATA 0x00000000
+#define DDRSS2_CTL_420_DATA 0x00000000
+#define DDRSS2_CTL_421_DATA 0x00030000
+#define DDRSS2_CTL_422_DATA 0x0007001F
+#define DDRSS2_CTL_423_DATA 0x001B0033
+#define DDRSS2_CTL_424_DATA 0x001B0033
+#define DDRSS2_CTL_425_DATA 0x00000000
+#define DDRSS2_CTL_426_DATA 0x00000000
+#define DDRSS2_CTL_427_DATA 0x02000000
+#define DDRSS2_CTL_428_DATA 0x01000404
+#define DDRSS2_CTL_429_DATA 0x0B220B22
+#define DDRSS2_CTL_430_DATA 0x00000105
+#define DDRSS2_CTL_431_DATA 0x00010101
+#define DDRSS2_CTL_432_DATA 0x00010101
+#define DDRSS2_CTL_433_DATA 0x00010001
+#define DDRSS2_CTL_434_DATA 0x00000101
+#define DDRSS2_CTL_435_DATA 0x02000201
+#define DDRSS2_CTL_436_DATA 0x02010000
+#define DDRSS2_CTL_437_DATA 0x00000200
+#define DDRSS2_CTL_438_DATA 0x28060000
+#define DDRSS2_CTL_439_DATA 0x00000128
+#define DDRSS2_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_442_DATA 0x00000000
+#define DDRSS2_CTL_443_DATA 0x00000000
+#define DDRSS2_CTL_444_DATA 0x00000000
+#define DDRSS2_CTL_445_DATA 0x00000000
+#define DDRSS2_CTL_446_DATA 0x00000000
+#define DDRSS2_CTL_447_DATA 0x00000000
+#define DDRSS2_CTL_448_DATA 0x00000000
+#define DDRSS2_CTL_449_DATA 0x00000000
+#define DDRSS2_CTL_450_DATA 0x00000000
+#define DDRSS2_CTL_451_DATA 0x00000000
+#define DDRSS2_CTL_452_DATA 0x00000000
+#define DDRSS2_CTL_453_DATA 0x00000000
+#define DDRSS2_CTL_454_DATA 0x00000000
+#define DDRSS2_CTL_455_DATA 0x00000000
+#define DDRSS2_CTL_456_DATA 0x00000000
+#define DDRSS2_CTL_457_DATA 0x00000000
+#define DDRSS2_CTL_458_DATA 0x00000000
+
+#define DDRSS2_PI_00_DATA 0x00000B00
+#define DDRSS2_PI_01_DATA 0x00000000
+#define DDRSS2_PI_02_DATA 0x00000000
+#define DDRSS2_PI_03_DATA 0x00000000
+#define DDRSS2_PI_04_DATA 0x00000000
+#define DDRSS2_PI_05_DATA 0x00000101
+#define DDRSS2_PI_06_DATA 0x00640000
+#define DDRSS2_PI_07_DATA 0x00000001
+#define DDRSS2_PI_08_DATA 0x00000000
+#define DDRSS2_PI_09_DATA 0x00000000
+#define DDRSS2_PI_10_DATA 0x00000000
+#define DDRSS2_PI_11_DATA 0x00000000
+#define DDRSS2_PI_12_DATA 0x00000003
+#define DDRSS2_PI_13_DATA 0x00010001
+#define DDRSS2_PI_14_DATA 0x0800000F
+#define DDRSS2_PI_15_DATA 0x00000103
+#define DDRSS2_PI_16_DATA 0x00000005
+#define DDRSS2_PI_17_DATA 0x00000000
+#define DDRSS2_PI_18_DATA 0x00000000
+#define DDRSS2_PI_19_DATA 0x00000000
+#define DDRSS2_PI_20_DATA 0x00000000
+#define DDRSS2_PI_21_DATA 0x00000000
+#define DDRSS2_PI_22_DATA 0x00000000
+#define DDRSS2_PI_23_DATA 0x00000000
+#define DDRSS2_PI_24_DATA 0x00000000
+#define DDRSS2_PI_25_DATA 0x00000000
+#define DDRSS2_PI_26_DATA 0x00010100
+#define DDRSS2_PI_27_DATA 0x00280A00
+#define DDRSS2_PI_28_DATA 0x00000000
+#define DDRSS2_PI_29_DATA 0x0F000000
+#define DDRSS2_PI_30_DATA 0x00003200
+#define DDRSS2_PI_31_DATA 0x00000000
+#define DDRSS2_PI_32_DATA 0x00000000
+#define DDRSS2_PI_33_DATA 0x01010102
+#define DDRSS2_PI_34_DATA 0x00000000
+#define DDRSS2_PI_35_DATA 0x000000AA
+#define DDRSS2_PI_36_DATA 0x00000055
+#define DDRSS2_PI_37_DATA 0x000000B5
+#define DDRSS2_PI_38_DATA 0x0000004A
+#define DDRSS2_PI_39_DATA 0x00000056
+#define DDRSS2_PI_40_DATA 0x000000A9
+#define DDRSS2_PI_41_DATA 0x000000A9
+#define DDRSS2_PI_42_DATA 0x000000B5
+#define DDRSS2_PI_43_DATA 0x00000000
+#define DDRSS2_PI_44_DATA 0x00000000
+#define DDRSS2_PI_45_DATA 0x000F0F00
+#define DDRSS2_PI_46_DATA 0x0000001B
+#define DDRSS2_PI_47_DATA 0x000007D0
+#define DDRSS2_PI_48_DATA 0x00000300
+#define DDRSS2_PI_49_DATA 0x00000000
+#define DDRSS2_PI_50_DATA 0x00000000
+#define DDRSS2_PI_51_DATA 0x01000000
+#define DDRSS2_PI_52_DATA 0x00010101
+#define DDRSS2_PI_53_DATA 0x00000000
+#define DDRSS2_PI_54_DATA 0x00030000
+#define DDRSS2_PI_55_DATA 0x0F000000
+#define DDRSS2_PI_56_DATA 0x00000017
+#define DDRSS2_PI_57_DATA 0x00000000
+#define DDRSS2_PI_58_DATA 0x00000000
+#define DDRSS2_PI_59_DATA 0x00000000
+#define DDRSS2_PI_60_DATA 0x0A0A140A
+#define DDRSS2_PI_61_DATA 0x10020201
+#define DDRSS2_PI_62_DATA 0x00020805
+#define DDRSS2_PI_63_DATA 0x01000404
+#define DDRSS2_PI_64_DATA 0x00000000
+#define DDRSS2_PI_65_DATA 0x00000000
+#define DDRSS2_PI_66_DATA 0x00000100
+#define DDRSS2_PI_67_DATA 0x0002020F
+#define DDRSS2_PI_68_DATA 0x00340000
+#define DDRSS2_PI_69_DATA 0x00000000
+#define DDRSS2_PI_70_DATA 0x00000000
+#define DDRSS2_PI_71_DATA 0x0000FFFF
+#define DDRSS2_PI_72_DATA 0x01000000
+#define DDRSS2_PI_73_DATA 0x00080000
+#define DDRSS2_PI_74_DATA 0x02000200
+#define DDRSS2_PI_75_DATA 0x01000100
+#define DDRSS2_PI_76_DATA 0x01000000
+#define DDRSS2_PI_77_DATA 0x02000200
+#define DDRSS2_PI_78_DATA 0x00000200
+#define DDRSS2_PI_79_DATA 0x00000000
+#define DDRSS2_PI_80_DATA 0x00000000
+#define DDRSS2_PI_81_DATA 0x00000000
+#define DDRSS2_PI_82_DATA 0x00000000
+#define DDRSS2_PI_83_DATA 0x00000000
+#define DDRSS2_PI_84_DATA 0x00000000
+#define DDRSS2_PI_85_DATA 0x00000000
+#define DDRSS2_PI_86_DATA 0x00000000
+#define DDRSS2_PI_87_DATA 0x00000000
+#define DDRSS2_PI_88_DATA 0x00000000
+#define DDRSS2_PI_89_DATA 0x00000000
+#define DDRSS2_PI_90_DATA 0x00000000
+#define DDRSS2_PI_91_DATA 0x00000400
+#define DDRSS2_PI_92_DATA 0x02010000
+#define DDRSS2_PI_93_DATA 0x00080003
+#define DDRSS2_PI_94_DATA 0x00080000
+#define DDRSS2_PI_95_DATA 0x00000001
+#define DDRSS2_PI_96_DATA 0x00000000
+#define DDRSS2_PI_97_DATA 0x0000AA00
+#define DDRSS2_PI_98_DATA 0x00000000
+#define DDRSS2_PI_99_DATA 0x00000000
+#define DDRSS2_PI_100_DATA 0x00010000
+#define DDRSS2_PI_101_DATA 0x00000000
+#define DDRSS2_PI_102_DATA 0x00000000
+#define DDRSS2_PI_103_DATA 0x00000000
+#define DDRSS2_PI_104_DATA 0x00000000
+#define DDRSS2_PI_105_DATA 0x00000000
+#define DDRSS2_PI_106_DATA 0x00000000
+#define DDRSS2_PI_107_DATA 0x00000000
+#define DDRSS2_PI_108_DATA 0x00000000
+#define DDRSS2_PI_109_DATA 0x00000000
+#define DDRSS2_PI_110_DATA 0x00000000
+#define DDRSS2_PI_111_DATA 0x00000000
+#define DDRSS2_PI_112_DATA 0x00000000
+#define DDRSS2_PI_113_DATA 0x00000000
+#define DDRSS2_PI_114_DATA 0x00000000
+#define DDRSS2_PI_115_DATA 0x00000000
+#define DDRSS2_PI_116_DATA 0x00000000
+#define DDRSS2_PI_117_DATA 0x00000000
+#define DDRSS2_PI_118_DATA 0x00000000
+#define DDRSS2_PI_119_DATA 0x00000000
+#define DDRSS2_PI_120_DATA 0x00000000
+#define DDRSS2_PI_121_DATA 0x00000000
+#define DDRSS2_PI_122_DATA 0x00000000
+#define DDRSS2_PI_123_DATA 0x00000000
+#define DDRSS2_PI_124_DATA 0x00000000
+#define DDRSS2_PI_125_DATA 0x00000008
+#define DDRSS2_PI_126_DATA 0x00000000
+#define DDRSS2_PI_127_DATA 0x00000000
+#define DDRSS2_PI_128_DATA 0x00000000
+#define DDRSS2_PI_129_DATA 0x00000000
+#define DDRSS2_PI_130_DATA 0x00000000
+#define DDRSS2_PI_131_DATA 0x00000000
+#define DDRSS2_PI_132_DATA 0x00000000
+#define DDRSS2_PI_133_DATA 0x00000000
+#define DDRSS2_PI_134_DATA 0x00000002
+#define DDRSS2_PI_135_DATA 0x00000000
+#define DDRSS2_PI_136_DATA 0x00000000
+#define DDRSS2_PI_137_DATA 0x0000000A
+#define DDRSS2_PI_138_DATA 0x00000019
+#define DDRSS2_PI_139_DATA 0x00000100
+#define DDRSS2_PI_140_DATA 0x00000000
+#define DDRSS2_PI_141_DATA 0x00000000
+#define DDRSS2_PI_142_DATA 0x00000000
+#define DDRSS2_PI_143_DATA 0x00000000
+#define DDRSS2_PI_144_DATA 0x01000000
+#define DDRSS2_PI_145_DATA 0x00010003
+#define DDRSS2_PI_146_DATA 0x02000101
+#define DDRSS2_PI_147_DATA 0x01030001
+#define DDRSS2_PI_148_DATA 0x00010400
+#define DDRSS2_PI_149_DATA 0x06000105
+#define DDRSS2_PI_150_DATA 0x01070001
+#define DDRSS2_PI_151_DATA 0x00000000
+#define DDRSS2_PI_152_DATA 0x00000000
+#define DDRSS2_PI_153_DATA 0x00000000
+#define DDRSS2_PI_154_DATA 0x00010001
+#define DDRSS2_PI_155_DATA 0x00000000
+#define DDRSS2_PI_156_DATA 0x00000000
+#define DDRSS2_PI_157_DATA 0x00000000
+#define DDRSS2_PI_158_DATA 0x00000000
+#define DDRSS2_PI_159_DATA 0x00000401
+#define DDRSS2_PI_160_DATA 0x00000000
+#define DDRSS2_PI_161_DATA 0x05010000
+#define DDRSS2_PI_162_DATA 0x00000001
+#define DDRSS2_PI_163_DATA 0x2B2B0201
+#define DDRSS2_PI_164_DATA 0x00000034
+#define DDRSS2_PI_165_DATA 0x00000068
+#define DDRSS2_PI_166_DATA 0x00020068
+#define DDRSS2_PI_167_DATA 0x02000200
+#define DDRSS2_PI_168_DATA 0x50120C04
+#define DDRSS2_PI_169_DATA 0x00155012
+#define DDRSS2_PI_170_DATA 0x00000068
+#define DDRSS2_PI_171_DATA 0x0000032B
+#define DDRSS2_PI_172_DATA 0x00001035
+#define DDRSS2_PI_173_DATA 0x0000032B
+#define DDRSS2_PI_174_DATA 0x04001035
+#define DDRSS2_PI_175_DATA 0x01010404
+#define DDRSS2_PI_176_DATA 0x00001500
+#define DDRSS2_PI_177_DATA 0x00150015
+#define DDRSS2_PI_178_DATA 0x01000100
+#define DDRSS2_PI_179_DATA 0x00000100
+#define DDRSS2_PI_180_DATA 0x00000000
+#define DDRSS2_PI_181_DATA 0x01010101
+#define DDRSS2_PI_182_DATA 0x00000000
+#define DDRSS2_PI_183_DATA 0x00000000
+#define DDRSS2_PI_184_DATA 0x00000000
+#define DDRSS2_PI_185_DATA 0x19040000
+#define DDRSS2_PI_186_DATA 0x0E0E0219
+#define DDRSS2_PI_187_DATA 0x00040402
+#define DDRSS2_PI_188_DATA 0x000D0035
+#define DDRSS2_PI_189_DATA 0x00218049
+#define DDRSS2_PI_190_DATA 0x00218049
+#define DDRSS2_PI_191_DATA 0x01000101
+#define DDRSS2_PI_192_DATA 0x0004000E
+#define DDRSS2_PI_193_DATA 0x00040216
+#define DDRSS2_PI_194_DATA 0x01000216
+#define DDRSS2_PI_195_DATA 0x000F000F
+#define DDRSS2_PI_196_DATA 0x02170100
+#define DDRSS2_PI_197_DATA 0x01000217
+#define DDRSS2_PI_198_DATA 0x02170217
+#define DDRSS2_PI_199_DATA 0x2F1B3200
+#define DDRSS2_PI_200_DATA 0x01012F1B
+#define DDRSS2_PI_201_DATA 0x0A070601
+#define DDRSS2_PI_202_DATA 0x1F130A0D
+#define DDRSS2_PI_203_DATA 0x1F130A14
+#define DDRSS2_PI_204_DATA 0x0000C014
+#define DDRSS2_PI_205_DATA 0x00C01000
+#define DDRSS2_PI_206_DATA 0x00C01000
+#define DDRSS2_PI_207_DATA 0x00021000
+#define DDRSS2_PI_208_DATA 0x0024000E
+#define DDRSS2_PI_209_DATA 0x00240216
+#define DDRSS2_PI_210_DATA 0x00110216
+#define DDRSS2_PI_211_DATA 0x32000056
+#define DDRSS2_PI_212_DATA 0x00000101
+#define DDRSS2_PI_213_DATA 0x005F0036
+#define DDRSS2_PI_214_DATA 0x03013212
+#define DDRSS2_PI_215_DATA 0x00003600
+#define DDRSS2_PI_216_DATA 0x3212005F
+#define DDRSS2_PI_217_DATA 0x09000001
+#define DDRSS2_PI_218_DATA 0x06010504
+#define DDRSS2_PI_219_DATA 0x04000364
+#define DDRSS2_PI_220_DATA 0x0A032001
+#define DDRSS2_PI_221_DATA 0x2C31110A
+#define DDRSS2_PI_222_DATA 0x00002918
+#define DDRSS2_PI_223_DATA 0x6000838E
+#define DDRSS2_PI_224_DATA 0x1E202008
+#define DDRSS2_PI_225_DATA 0x2C311116
+#define DDRSS2_PI_226_DATA 0x00002918
+#define DDRSS2_PI_227_DATA 0x6000838E
+#define DDRSS2_PI_228_DATA 0x1E202008
+#define DDRSS2_PI_229_DATA 0x0000C616
+#define DDRSS2_PI_230_DATA 0x000007BC
+#define DDRSS2_PI_231_DATA 0x0000206A
+#define DDRSS2_PI_232_DATA 0x00014424
+#define DDRSS2_PI_233_DATA 0x0000206A
+#define DDRSS2_PI_234_DATA 0x00014424
+#define DDRSS2_PI_235_DATA 0x033B0016
+#define DDRSS2_PI_236_DATA 0x0303033B
+#define DDRSS2_PI_237_DATA 0x002AF803
+#define DDRSS2_PI_238_DATA 0x0001ADAF
+#define DDRSS2_PI_239_DATA 0x00000005
+#define DDRSS2_PI_240_DATA 0x0000006E
+#define DDRSS2_PI_241_DATA 0x00000016
+#define DDRSS2_PI_242_DATA 0x000681C8
+#define DDRSS2_PI_243_DATA 0x0001ADAF
+#define DDRSS2_PI_244_DATA 0x00000005
+#define DDRSS2_PI_245_DATA 0x000010A9
+#define DDRSS2_PI_246_DATA 0x0000033B
+#define DDRSS2_PI_247_DATA 0x000681C8
+#define DDRSS2_PI_248_DATA 0x0001ADAF
+#define DDRSS2_PI_249_DATA 0x00000005
+#define DDRSS2_PI_250_DATA 0x000010A9
+#define DDRSS2_PI_251_DATA 0x0100033B
+#define DDRSS2_PI_252_DATA 0x00370040
+#define DDRSS2_PI_253_DATA 0x00010008
+#define DDRSS2_PI_254_DATA 0x08550040
+#define DDRSS2_PI_255_DATA 0x00010040
+#define DDRSS2_PI_256_DATA 0x08550040
+#define DDRSS2_PI_257_DATA 0x00000340
+#define DDRSS2_PI_258_DATA 0x006B006B
+#define DDRSS2_PI_259_DATA 0x08040404
+#define DDRSS2_PI_260_DATA 0x00000055
+#define DDRSS2_PI_261_DATA 0x55083C5A
+#define DDRSS2_PI_262_DATA 0x5A000000
+#define DDRSS2_PI_263_DATA 0x0055083C
+#define DDRSS2_PI_264_DATA 0x3C5A0000
+#define DDRSS2_PI_265_DATA 0x00005508
+#define DDRSS2_PI_266_DATA 0x0C3C5A00
+#define DDRSS2_PI_267_DATA 0x080F0E0D
+#define DDRSS2_PI_268_DATA 0x000B0A09
+#define DDRSS2_PI_269_DATA 0x00030201
+#define DDRSS2_PI_270_DATA 0x01000000
+#define DDRSS2_PI_271_DATA 0x04020201
+#define DDRSS2_PI_272_DATA 0x00080804
+#define DDRSS2_PI_273_DATA 0x00000000
+#define DDRSS2_PI_274_DATA 0x00000000
+#define DDRSS2_PI_275_DATA 0x00F30084
+#define DDRSS2_PI_276_DATA 0x00160000
+#define DDRSS2_PI_277_DATA 0x35F33FF4
+#define DDRSS2_PI_278_DATA 0x00160F27
+#define DDRSS2_PI_279_DATA 0x35F33FF4
+#define DDRSS2_PI_280_DATA 0x00160F27
+#define DDRSS2_PI_281_DATA 0x00F30084
+#define DDRSS2_PI_282_DATA 0x00160000
+#define DDRSS2_PI_283_DATA 0x35F33FF4
+#define DDRSS2_PI_284_DATA 0x00160F27
+#define DDRSS2_PI_285_DATA 0x35F33FF4
+#define DDRSS2_PI_286_DATA 0x00160F27
+#define DDRSS2_PI_287_DATA 0x00F30084
+#define DDRSS2_PI_288_DATA 0x00160000
+#define DDRSS2_PI_289_DATA 0x35F33FF4
+#define DDRSS2_PI_290_DATA 0x00160F27
+#define DDRSS2_PI_291_DATA 0x35F33FF4
+#define DDRSS2_PI_292_DATA 0x00160F27
+#define DDRSS2_PI_293_DATA 0x00F30084
+#define DDRSS2_PI_294_DATA 0x00160000
+#define DDRSS2_PI_295_DATA 0x35F33FF4
+#define DDRSS2_PI_296_DATA 0x00160F27
+#define DDRSS2_PI_297_DATA 0x35F33FF4
+#define DDRSS2_PI_298_DATA 0x00160F27
+#define DDRSS2_PI_299_DATA 0x00000000
+
+#define DDRSS2_PHY_00_DATA 0x000004F0
+#define DDRSS2_PHY_01_DATA 0x00000000
+#define DDRSS2_PHY_02_DATA 0x00030200
+#define DDRSS2_PHY_03_DATA 0x00000000
+#define DDRSS2_PHY_04_DATA 0x00000000
+#define DDRSS2_PHY_05_DATA 0x01030000
+#define DDRSS2_PHY_06_DATA 0x00010000
+#define DDRSS2_PHY_07_DATA 0x01030004
+#define DDRSS2_PHY_08_DATA 0x01000000
+#define DDRSS2_PHY_09_DATA 0x00000000
+#define DDRSS2_PHY_10_DATA 0x00000000
+#define DDRSS2_PHY_11_DATA 0x01000001
+#define DDRSS2_PHY_12_DATA 0x00000200
+#define DDRSS2_PHY_13_DATA 0x000800C0
+#define DDRSS2_PHY_14_DATA 0x060100CC
+#define DDRSS2_PHY_15_DATA 0x00030066
+#define DDRSS2_PHY_16_DATA 0x00000000
+#define DDRSS2_PHY_17_DATA 0x00000301
+#define DDRSS2_PHY_18_DATA 0x0000AAAA
+#define DDRSS2_PHY_19_DATA 0x00005555
+#define DDRSS2_PHY_20_DATA 0x0000B5B5
+#define DDRSS2_PHY_21_DATA 0x00004A4A
+#define DDRSS2_PHY_22_DATA 0x00005656
+#define DDRSS2_PHY_23_DATA 0x0000A9A9
+#define DDRSS2_PHY_24_DATA 0x0000A9A9
+#define DDRSS2_PHY_25_DATA 0x0000B5B5
+#define DDRSS2_PHY_26_DATA 0x00000000
+#define DDRSS2_PHY_27_DATA 0x00000000
+#define DDRSS2_PHY_28_DATA 0x2A000000
+#define DDRSS2_PHY_29_DATA 0x00000808
+#define DDRSS2_PHY_30_DATA 0x0F000000
+#define DDRSS2_PHY_31_DATA 0x00000F08
+#define DDRSS2_PHY_32_DATA 0x10400000
+#define DDRSS2_PHY_33_DATA 0x0C002006
+#define DDRSS2_PHY_34_DATA 0x00000000
+#define DDRSS2_PHY_35_DATA 0x00000000
+#define DDRSS2_PHY_36_DATA 0x55555555
+#define DDRSS2_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_38_DATA 0x55555555
+#define DDRSS2_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_40_DATA 0x00005555
+#define DDRSS2_PHY_41_DATA 0x01000100
+#define DDRSS2_PHY_42_DATA 0x00800180
+#define DDRSS2_PHY_43_DATA 0x00000001
+#define DDRSS2_PHY_44_DATA 0x00000000
+#define DDRSS2_PHY_45_DATA 0x00000000
+#define DDRSS2_PHY_46_DATA 0x00000000
+#define DDRSS2_PHY_47_DATA 0x00000000
+#define DDRSS2_PHY_48_DATA 0x00000000
+#define DDRSS2_PHY_49_DATA 0x00000000
+#define DDRSS2_PHY_50_DATA 0x00000000
+#define DDRSS2_PHY_51_DATA 0x00000000
+#define DDRSS2_PHY_52_DATA 0x00000000
+#define DDRSS2_PHY_53_DATA 0x00000000
+#define DDRSS2_PHY_54_DATA 0x00000000
+#define DDRSS2_PHY_55_DATA 0x00000000
+#define DDRSS2_PHY_56_DATA 0x00000000
+#define DDRSS2_PHY_57_DATA 0x00000000
+#define DDRSS2_PHY_58_DATA 0x00000000
+#define DDRSS2_PHY_59_DATA 0x00000000
+#define DDRSS2_PHY_60_DATA 0x00000000
+#define DDRSS2_PHY_61_DATA 0x00000000
+#define DDRSS2_PHY_62_DATA 0x00000000
+#define DDRSS2_PHY_63_DATA 0x00000000
+#define DDRSS2_PHY_64_DATA 0x00000000
+#define DDRSS2_PHY_65_DATA 0x00000000
+#define DDRSS2_PHY_66_DATA 0x00000104
+#define DDRSS2_PHY_67_DATA 0x00000120
+#define DDRSS2_PHY_68_DATA 0x00000000
+#define DDRSS2_PHY_69_DATA 0x00000000
+#define DDRSS2_PHY_70_DATA 0x00000000
+#define DDRSS2_PHY_71_DATA 0x00000000
+#define DDRSS2_PHY_72_DATA 0x00000000
+#define DDRSS2_PHY_73_DATA 0x00000000
+#define DDRSS2_PHY_74_DATA 0x00000000
+#define DDRSS2_PHY_75_DATA 0x00000001
+#define DDRSS2_PHY_76_DATA 0x07FF0000
+#define DDRSS2_PHY_77_DATA 0x0080081F
+#define DDRSS2_PHY_78_DATA 0x00081020
+#define DDRSS2_PHY_79_DATA 0x04010000
+#define DDRSS2_PHY_80_DATA 0x00000000
+#define DDRSS2_PHY_81_DATA 0x00000000
+#define DDRSS2_PHY_82_DATA 0x00000000
+#define DDRSS2_PHY_83_DATA 0x00000100
+#define DDRSS2_PHY_84_DATA 0x01CC0C01
+#define DDRSS2_PHY_85_DATA 0x1003CC0C
+#define DDRSS2_PHY_86_DATA 0x20000140
+#define DDRSS2_PHY_87_DATA 0x07FF0200
+#define DDRSS2_PHY_88_DATA 0x0000DD01
+#define DDRSS2_PHY_89_DATA 0x10100303
+#define DDRSS2_PHY_90_DATA 0x10101010
+#define DDRSS2_PHY_91_DATA 0x10101010
+#define DDRSS2_PHY_92_DATA 0x00021010
+#define DDRSS2_PHY_93_DATA 0x00100010
+#define DDRSS2_PHY_94_DATA 0x00100010
+#define DDRSS2_PHY_95_DATA 0x00100010
+#define DDRSS2_PHY_96_DATA 0x00100010
+#define DDRSS2_PHY_97_DATA 0x00050010
+#define DDRSS2_PHY_98_DATA 0x51517041
+#define DDRSS2_PHY_99_DATA 0x31C06001
+#define DDRSS2_PHY_100_DATA 0x07AB01AB
+#define DDRSS2_PHY_101_DATA 0x00C0C001
+#define DDRSS2_PHY_102_DATA 0x0E0D0101
+#define DDRSS2_PHY_103_DATA 0x10001000
+#define DDRSS2_PHY_104_DATA 0x0C083E42
+#define DDRSS2_PHY_105_DATA 0x0F0C3701
+#define DDRSS2_PHY_106_DATA 0x01000140
+#define DDRSS2_PHY_107_DATA 0x0C000420
+#define DDRSS2_PHY_108_DATA 0x00000198
+#define DDRSS2_PHY_109_DATA 0x0A0000D0
+#define DDRSS2_PHY_110_DATA 0x00030200
+#define DDRSS2_PHY_111_DATA 0x02800000
+#define DDRSS2_PHY_112_DATA 0x80800000
+#define DDRSS2_PHY_113_DATA 0x000E2010
+#define DDRSS2_PHY_114_DATA 0x76543210
+#define DDRSS2_PHY_115_DATA 0x00000008
+#define DDRSS2_PHY_116_DATA 0x02800280
+#define DDRSS2_PHY_117_DATA 0x02800280
+#define DDRSS2_PHY_118_DATA 0x02800280
+#define DDRSS2_PHY_119_DATA 0x02800280
+#define DDRSS2_PHY_120_DATA 0x00000280
+#define DDRSS2_PHY_121_DATA 0x0000A000
+#define DDRSS2_PHY_122_DATA 0x00A000A0
+#define DDRSS2_PHY_123_DATA 0x00A000A0
+#define DDRSS2_PHY_124_DATA 0x00A000A0
+#define DDRSS2_PHY_125_DATA 0x00A000A0
+#define DDRSS2_PHY_126_DATA 0x00A000A0
+#define DDRSS2_PHY_127_DATA 0x00A000A0
+#define DDRSS2_PHY_128_DATA 0x00A000A0
+#define DDRSS2_PHY_129_DATA 0x00A000A0
+#define DDRSS2_PHY_130_DATA 0x01C200A0
+#define DDRSS2_PHY_131_DATA 0x01A00005
+#define DDRSS2_PHY_132_DATA 0x00000000
+#define DDRSS2_PHY_133_DATA 0x00000000
+#define DDRSS2_PHY_134_DATA 0x00080200
+#define DDRSS2_PHY_135_DATA 0x00000000
+#define DDRSS2_PHY_136_DATA 0x20202000
+#define DDRSS2_PHY_137_DATA 0x20202020
+#define DDRSS2_PHY_138_DATA 0xF0F02020
+#define DDRSS2_PHY_139_DATA 0x00000000
+#define DDRSS2_PHY_140_DATA 0x00000000
+#define DDRSS2_PHY_141_DATA 0x00000000
+#define DDRSS2_PHY_142_DATA 0x00000000
+#define DDRSS2_PHY_143_DATA 0x00000000
+#define DDRSS2_PHY_144_DATA 0x00000000
+#define DDRSS2_PHY_145_DATA 0x00000000
+#define DDRSS2_PHY_146_DATA 0x00000000
+#define DDRSS2_PHY_147_DATA 0x00000000
+#define DDRSS2_PHY_148_DATA 0x00000000
+#define DDRSS2_PHY_149_DATA 0x00000000
+#define DDRSS2_PHY_150_DATA 0x00000000
+#define DDRSS2_PHY_151_DATA 0x00000000
+#define DDRSS2_PHY_152_DATA 0x00000000
+#define DDRSS2_PHY_153_DATA 0x00000000
+#define DDRSS2_PHY_154_DATA 0x00000000
+#define DDRSS2_PHY_155_DATA 0x00000000
+#define DDRSS2_PHY_156_DATA 0x00000000
+#define DDRSS2_PHY_157_DATA 0x00000000
+#define DDRSS2_PHY_158_DATA 0x00000000
+#define DDRSS2_PHY_159_DATA 0x00000000
+#define DDRSS2_PHY_160_DATA 0x00000000
+#define DDRSS2_PHY_161_DATA 0x00000000
+#define DDRSS2_PHY_162_DATA 0x00000000
+#define DDRSS2_PHY_163_DATA 0x00000000
+#define DDRSS2_PHY_164_DATA 0x00000000
+#define DDRSS2_PHY_165_DATA 0x00000000
+#define DDRSS2_PHY_166_DATA 0x00000000
+#define DDRSS2_PHY_167_DATA 0x00000000
+#define DDRSS2_PHY_168_DATA 0x00000000
+#define DDRSS2_PHY_169_DATA 0x00000000
+#define DDRSS2_PHY_170_DATA 0x00000000
+#define DDRSS2_PHY_171_DATA 0x00000000
+#define DDRSS2_PHY_172_DATA 0x00000000
+#define DDRSS2_PHY_173_DATA 0x00000000
+#define DDRSS2_PHY_174_DATA 0x00000000
+#define DDRSS2_PHY_175_DATA 0x00000000
+#define DDRSS2_PHY_176_DATA 0x00000000
+#define DDRSS2_PHY_177_DATA 0x00000000
+#define DDRSS2_PHY_178_DATA 0x00000000
+#define DDRSS2_PHY_179_DATA 0x00000000
+#define DDRSS2_PHY_180_DATA 0x00000000
+#define DDRSS2_PHY_181_DATA 0x00000000
+#define DDRSS2_PHY_182_DATA 0x00000000
+#define DDRSS2_PHY_183_DATA 0x00000000
+#define DDRSS2_PHY_184_DATA 0x00000000
+#define DDRSS2_PHY_185_DATA 0x00000000
+#define DDRSS2_PHY_186_DATA 0x00000000
+#define DDRSS2_PHY_187_DATA 0x00000000
+#define DDRSS2_PHY_188_DATA 0x00000000
+#define DDRSS2_PHY_189_DATA 0x00000000
+#define DDRSS2_PHY_190_DATA 0x00000000
+#define DDRSS2_PHY_191_DATA 0x00000000
+#define DDRSS2_PHY_192_DATA 0x00000000
+#define DDRSS2_PHY_193_DATA 0x00000000
+#define DDRSS2_PHY_194_DATA 0x00000000
+#define DDRSS2_PHY_195_DATA 0x00000000
+#define DDRSS2_PHY_196_DATA 0x00000000
+#define DDRSS2_PHY_197_DATA 0x00000000
+#define DDRSS2_PHY_198_DATA 0x00000000
+#define DDRSS2_PHY_199_DATA 0x00000000
+#define DDRSS2_PHY_200_DATA 0x00000000
+#define DDRSS2_PHY_201_DATA 0x00000000
+#define DDRSS2_PHY_202_DATA 0x00000000
+#define DDRSS2_PHY_203_DATA 0x00000000
+#define DDRSS2_PHY_204_DATA 0x00000000
+#define DDRSS2_PHY_205_DATA 0x00000000
+#define DDRSS2_PHY_206_DATA 0x00000000
+#define DDRSS2_PHY_207_DATA 0x00000000
+#define DDRSS2_PHY_208_DATA 0x00000000
+#define DDRSS2_PHY_209_DATA 0x00000000
+#define DDRSS2_PHY_210_DATA 0x00000000
+#define DDRSS2_PHY_211_DATA 0x00000000
+#define DDRSS2_PHY_212_DATA 0x00000000
+#define DDRSS2_PHY_213_DATA 0x00000000
+#define DDRSS2_PHY_214_DATA 0x00000000
+#define DDRSS2_PHY_215_DATA 0x00000000
+#define DDRSS2_PHY_216_DATA 0x00000000
+#define DDRSS2_PHY_217_DATA 0x00000000
+#define DDRSS2_PHY_218_DATA 0x00000000
+#define DDRSS2_PHY_219_DATA 0x00000000
+#define DDRSS2_PHY_220_DATA 0x00000000
+#define DDRSS2_PHY_221_DATA 0x00000000
+#define DDRSS2_PHY_222_DATA 0x00000000
+#define DDRSS2_PHY_223_DATA 0x00000000
+#define DDRSS2_PHY_224_DATA 0x00000000
+#define DDRSS2_PHY_225_DATA 0x00000000
+#define DDRSS2_PHY_226_DATA 0x00000000
+#define DDRSS2_PHY_227_DATA 0x00000000
+#define DDRSS2_PHY_228_DATA 0x00000000
+#define DDRSS2_PHY_229_DATA 0x00000000
+#define DDRSS2_PHY_230_DATA 0x00000000
+#define DDRSS2_PHY_231_DATA 0x00000000
+#define DDRSS2_PHY_232_DATA 0x00000000
+#define DDRSS2_PHY_233_DATA 0x00000000
+#define DDRSS2_PHY_234_DATA 0x00000000
+#define DDRSS2_PHY_235_DATA 0x00000000
+#define DDRSS2_PHY_236_DATA 0x00000000
+#define DDRSS2_PHY_237_DATA 0x00000000
+#define DDRSS2_PHY_238_DATA 0x00000000
+#define DDRSS2_PHY_239_DATA 0x00000000
+#define DDRSS2_PHY_240_DATA 0x00000000
+#define DDRSS2_PHY_241_DATA 0x00000000
+#define DDRSS2_PHY_242_DATA 0x00000000
+#define DDRSS2_PHY_243_DATA 0x00000000
+#define DDRSS2_PHY_244_DATA 0x00000000
+#define DDRSS2_PHY_245_DATA 0x00000000
+#define DDRSS2_PHY_246_DATA 0x00000000
+#define DDRSS2_PHY_247_DATA 0x00000000
+#define DDRSS2_PHY_248_DATA 0x00000000
+#define DDRSS2_PHY_249_DATA 0x00000000
+#define DDRSS2_PHY_250_DATA 0x00000000
+#define DDRSS2_PHY_251_DATA 0x00000000
+#define DDRSS2_PHY_252_DATA 0x00000000
+#define DDRSS2_PHY_253_DATA 0x00000000
+#define DDRSS2_PHY_254_DATA 0x00000000
+#define DDRSS2_PHY_255_DATA 0x00000000
+#define DDRSS2_PHY_256_DATA 0x000004F0
+#define DDRSS2_PHY_257_DATA 0x00000000
+#define DDRSS2_PHY_258_DATA 0x00030200
+#define DDRSS2_PHY_259_DATA 0x00000000
+#define DDRSS2_PHY_260_DATA 0x00000000
+#define DDRSS2_PHY_261_DATA 0x01030000
+#define DDRSS2_PHY_262_DATA 0x00010000
+#define DDRSS2_PHY_263_DATA 0x01030004
+#define DDRSS2_PHY_264_DATA 0x01000000
+#define DDRSS2_PHY_265_DATA 0x00000000
+#define DDRSS2_PHY_266_DATA 0x00000000
+#define DDRSS2_PHY_267_DATA 0x01000001
+#define DDRSS2_PHY_268_DATA 0x00000200
+#define DDRSS2_PHY_269_DATA 0x000800C0
+#define DDRSS2_PHY_270_DATA 0x060100CC
+#define DDRSS2_PHY_271_DATA 0x00030066
+#define DDRSS2_PHY_272_DATA 0x00000000
+#define DDRSS2_PHY_273_DATA 0x00000301
+#define DDRSS2_PHY_274_DATA 0x0000AAAA
+#define DDRSS2_PHY_275_DATA 0x00005555
+#define DDRSS2_PHY_276_DATA 0x0000B5B5
+#define DDRSS2_PHY_277_DATA 0x00004A4A
+#define DDRSS2_PHY_278_DATA 0x00005656
+#define DDRSS2_PHY_279_DATA 0x0000A9A9
+#define DDRSS2_PHY_280_DATA 0x0000A9A9
+#define DDRSS2_PHY_281_DATA 0x0000B5B5
+#define DDRSS2_PHY_282_DATA 0x00000000
+#define DDRSS2_PHY_283_DATA 0x00000000
+#define DDRSS2_PHY_284_DATA 0x2A000000
+#define DDRSS2_PHY_285_DATA 0x00000808
+#define DDRSS2_PHY_286_DATA 0x0F000000
+#define DDRSS2_PHY_287_DATA 0x00000F08
+#define DDRSS2_PHY_288_DATA 0x10400000
+#define DDRSS2_PHY_289_DATA 0x0C002006
+#define DDRSS2_PHY_290_DATA 0x00000000
+#define DDRSS2_PHY_291_DATA 0x00000000
+#define DDRSS2_PHY_292_DATA 0x55555555
+#define DDRSS2_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_294_DATA 0x55555555
+#define DDRSS2_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_296_DATA 0x00005555
+#define DDRSS2_PHY_297_DATA 0x01000100
+#define DDRSS2_PHY_298_DATA 0x00800180
+#define DDRSS2_PHY_299_DATA 0x00000000
+#define DDRSS2_PHY_300_DATA 0x00000000
+#define DDRSS2_PHY_301_DATA 0x00000000
+#define DDRSS2_PHY_302_DATA 0x00000000
+#define DDRSS2_PHY_303_DATA 0x00000000
+#define DDRSS2_PHY_304_DATA 0x00000000
+#define DDRSS2_PHY_305_DATA 0x00000000
+#define DDRSS2_PHY_306_DATA 0x00000000
+#define DDRSS2_PHY_307_DATA 0x00000000
+#define DDRSS2_PHY_308_DATA 0x00000000
+#define DDRSS2_PHY_309_DATA 0x00000000
+#define DDRSS2_PHY_310_DATA 0x00000000
+#define DDRSS2_PHY_311_DATA 0x00000000
+#define DDRSS2_PHY_312_DATA 0x00000000
+#define DDRSS2_PHY_313_DATA 0x00000000
+#define DDRSS2_PHY_314_DATA 0x00000000
+#define DDRSS2_PHY_315_DATA 0x00000000
+#define DDRSS2_PHY_316_DATA 0x00000000
+#define DDRSS2_PHY_317_DATA 0x00000000
+#define DDRSS2_PHY_318_DATA 0x00000000
+#define DDRSS2_PHY_319_DATA 0x00000000
+#define DDRSS2_PHY_320_DATA 0x00000000
+#define DDRSS2_PHY_321_DATA 0x00000000
+#define DDRSS2_PHY_322_DATA 0x00000104
+#define DDRSS2_PHY_323_DATA 0x00000120
+#define DDRSS2_PHY_324_DATA 0x00000000
+#define DDRSS2_PHY_325_DATA 0x00000000
+#define DDRSS2_PHY_326_DATA 0x00000000
+#define DDRSS2_PHY_327_DATA 0x00000000
+#define DDRSS2_PHY_328_DATA 0x00000000
+#define DDRSS2_PHY_329_DATA 0x00000000
+#define DDRSS2_PHY_330_DATA 0x00000000
+#define DDRSS2_PHY_331_DATA 0x00000001
+#define DDRSS2_PHY_332_DATA 0x07FF0000
+#define DDRSS2_PHY_333_DATA 0x0080081F
+#define DDRSS2_PHY_334_DATA 0x00081020
+#define DDRSS2_PHY_335_DATA 0x04010000
+#define DDRSS2_PHY_336_DATA 0x00000000
+#define DDRSS2_PHY_337_DATA 0x00000000
+#define DDRSS2_PHY_338_DATA 0x00000000
+#define DDRSS2_PHY_339_DATA 0x00000100
+#define DDRSS2_PHY_340_DATA 0x01CC0C01
+#define DDRSS2_PHY_341_DATA 0x1003CC0C
+#define DDRSS2_PHY_342_DATA 0x20000140
+#define DDRSS2_PHY_343_DATA 0x07FF0200
+#define DDRSS2_PHY_344_DATA 0x0000DD01
+#define DDRSS2_PHY_345_DATA 0x10100303
+#define DDRSS2_PHY_346_DATA 0x10101010
+#define DDRSS2_PHY_347_DATA 0x10101010
+#define DDRSS2_PHY_348_DATA 0x00021010
+#define DDRSS2_PHY_349_DATA 0x00100010
+#define DDRSS2_PHY_350_DATA 0x00100010
+#define DDRSS2_PHY_351_DATA 0x00100010
+#define DDRSS2_PHY_352_DATA 0x00100010
+#define DDRSS2_PHY_353_DATA 0x00050010
+#define DDRSS2_PHY_354_DATA 0x51517041
+#define DDRSS2_PHY_355_DATA 0x31C06001
+#define DDRSS2_PHY_356_DATA 0x07AB01AB
+#define DDRSS2_PHY_357_DATA 0x00C0C001
+#define DDRSS2_PHY_358_DATA 0x0E0D0101
+#define DDRSS2_PHY_359_DATA 0x10001000
+#define DDRSS2_PHY_360_DATA 0x0C083E42
+#define DDRSS2_PHY_361_DATA 0x0F0C3701
+#define DDRSS2_PHY_362_DATA 0x01000140
+#define DDRSS2_PHY_363_DATA 0x0C000420
+#define DDRSS2_PHY_364_DATA 0x00000198
+#define DDRSS2_PHY_365_DATA 0x0A0000D0
+#define DDRSS2_PHY_366_DATA 0x00030200
+#define DDRSS2_PHY_367_DATA 0x02800000
+#define DDRSS2_PHY_368_DATA 0x80800000
+#define DDRSS2_PHY_369_DATA 0x000E2010
+#define DDRSS2_PHY_370_DATA 0x76543210
+#define DDRSS2_PHY_371_DATA 0x00000008
+#define DDRSS2_PHY_372_DATA 0x02800280
+#define DDRSS2_PHY_373_DATA 0x02800280
+#define DDRSS2_PHY_374_DATA 0x02800280
+#define DDRSS2_PHY_375_DATA 0x02800280
+#define DDRSS2_PHY_376_DATA 0x00000280
+#define DDRSS2_PHY_377_DATA 0x0000A000
+#define DDRSS2_PHY_378_DATA 0x00A000A0
+#define DDRSS2_PHY_379_DATA 0x00A000A0
+#define DDRSS2_PHY_380_DATA 0x00A000A0
+#define DDRSS2_PHY_381_DATA 0x00A000A0
+#define DDRSS2_PHY_382_DATA 0x00A000A0
+#define DDRSS2_PHY_383_DATA 0x00A000A0
+#define DDRSS2_PHY_384_DATA 0x00A000A0
+#define DDRSS2_PHY_385_DATA 0x00A000A0
+#define DDRSS2_PHY_386_DATA 0x01C200A0
+#define DDRSS2_PHY_387_DATA 0x01A00005
+#define DDRSS2_PHY_388_DATA 0x00000000
+#define DDRSS2_PHY_389_DATA 0x00000000
+#define DDRSS2_PHY_390_DATA 0x00080200
+#define DDRSS2_PHY_391_DATA 0x00000000
+#define DDRSS2_PHY_392_DATA 0x20202000
+#define DDRSS2_PHY_393_DATA 0x20202020
+#define DDRSS2_PHY_394_DATA 0xF0F02020
+#define DDRSS2_PHY_395_DATA 0x00000000
+#define DDRSS2_PHY_396_DATA 0x00000000
+#define DDRSS2_PHY_397_DATA 0x00000000
+#define DDRSS2_PHY_398_DATA 0x00000000
+#define DDRSS2_PHY_399_DATA 0x00000000
+#define DDRSS2_PHY_400_DATA 0x00000000
+#define DDRSS2_PHY_401_DATA 0x00000000
+#define DDRSS2_PHY_402_DATA 0x00000000
+#define DDRSS2_PHY_403_DATA 0x00000000
+#define DDRSS2_PHY_404_DATA 0x00000000
+#define DDRSS2_PHY_405_DATA 0x00000000
+#define DDRSS2_PHY_406_DATA 0x00000000
+#define DDRSS2_PHY_407_DATA 0x00000000
+#define DDRSS2_PHY_408_DATA 0x00000000
+#define DDRSS2_PHY_409_DATA 0x00000000
+#define DDRSS2_PHY_410_DATA 0x00000000
+#define DDRSS2_PHY_411_DATA 0x00000000
+#define DDRSS2_PHY_412_DATA 0x00000000
+#define DDRSS2_PHY_413_DATA 0x00000000
+#define DDRSS2_PHY_414_DATA 0x00000000
+#define DDRSS2_PHY_415_DATA 0x00000000
+#define DDRSS2_PHY_416_DATA 0x00000000
+#define DDRSS2_PHY_417_DATA 0x00000000
+#define DDRSS2_PHY_418_DATA 0x00000000
+#define DDRSS2_PHY_419_DATA 0x00000000
+#define DDRSS2_PHY_420_DATA 0x00000000
+#define DDRSS2_PHY_421_DATA 0x00000000
+#define DDRSS2_PHY_422_DATA 0x00000000
+#define DDRSS2_PHY_423_DATA 0x00000000
+#define DDRSS2_PHY_424_DATA 0x00000000
+#define DDRSS2_PHY_425_DATA 0x00000000
+#define DDRSS2_PHY_426_DATA 0x00000000
+#define DDRSS2_PHY_427_DATA 0x00000000
+#define DDRSS2_PHY_428_DATA 0x00000000
+#define DDRSS2_PHY_429_DATA 0x00000000
+#define DDRSS2_PHY_430_DATA 0x00000000
+#define DDRSS2_PHY_431_DATA 0x00000000
+#define DDRSS2_PHY_432_DATA 0x00000000
+#define DDRSS2_PHY_433_DATA 0x00000000
+#define DDRSS2_PHY_434_DATA 0x00000000
+#define DDRSS2_PHY_435_DATA 0x00000000
+#define DDRSS2_PHY_436_DATA 0x00000000
+#define DDRSS2_PHY_437_DATA 0x00000000
+#define DDRSS2_PHY_438_DATA 0x00000000
+#define DDRSS2_PHY_439_DATA 0x00000000
+#define DDRSS2_PHY_440_DATA 0x00000000
+#define DDRSS2_PHY_441_DATA 0x00000000
+#define DDRSS2_PHY_442_DATA 0x00000000
+#define DDRSS2_PHY_443_DATA 0x00000000
+#define DDRSS2_PHY_444_DATA 0x00000000
+#define DDRSS2_PHY_445_DATA 0x00000000
+#define DDRSS2_PHY_446_DATA 0x00000000
+#define DDRSS2_PHY_447_DATA 0x00000000
+#define DDRSS2_PHY_448_DATA 0x00000000
+#define DDRSS2_PHY_449_DATA 0x00000000
+#define DDRSS2_PHY_450_DATA 0x00000000
+#define DDRSS2_PHY_451_DATA 0x00000000
+#define DDRSS2_PHY_452_DATA 0x00000000
+#define DDRSS2_PHY_453_DATA 0x00000000
+#define DDRSS2_PHY_454_DATA 0x00000000
+#define DDRSS2_PHY_455_DATA 0x00000000
+#define DDRSS2_PHY_456_DATA 0x00000000
+#define DDRSS2_PHY_457_DATA 0x00000000
+#define DDRSS2_PHY_458_DATA 0x00000000
+#define DDRSS2_PHY_459_DATA 0x00000000
+#define DDRSS2_PHY_460_DATA 0x00000000
+#define DDRSS2_PHY_461_DATA 0x00000000
+#define DDRSS2_PHY_462_DATA 0x00000000
+#define DDRSS2_PHY_463_DATA 0x00000000
+#define DDRSS2_PHY_464_DATA 0x00000000
+#define DDRSS2_PHY_465_DATA 0x00000000
+#define DDRSS2_PHY_466_DATA 0x00000000
+#define DDRSS2_PHY_467_DATA 0x00000000
+#define DDRSS2_PHY_468_DATA 0x00000000
+#define DDRSS2_PHY_469_DATA 0x00000000
+#define DDRSS2_PHY_470_DATA 0x00000000
+#define DDRSS2_PHY_471_DATA 0x00000000
+#define DDRSS2_PHY_472_DATA 0x00000000
+#define DDRSS2_PHY_473_DATA 0x00000000
+#define DDRSS2_PHY_474_DATA 0x00000000
+#define DDRSS2_PHY_475_DATA 0x00000000
+#define DDRSS2_PHY_476_DATA 0x00000000
+#define DDRSS2_PHY_477_DATA 0x00000000
+#define DDRSS2_PHY_478_DATA 0x00000000
+#define DDRSS2_PHY_479_DATA 0x00000000
+#define DDRSS2_PHY_480_DATA 0x00000000
+#define DDRSS2_PHY_481_DATA 0x00000000
+#define DDRSS2_PHY_482_DATA 0x00000000
+#define DDRSS2_PHY_483_DATA 0x00000000
+#define DDRSS2_PHY_484_DATA 0x00000000
+#define DDRSS2_PHY_485_DATA 0x00000000
+#define DDRSS2_PHY_486_DATA 0x00000000
+#define DDRSS2_PHY_487_DATA 0x00000000
+#define DDRSS2_PHY_488_DATA 0x00000000
+#define DDRSS2_PHY_489_DATA 0x00000000
+#define DDRSS2_PHY_490_DATA 0x00000000
+#define DDRSS2_PHY_491_DATA 0x00000000
+#define DDRSS2_PHY_492_DATA 0x00000000
+#define DDRSS2_PHY_493_DATA 0x00000000
+#define DDRSS2_PHY_494_DATA 0x00000000
+#define DDRSS2_PHY_495_DATA 0x00000000
+#define DDRSS2_PHY_496_DATA 0x00000000
+#define DDRSS2_PHY_497_DATA 0x00000000
+#define DDRSS2_PHY_498_DATA 0x00000000
+#define DDRSS2_PHY_499_DATA 0x00000000
+#define DDRSS2_PHY_500_DATA 0x00000000
+#define DDRSS2_PHY_501_DATA 0x00000000
+#define DDRSS2_PHY_502_DATA 0x00000000
+#define DDRSS2_PHY_503_DATA 0x00000000
+#define DDRSS2_PHY_504_DATA 0x00000000
+#define DDRSS2_PHY_505_DATA 0x00000000
+#define DDRSS2_PHY_506_DATA 0x00000000
+#define DDRSS2_PHY_507_DATA 0x00000000
+#define DDRSS2_PHY_508_DATA 0x00000000
+#define DDRSS2_PHY_509_DATA 0x00000000
+#define DDRSS2_PHY_510_DATA 0x00000000
+#define DDRSS2_PHY_511_DATA 0x00000000
+#define DDRSS2_PHY_512_DATA 0x000004F0
+#define DDRSS2_PHY_513_DATA 0x00000000
+#define DDRSS2_PHY_514_DATA 0x00030200
+#define DDRSS2_PHY_515_DATA 0x00000000
+#define DDRSS2_PHY_516_DATA 0x00000000
+#define DDRSS2_PHY_517_DATA 0x01030000
+#define DDRSS2_PHY_518_DATA 0x00010000
+#define DDRSS2_PHY_519_DATA 0x01030004
+#define DDRSS2_PHY_520_DATA 0x01000000
+#define DDRSS2_PHY_521_DATA 0x00000000
+#define DDRSS2_PHY_522_DATA 0x00000000
+#define DDRSS2_PHY_523_DATA 0x01000001
+#define DDRSS2_PHY_524_DATA 0x00000200
+#define DDRSS2_PHY_525_DATA 0x000800C0
+#define DDRSS2_PHY_526_DATA 0x060100CC
+#define DDRSS2_PHY_527_DATA 0x00030066
+#define DDRSS2_PHY_528_DATA 0x00000000
+#define DDRSS2_PHY_529_DATA 0x00000301
+#define DDRSS2_PHY_530_DATA 0x0000AAAA
+#define DDRSS2_PHY_531_DATA 0x00005555
+#define DDRSS2_PHY_532_DATA 0x0000B5B5
+#define DDRSS2_PHY_533_DATA 0x00004A4A
+#define DDRSS2_PHY_534_DATA 0x00005656
+#define DDRSS2_PHY_535_DATA 0x0000A9A9
+#define DDRSS2_PHY_536_DATA 0x0000A9A9
+#define DDRSS2_PHY_537_DATA 0x0000B5B5
+#define DDRSS2_PHY_538_DATA 0x00000000
+#define DDRSS2_PHY_539_DATA 0x00000000
+#define DDRSS2_PHY_540_DATA 0x2A000000
+#define DDRSS2_PHY_541_DATA 0x00000808
+#define DDRSS2_PHY_542_DATA 0x0F000000
+#define DDRSS2_PHY_543_DATA 0x00000F08
+#define DDRSS2_PHY_544_DATA 0x10400000
+#define DDRSS2_PHY_545_DATA 0x0C002006
+#define DDRSS2_PHY_546_DATA 0x00000000
+#define DDRSS2_PHY_547_DATA 0x00000000
+#define DDRSS2_PHY_548_DATA 0x55555555
+#define DDRSS2_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_550_DATA 0x55555555
+#define DDRSS2_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_552_DATA 0x00005555
+#define DDRSS2_PHY_553_DATA 0x01000100
+#define DDRSS2_PHY_554_DATA 0x00800180
+#define DDRSS2_PHY_555_DATA 0x00000001
+#define DDRSS2_PHY_556_DATA 0x00000000
+#define DDRSS2_PHY_557_DATA 0x00000000
+#define DDRSS2_PHY_558_DATA 0x00000000
+#define DDRSS2_PHY_559_DATA 0x00000000
+#define DDRSS2_PHY_560_DATA 0x00000000
+#define DDRSS2_PHY_561_DATA 0x00000000
+#define DDRSS2_PHY_562_DATA 0x00000000
+#define DDRSS2_PHY_563_DATA 0x00000000
+#define DDRSS2_PHY_564_DATA 0x00000000
+#define DDRSS2_PHY_565_DATA 0x00000000
+#define DDRSS2_PHY_566_DATA 0x00000000
+#define DDRSS2_PHY_567_DATA 0x00000000
+#define DDRSS2_PHY_568_DATA 0x00000000
+#define DDRSS2_PHY_569_DATA 0x00000000
+#define DDRSS2_PHY_570_DATA 0x00000000
+#define DDRSS2_PHY_571_DATA 0x00000000
+#define DDRSS2_PHY_572_DATA 0x00000000
+#define DDRSS2_PHY_573_DATA 0x00000000
+#define DDRSS2_PHY_574_DATA 0x00000000
+#define DDRSS2_PHY_575_DATA 0x00000000
+#define DDRSS2_PHY_576_DATA 0x00000000
+#define DDRSS2_PHY_577_DATA 0x00000000
+#define DDRSS2_PHY_578_DATA 0x00000104
+#define DDRSS2_PHY_579_DATA 0x00000120
+#define DDRSS2_PHY_580_DATA 0x00000000
+#define DDRSS2_PHY_581_DATA 0x00000000
+#define DDRSS2_PHY_582_DATA 0x00000000
+#define DDRSS2_PHY_583_DATA 0x00000000
+#define DDRSS2_PHY_584_DATA 0x00000000
+#define DDRSS2_PHY_585_DATA 0x00000000
+#define DDRSS2_PHY_586_DATA 0x00000000
+#define DDRSS2_PHY_587_DATA 0x00000001
+#define DDRSS2_PHY_588_DATA 0x07FF0000
+#define DDRSS2_PHY_589_DATA 0x0080081F
+#define DDRSS2_PHY_590_DATA 0x00081020
+#define DDRSS2_PHY_591_DATA 0x04010000
+#define DDRSS2_PHY_592_DATA 0x00000000
+#define DDRSS2_PHY_593_DATA 0x00000000
+#define DDRSS2_PHY_594_DATA 0x00000000
+#define DDRSS2_PHY_595_DATA 0x00000100
+#define DDRSS2_PHY_596_DATA 0x01CC0C01
+#define DDRSS2_PHY_597_DATA 0x1003CC0C
+#define DDRSS2_PHY_598_DATA 0x20000140
+#define DDRSS2_PHY_599_DATA 0x07FF0200
+#define DDRSS2_PHY_600_DATA 0x0000DD01
+#define DDRSS2_PHY_601_DATA 0x10100303
+#define DDRSS2_PHY_602_DATA 0x10101010
+#define DDRSS2_PHY_603_DATA 0x10101010
+#define DDRSS2_PHY_604_DATA 0x00021010
+#define DDRSS2_PHY_605_DATA 0x00100010
+#define DDRSS2_PHY_606_DATA 0x00100010
+#define DDRSS2_PHY_607_DATA 0x00100010
+#define DDRSS2_PHY_608_DATA 0x00100010
+#define DDRSS2_PHY_609_DATA 0x00050010
+#define DDRSS2_PHY_610_DATA 0x51517041
+#define DDRSS2_PHY_611_DATA 0x31C06001
+#define DDRSS2_PHY_612_DATA 0x07AB01AB
+#define DDRSS2_PHY_613_DATA 0x00C0C001
+#define DDRSS2_PHY_614_DATA 0x0E0D0101
+#define DDRSS2_PHY_615_DATA 0x10001000
+#define DDRSS2_PHY_616_DATA 0x0C083E42
+#define DDRSS2_PHY_617_DATA 0x0F0C3701
+#define DDRSS2_PHY_618_DATA 0x01000140
+#define DDRSS2_PHY_619_DATA 0x0C000420
+#define DDRSS2_PHY_620_DATA 0x00000198
+#define DDRSS2_PHY_621_DATA 0x0A0000D0
+#define DDRSS2_PHY_622_DATA 0x00030200
+#define DDRSS2_PHY_623_DATA 0x02800000
+#define DDRSS2_PHY_624_DATA 0x80800000
+#define DDRSS2_PHY_625_DATA 0x000E2010
+#define DDRSS2_PHY_626_DATA 0x76543210
+#define DDRSS2_PHY_627_DATA 0x00000008
+#define DDRSS2_PHY_628_DATA 0x02800280
+#define DDRSS2_PHY_629_DATA 0x02800280
+#define DDRSS2_PHY_630_DATA 0x02800280
+#define DDRSS2_PHY_631_DATA 0x02800280
+#define DDRSS2_PHY_632_DATA 0x00000280
+#define DDRSS2_PHY_633_DATA 0x0000A000
+#define DDRSS2_PHY_634_DATA 0x00A000A0
+#define DDRSS2_PHY_635_DATA 0x00A000A0
+#define DDRSS2_PHY_636_DATA 0x00A000A0
+#define DDRSS2_PHY_637_DATA 0x00A000A0
+#define DDRSS2_PHY_638_DATA 0x00A000A0
+#define DDRSS2_PHY_639_DATA 0x00A000A0
+#define DDRSS2_PHY_640_DATA 0x00A000A0
+#define DDRSS2_PHY_641_DATA 0x00A000A0
+#define DDRSS2_PHY_642_DATA 0x01C200A0
+#define DDRSS2_PHY_643_DATA 0x01A00005
+#define DDRSS2_PHY_644_DATA 0x00000000
+#define DDRSS2_PHY_645_DATA 0x00000000
+#define DDRSS2_PHY_646_DATA 0x00080200
+#define DDRSS2_PHY_647_DATA 0x00000000
+#define DDRSS2_PHY_648_DATA 0x20202000
+#define DDRSS2_PHY_649_DATA 0x20202020
+#define DDRSS2_PHY_650_DATA 0xF0F02020
+#define DDRSS2_PHY_651_DATA 0x00000000
+#define DDRSS2_PHY_652_DATA 0x00000000
+#define DDRSS2_PHY_653_DATA 0x00000000
+#define DDRSS2_PHY_654_DATA 0x00000000
+#define DDRSS2_PHY_655_DATA 0x00000000
+#define DDRSS2_PHY_656_DATA 0x00000000
+#define DDRSS2_PHY_657_DATA 0x00000000
+#define DDRSS2_PHY_658_DATA 0x00000000
+#define DDRSS2_PHY_659_DATA 0x00000000
+#define DDRSS2_PHY_660_DATA 0x00000000
+#define DDRSS2_PHY_661_DATA 0x00000000
+#define DDRSS2_PHY_662_DATA 0x00000000
+#define DDRSS2_PHY_663_DATA 0x00000000
+#define DDRSS2_PHY_664_DATA 0x00000000
+#define DDRSS2_PHY_665_DATA 0x00000000
+#define DDRSS2_PHY_666_DATA 0x00000000
+#define DDRSS2_PHY_667_DATA 0x00000000
+#define DDRSS2_PHY_668_DATA 0x00000000
+#define DDRSS2_PHY_669_DATA 0x00000000
+#define DDRSS2_PHY_670_DATA 0x00000000
+#define DDRSS2_PHY_671_DATA 0x00000000
+#define DDRSS2_PHY_672_DATA 0x00000000
+#define DDRSS2_PHY_673_DATA 0x00000000
+#define DDRSS2_PHY_674_DATA 0x00000000
+#define DDRSS2_PHY_675_DATA 0x00000000
+#define DDRSS2_PHY_676_DATA 0x00000000
+#define DDRSS2_PHY_677_DATA 0x00000000
+#define DDRSS2_PHY_678_DATA 0x00000000
+#define DDRSS2_PHY_679_DATA 0x00000000
+#define DDRSS2_PHY_680_DATA 0x00000000
+#define DDRSS2_PHY_681_DATA 0x00000000
+#define DDRSS2_PHY_682_DATA 0x00000000
+#define DDRSS2_PHY_683_DATA 0x00000000
+#define DDRSS2_PHY_684_DATA 0x00000000
+#define DDRSS2_PHY_685_DATA 0x00000000
+#define DDRSS2_PHY_686_DATA 0x00000000
+#define DDRSS2_PHY_687_DATA 0x00000000
+#define DDRSS2_PHY_688_DATA 0x00000000
+#define DDRSS2_PHY_689_DATA 0x00000000
+#define DDRSS2_PHY_690_DATA 0x00000000
+#define DDRSS2_PHY_691_DATA 0x00000000
+#define DDRSS2_PHY_692_DATA 0x00000000
+#define DDRSS2_PHY_693_DATA 0x00000000
+#define DDRSS2_PHY_694_DATA 0x00000000
+#define DDRSS2_PHY_695_DATA 0x00000000
+#define DDRSS2_PHY_696_DATA 0x00000000
+#define DDRSS2_PHY_697_DATA 0x00000000
+#define DDRSS2_PHY_698_DATA 0x00000000
+#define DDRSS2_PHY_699_DATA 0x00000000
+#define DDRSS2_PHY_700_DATA 0x00000000
+#define DDRSS2_PHY_701_DATA 0x00000000
+#define DDRSS2_PHY_702_DATA 0x00000000
+#define DDRSS2_PHY_703_DATA 0x00000000
+#define DDRSS2_PHY_704_DATA 0x00000000
+#define DDRSS2_PHY_705_DATA 0x00000000
+#define DDRSS2_PHY_706_DATA 0x00000000
+#define DDRSS2_PHY_707_DATA 0x00000000
+#define DDRSS2_PHY_708_DATA 0x00000000
+#define DDRSS2_PHY_709_DATA 0x00000000
+#define DDRSS2_PHY_710_DATA 0x00000000
+#define DDRSS2_PHY_711_DATA 0x00000000
+#define DDRSS2_PHY_712_DATA 0x00000000
+#define DDRSS2_PHY_713_DATA 0x00000000
+#define DDRSS2_PHY_714_DATA 0x00000000
+#define DDRSS2_PHY_715_DATA 0x00000000
+#define DDRSS2_PHY_716_DATA 0x00000000
+#define DDRSS2_PHY_717_DATA 0x00000000
+#define DDRSS2_PHY_718_DATA 0x00000000
+#define DDRSS2_PHY_719_DATA 0x00000000
+#define DDRSS2_PHY_720_DATA 0x00000000
+#define DDRSS2_PHY_721_DATA 0x00000000
+#define DDRSS2_PHY_722_DATA 0x00000000
+#define DDRSS2_PHY_723_DATA 0x00000000
+#define DDRSS2_PHY_724_DATA 0x00000000
+#define DDRSS2_PHY_725_DATA 0x00000000
+#define DDRSS2_PHY_726_DATA 0x00000000
+#define DDRSS2_PHY_727_DATA 0x00000000
+#define DDRSS2_PHY_728_DATA 0x00000000
+#define DDRSS2_PHY_729_DATA 0x00000000
+#define DDRSS2_PHY_730_DATA 0x00000000
+#define DDRSS2_PHY_731_DATA 0x00000000
+#define DDRSS2_PHY_732_DATA 0x00000000
+#define DDRSS2_PHY_733_DATA 0x00000000
+#define DDRSS2_PHY_734_DATA 0x00000000
+#define DDRSS2_PHY_735_DATA 0x00000000
+#define DDRSS2_PHY_736_DATA 0x00000000
+#define DDRSS2_PHY_737_DATA 0x00000000
+#define DDRSS2_PHY_738_DATA 0x00000000
+#define DDRSS2_PHY_739_DATA 0x00000000
+#define DDRSS2_PHY_740_DATA 0x00000000
+#define DDRSS2_PHY_741_DATA 0x00000000
+#define DDRSS2_PHY_742_DATA 0x00000000
+#define DDRSS2_PHY_743_DATA 0x00000000
+#define DDRSS2_PHY_744_DATA 0x00000000
+#define DDRSS2_PHY_745_DATA 0x00000000
+#define DDRSS2_PHY_746_DATA 0x00000000
+#define DDRSS2_PHY_747_DATA 0x00000000
+#define DDRSS2_PHY_748_DATA 0x00000000
+#define DDRSS2_PHY_749_DATA 0x00000000
+#define DDRSS2_PHY_750_DATA 0x00000000
+#define DDRSS2_PHY_751_DATA 0x00000000
+#define DDRSS2_PHY_752_DATA 0x00000000
+#define DDRSS2_PHY_753_DATA 0x00000000
+#define DDRSS2_PHY_754_DATA 0x00000000
+#define DDRSS2_PHY_755_DATA 0x00000000
+#define DDRSS2_PHY_756_DATA 0x00000000
+#define DDRSS2_PHY_757_DATA 0x00000000
+#define DDRSS2_PHY_758_DATA 0x00000000
+#define DDRSS2_PHY_759_DATA 0x00000000
+#define DDRSS2_PHY_760_DATA 0x00000000
+#define DDRSS2_PHY_761_DATA 0x00000000
+#define DDRSS2_PHY_762_DATA 0x00000000
+#define DDRSS2_PHY_763_DATA 0x00000000
+#define DDRSS2_PHY_764_DATA 0x00000000
+#define DDRSS2_PHY_765_DATA 0x00000000
+#define DDRSS2_PHY_766_DATA 0x00000000
+#define DDRSS2_PHY_767_DATA 0x00000000
+#define DDRSS2_PHY_768_DATA 0x000004F0
+#define DDRSS2_PHY_769_DATA 0x00000000
+#define DDRSS2_PHY_770_DATA 0x00030200
+#define DDRSS2_PHY_771_DATA 0x00000000
+#define DDRSS2_PHY_772_DATA 0x00000000
+#define DDRSS2_PHY_773_DATA 0x01030000
+#define DDRSS2_PHY_774_DATA 0x00010000
+#define DDRSS2_PHY_775_DATA 0x01030004
+#define DDRSS2_PHY_776_DATA 0x01000000
+#define DDRSS2_PHY_777_DATA 0x00000000
+#define DDRSS2_PHY_778_DATA 0x00000000
+#define DDRSS2_PHY_779_DATA 0x01000001
+#define DDRSS2_PHY_780_DATA 0x00000200
+#define DDRSS2_PHY_781_DATA 0x000800C0
+#define DDRSS2_PHY_782_DATA 0x060100CC
+#define DDRSS2_PHY_783_DATA 0x00030066
+#define DDRSS2_PHY_784_DATA 0x00000000
+#define DDRSS2_PHY_785_DATA 0x00000301
+#define DDRSS2_PHY_786_DATA 0x0000AAAA
+#define DDRSS2_PHY_787_DATA 0x00005555
+#define DDRSS2_PHY_788_DATA 0x0000B5B5
+#define DDRSS2_PHY_789_DATA 0x00004A4A
+#define DDRSS2_PHY_790_DATA 0x00005656
+#define DDRSS2_PHY_791_DATA 0x0000A9A9
+#define DDRSS2_PHY_792_DATA 0x0000A9A9
+#define DDRSS2_PHY_793_DATA 0x0000B5B5
+#define DDRSS2_PHY_794_DATA 0x00000000
+#define DDRSS2_PHY_795_DATA 0x00000000
+#define DDRSS2_PHY_796_DATA 0x2A000000
+#define DDRSS2_PHY_797_DATA 0x00000808
+#define DDRSS2_PHY_798_DATA 0x0F000000
+#define DDRSS2_PHY_799_DATA 0x00000F08
+#define DDRSS2_PHY_800_DATA 0x10400000
+#define DDRSS2_PHY_801_DATA 0x0C002006
+#define DDRSS2_PHY_802_DATA 0x00000000
+#define DDRSS2_PHY_803_DATA 0x00000000
+#define DDRSS2_PHY_804_DATA 0x55555555
+#define DDRSS2_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_806_DATA 0x55555555
+#define DDRSS2_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_808_DATA 0x00005555
+#define DDRSS2_PHY_809_DATA 0x01000100
+#define DDRSS2_PHY_810_DATA 0x00800180
+#define DDRSS2_PHY_811_DATA 0x00000000
+#define DDRSS2_PHY_812_DATA 0x00000000
+#define DDRSS2_PHY_813_DATA 0x00000000
+#define DDRSS2_PHY_814_DATA 0x00000000
+#define DDRSS2_PHY_815_DATA 0x00000000
+#define DDRSS2_PHY_816_DATA 0x00000000
+#define DDRSS2_PHY_817_DATA 0x00000000
+#define DDRSS2_PHY_818_DATA 0x00000000
+#define DDRSS2_PHY_819_DATA 0x00000000
+#define DDRSS2_PHY_820_DATA 0x00000000
+#define DDRSS2_PHY_821_DATA 0x00000000
+#define DDRSS2_PHY_822_DATA 0x00000000
+#define DDRSS2_PHY_823_DATA 0x00000000
+#define DDRSS2_PHY_824_DATA 0x00000000
+#define DDRSS2_PHY_825_DATA 0x00000000
+#define DDRSS2_PHY_826_DATA 0x00000000
+#define DDRSS2_PHY_827_DATA 0x00000000
+#define DDRSS2_PHY_828_DATA 0x00000000
+#define DDRSS2_PHY_829_DATA 0x00000000
+#define DDRSS2_PHY_830_DATA 0x00000000
+#define DDRSS2_PHY_831_DATA 0x00000000
+#define DDRSS2_PHY_832_DATA 0x00000000
+#define DDRSS2_PHY_833_DATA 0x00000000
+#define DDRSS2_PHY_834_DATA 0x00000104
+#define DDRSS2_PHY_835_DATA 0x00000120
+#define DDRSS2_PHY_836_DATA 0x00000000
+#define DDRSS2_PHY_837_DATA 0x00000000
+#define DDRSS2_PHY_838_DATA 0x00000000
+#define DDRSS2_PHY_839_DATA 0x00000000
+#define DDRSS2_PHY_840_DATA 0x00000000
+#define DDRSS2_PHY_841_DATA 0x00000000
+#define DDRSS2_PHY_842_DATA 0x00000000
+#define DDRSS2_PHY_843_DATA 0x00000001
+#define DDRSS2_PHY_844_DATA 0x07FF0000
+#define DDRSS2_PHY_845_DATA 0x0080081F
+#define DDRSS2_PHY_846_DATA 0x00081020
+#define DDRSS2_PHY_847_DATA 0x04010000
+#define DDRSS2_PHY_848_DATA 0x00000000
+#define DDRSS2_PHY_849_DATA 0x00000000
+#define DDRSS2_PHY_850_DATA 0x00000000
+#define DDRSS2_PHY_851_DATA 0x00000100
+#define DDRSS2_PHY_852_DATA 0x01CC0C01
+#define DDRSS2_PHY_853_DATA 0x1003CC0C
+#define DDRSS2_PHY_854_DATA 0x20000140
+#define DDRSS2_PHY_855_DATA 0x07FF0200
+#define DDRSS2_PHY_856_DATA 0x0000DD01
+#define DDRSS2_PHY_857_DATA 0x10100303
+#define DDRSS2_PHY_858_DATA 0x10101010
+#define DDRSS2_PHY_859_DATA 0x10101010
+#define DDRSS2_PHY_860_DATA 0x00021010
+#define DDRSS2_PHY_861_DATA 0x00100010
+#define DDRSS2_PHY_862_DATA 0x00100010
+#define DDRSS2_PHY_863_DATA 0x00100010
+#define DDRSS2_PHY_864_DATA 0x00100010
+#define DDRSS2_PHY_865_DATA 0x00050010
+#define DDRSS2_PHY_866_DATA 0x51517041
+#define DDRSS2_PHY_867_DATA 0x31C06001
+#define DDRSS2_PHY_868_DATA 0x07AB01AB
+#define DDRSS2_PHY_869_DATA 0x00C0C001
+#define DDRSS2_PHY_870_DATA 0x0E0D0101
+#define DDRSS2_PHY_871_DATA 0x10001000
+#define DDRSS2_PHY_872_DATA 0x0C083E42
+#define DDRSS2_PHY_873_DATA 0x0F0C3701
+#define DDRSS2_PHY_874_DATA 0x01000140
+#define DDRSS2_PHY_875_DATA 0x0C000420
+#define DDRSS2_PHY_876_DATA 0x00000198
+#define DDRSS2_PHY_877_DATA 0x0A0000D0
+#define DDRSS2_PHY_878_DATA 0x00030200
+#define DDRSS2_PHY_879_DATA 0x02800000
+#define DDRSS2_PHY_880_DATA 0x80800000
+#define DDRSS2_PHY_881_DATA 0x000E2010
+#define DDRSS2_PHY_882_DATA 0x76543210
+#define DDRSS2_PHY_883_DATA 0x00000008
+#define DDRSS2_PHY_884_DATA 0x02800280
+#define DDRSS2_PHY_885_DATA 0x02800280
+#define DDRSS2_PHY_886_DATA 0x02800280
+#define DDRSS2_PHY_887_DATA 0x02800280
+#define DDRSS2_PHY_888_DATA 0x00000280
+#define DDRSS2_PHY_889_DATA 0x0000A000
+#define DDRSS2_PHY_890_DATA 0x00A000A0
+#define DDRSS2_PHY_891_DATA 0x00A000A0
+#define DDRSS2_PHY_892_DATA 0x00A000A0
+#define DDRSS2_PHY_893_DATA 0x00A000A0
+#define DDRSS2_PHY_894_DATA 0x00A000A0
+#define DDRSS2_PHY_895_DATA 0x00A000A0
+#define DDRSS2_PHY_896_DATA 0x00A000A0
+#define DDRSS2_PHY_897_DATA 0x00A000A0
+#define DDRSS2_PHY_898_DATA 0x01C200A0
+#define DDRSS2_PHY_899_DATA 0x01A00005
+#define DDRSS2_PHY_900_DATA 0x00000000
+#define DDRSS2_PHY_901_DATA 0x00000000
+#define DDRSS2_PHY_902_DATA 0x00080200
+#define DDRSS2_PHY_903_DATA 0x00000000
+#define DDRSS2_PHY_904_DATA 0x20202000
+#define DDRSS2_PHY_905_DATA 0x20202020
+#define DDRSS2_PHY_906_DATA 0xF0F02020
+#define DDRSS2_PHY_907_DATA 0x00000000
+#define DDRSS2_PHY_908_DATA 0x00000000
+#define DDRSS2_PHY_909_DATA 0x00000000
+#define DDRSS2_PHY_910_DATA 0x00000000
+#define DDRSS2_PHY_911_DATA 0x00000000
+#define DDRSS2_PHY_912_DATA 0x00000000
+#define DDRSS2_PHY_913_DATA 0x00000000
+#define DDRSS2_PHY_914_DATA 0x00000000
+#define DDRSS2_PHY_915_DATA 0x00000000
+#define DDRSS2_PHY_916_DATA 0x00000000
+#define DDRSS2_PHY_917_DATA 0x00000000
+#define DDRSS2_PHY_918_DATA 0x00000000
+#define DDRSS2_PHY_919_DATA 0x00000000
+#define DDRSS2_PHY_920_DATA 0x00000000
+#define DDRSS2_PHY_921_DATA 0x00000000
+#define DDRSS2_PHY_922_DATA 0x00000000
+#define DDRSS2_PHY_923_DATA 0x00000000
+#define DDRSS2_PHY_924_DATA 0x00000000
+#define DDRSS2_PHY_925_DATA 0x00000000
+#define DDRSS2_PHY_926_DATA 0x00000000
+#define DDRSS2_PHY_927_DATA 0x00000000
+#define DDRSS2_PHY_928_DATA 0x00000000
+#define DDRSS2_PHY_929_DATA 0x00000000
+#define DDRSS2_PHY_930_DATA 0x00000000
+#define DDRSS2_PHY_931_DATA 0x00000000
+#define DDRSS2_PHY_932_DATA 0x00000000
+#define DDRSS2_PHY_933_DATA 0x00000000
+#define DDRSS2_PHY_934_DATA 0x00000000
+#define DDRSS2_PHY_935_DATA 0x00000000
+#define DDRSS2_PHY_936_DATA 0x00000000
+#define DDRSS2_PHY_937_DATA 0x00000000
+#define DDRSS2_PHY_938_DATA 0x00000000
+#define DDRSS2_PHY_939_DATA 0x00000000
+#define DDRSS2_PHY_940_DATA 0x00000000
+#define DDRSS2_PHY_941_DATA 0x00000000
+#define DDRSS2_PHY_942_DATA 0x00000000
+#define DDRSS2_PHY_943_DATA 0x00000000
+#define DDRSS2_PHY_944_DATA 0x00000000
+#define DDRSS2_PHY_945_DATA 0x00000000
+#define DDRSS2_PHY_946_DATA 0x00000000
+#define DDRSS2_PHY_947_DATA 0x00000000
+#define DDRSS2_PHY_948_DATA 0x00000000
+#define DDRSS2_PHY_949_DATA 0x00000000
+#define DDRSS2_PHY_950_DATA 0x00000000
+#define DDRSS2_PHY_951_DATA 0x00000000
+#define DDRSS2_PHY_952_DATA 0x00000000
+#define DDRSS2_PHY_953_DATA 0x00000000
+#define DDRSS2_PHY_954_DATA 0x00000000
+#define DDRSS2_PHY_955_DATA 0x00000000
+#define DDRSS2_PHY_956_DATA 0x00000000
+#define DDRSS2_PHY_957_DATA 0x00000000
+#define DDRSS2_PHY_958_DATA 0x00000000
+#define DDRSS2_PHY_959_DATA 0x00000000
+#define DDRSS2_PHY_960_DATA 0x00000000
+#define DDRSS2_PHY_961_DATA 0x00000000
+#define DDRSS2_PHY_962_DATA 0x00000000
+#define DDRSS2_PHY_963_DATA 0x00000000
+#define DDRSS2_PHY_964_DATA 0x00000000
+#define DDRSS2_PHY_965_DATA 0x00000000
+#define DDRSS2_PHY_966_DATA 0x00000000
+#define DDRSS2_PHY_967_DATA 0x00000000
+#define DDRSS2_PHY_968_DATA 0x00000000
+#define DDRSS2_PHY_969_DATA 0x00000000
+#define DDRSS2_PHY_970_DATA 0x00000000
+#define DDRSS2_PHY_971_DATA 0x00000000
+#define DDRSS2_PHY_972_DATA 0x00000000
+#define DDRSS2_PHY_973_DATA 0x00000000
+#define DDRSS2_PHY_974_DATA 0x00000000
+#define DDRSS2_PHY_975_DATA 0x00000000
+#define DDRSS2_PHY_976_DATA 0x00000000
+#define DDRSS2_PHY_977_DATA 0x00000000
+#define DDRSS2_PHY_978_DATA 0x00000000
+#define DDRSS2_PHY_979_DATA 0x00000000
+#define DDRSS2_PHY_980_DATA 0x00000000
+#define DDRSS2_PHY_981_DATA 0x00000000
+#define DDRSS2_PHY_982_DATA 0x00000000
+#define DDRSS2_PHY_983_DATA 0x00000000
+#define DDRSS2_PHY_984_DATA 0x00000000
+#define DDRSS2_PHY_985_DATA 0x00000000
+#define DDRSS2_PHY_986_DATA 0x00000000
+#define DDRSS2_PHY_987_DATA 0x00000000
+#define DDRSS2_PHY_988_DATA 0x00000000
+#define DDRSS2_PHY_989_DATA 0x00000000
+#define DDRSS2_PHY_990_DATA 0x00000000
+#define DDRSS2_PHY_991_DATA 0x00000000
+#define DDRSS2_PHY_992_DATA 0x00000000
+#define DDRSS2_PHY_993_DATA 0x00000000
+#define DDRSS2_PHY_994_DATA 0x00000000
+#define DDRSS2_PHY_995_DATA 0x00000000
+#define DDRSS2_PHY_996_DATA 0x00000000
+#define DDRSS2_PHY_997_DATA 0x00000000
+#define DDRSS2_PHY_998_DATA 0x00000000
+#define DDRSS2_PHY_999_DATA 0x00000000
+#define DDRSS2_PHY_1000_DATA 0x00000000
+#define DDRSS2_PHY_1001_DATA 0x00000000
+#define DDRSS2_PHY_1002_DATA 0x00000000
+#define DDRSS2_PHY_1003_DATA 0x00000000
+#define DDRSS2_PHY_1004_DATA 0x00000000
+#define DDRSS2_PHY_1005_DATA 0x00000000
+#define DDRSS2_PHY_1006_DATA 0x00000000
+#define DDRSS2_PHY_1007_DATA 0x00000000
+#define DDRSS2_PHY_1008_DATA 0x00000000
+#define DDRSS2_PHY_1009_DATA 0x00000000
+#define DDRSS2_PHY_1010_DATA 0x00000000
+#define DDRSS2_PHY_1011_DATA 0x00000000
+#define DDRSS2_PHY_1012_DATA 0x00000000
+#define DDRSS2_PHY_1013_DATA 0x00000000
+#define DDRSS2_PHY_1014_DATA 0x00000000
+#define DDRSS2_PHY_1015_DATA 0x00000000
+#define DDRSS2_PHY_1016_DATA 0x00000000
+#define DDRSS2_PHY_1017_DATA 0x00000000
+#define DDRSS2_PHY_1018_DATA 0x00000000
+#define DDRSS2_PHY_1019_DATA 0x00000000
+#define DDRSS2_PHY_1020_DATA 0x00000000
+#define DDRSS2_PHY_1021_DATA 0x00000000
+#define DDRSS2_PHY_1022_DATA 0x00000000
+#define DDRSS2_PHY_1023_DATA 0x00000000
+#define DDRSS2_PHY_1024_DATA 0x00000000
+#define DDRSS2_PHY_1025_DATA 0x00000000
+#define DDRSS2_PHY_1026_DATA 0x00000000
+#define DDRSS2_PHY_1027_DATA 0x00000000
+#define DDRSS2_PHY_1028_DATA 0x00000000
+#define DDRSS2_PHY_1029_DATA 0x00000100
+#define DDRSS2_PHY_1030_DATA 0x00000200
+#define DDRSS2_PHY_1031_DATA 0x00000000
+#define DDRSS2_PHY_1032_DATA 0x00000000
+#define DDRSS2_PHY_1033_DATA 0x00000000
+#define DDRSS2_PHY_1034_DATA 0x00000000
+#define DDRSS2_PHY_1035_DATA 0x00400000
+#define DDRSS2_PHY_1036_DATA 0x00000080
+#define DDRSS2_PHY_1037_DATA 0x00DCBA98
+#define DDRSS2_PHY_1038_DATA 0x03000000
+#define DDRSS2_PHY_1039_DATA 0x00200000
+#define DDRSS2_PHY_1040_DATA 0x00000000
+#define DDRSS2_PHY_1041_DATA 0x00000000
+#define DDRSS2_PHY_1042_DATA 0x00000000
+#define DDRSS2_PHY_1043_DATA 0x00000000
+#define DDRSS2_PHY_1044_DATA 0x00000000
+#define DDRSS2_PHY_1045_DATA 0x0000002A
+#define DDRSS2_PHY_1046_DATA 0x00000015
+#define DDRSS2_PHY_1047_DATA 0x00000015
+#define DDRSS2_PHY_1048_DATA 0x0000002A
+#define DDRSS2_PHY_1049_DATA 0x00000033
+#define DDRSS2_PHY_1050_DATA 0x0000000C
+#define DDRSS2_PHY_1051_DATA 0x0000000C
+#define DDRSS2_PHY_1052_DATA 0x00000033
+#define DDRSS2_PHY_1053_DATA 0x00543210
+#define DDRSS2_PHY_1054_DATA 0x003F0000
+#define DDRSS2_PHY_1055_DATA 0x000F3F3F
+#define DDRSS2_PHY_1056_DATA 0x20202003
+#define DDRSS2_PHY_1057_DATA 0x00202020
+#define DDRSS2_PHY_1058_DATA 0x20008008
+#define DDRSS2_PHY_1059_DATA 0x00000810
+#define DDRSS2_PHY_1060_DATA 0x00000F00
+#define DDRSS2_PHY_1061_DATA 0x00000000
+#define DDRSS2_PHY_1062_DATA 0x00000000
+#define DDRSS2_PHY_1063_DATA 0x00000000
+#define DDRSS2_PHY_1064_DATA 0x000305CC
+#define DDRSS2_PHY_1065_DATA 0x00030000
+#define DDRSS2_PHY_1066_DATA 0x00000300
+#define DDRSS2_PHY_1067_DATA 0x00000300
+#define DDRSS2_PHY_1068_DATA 0x00000300
+#define DDRSS2_PHY_1069_DATA 0x00000300
+#define DDRSS2_PHY_1070_DATA 0x00000300
+#define DDRSS2_PHY_1071_DATA 0x42080010
+#define DDRSS2_PHY_1072_DATA 0x0000803E
+#define DDRSS2_PHY_1073_DATA 0x00000001
+#define DDRSS2_PHY_1074_DATA 0x01000102
+#define DDRSS2_PHY_1075_DATA 0x00008000
+#define DDRSS2_PHY_1076_DATA 0x00000000
+#define DDRSS2_PHY_1077_DATA 0x00000000
+#define DDRSS2_PHY_1078_DATA 0x00000000
+#define DDRSS2_PHY_1079_DATA 0x00000000
+#define DDRSS2_PHY_1080_DATA 0x00000000
+#define DDRSS2_PHY_1081_DATA 0x00000000
+#define DDRSS2_PHY_1082_DATA 0x00000000
+#define DDRSS2_PHY_1083_DATA 0x00000000
+#define DDRSS2_PHY_1084_DATA 0x00000000
+#define DDRSS2_PHY_1085_DATA 0x00000000
+#define DDRSS2_PHY_1086_DATA 0x00000000
+#define DDRSS2_PHY_1087_DATA 0x00000000
+#define DDRSS2_PHY_1088_DATA 0x00000000
+#define DDRSS2_PHY_1089_DATA 0x00000000
+#define DDRSS2_PHY_1090_DATA 0x00000000
+#define DDRSS2_PHY_1091_DATA 0x00000000
+#define DDRSS2_PHY_1092_DATA 0x00000000
+#define DDRSS2_PHY_1093_DATA 0x00000000
+#define DDRSS2_PHY_1094_DATA 0x00000000
+#define DDRSS2_PHY_1095_DATA 0x00000000
+#define DDRSS2_PHY_1096_DATA 0x00000000
+#define DDRSS2_PHY_1097_DATA 0x00000000
+#define DDRSS2_PHY_1098_DATA 0x00000000
+#define DDRSS2_PHY_1099_DATA 0x00000000
+#define DDRSS2_PHY_1100_DATA 0x00000000
+#define DDRSS2_PHY_1101_DATA 0x00000000
+#define DDRSS2_PHY_1102_DATA 0x00000000
+#define DDRSS2_PHY_1103_DATA 0x00000000
+#define DDRSS2_PHY_1104_DATA 0x00000000
+#define DDRSS2_PHY_1105_DATA 0x00000000
+#define DDRSS2_PHY_1106_DATA 0x00000000
+#define DDRSS2_PHY_1107_DATA 0x00000000
+#define DDRSS2_PHY_1108_DATA 0x00000000
+#define DDRSS2_PHY_1109_DATA 0x00000000
+#define DDRSS2_PHY_1110_DATA 0x00000000
+#define DDRSS2_PHY_1111_DATA 0x00000000
+#define DDRSS2_PHY_1112_DATA 0x00000000
+#define DDRSS2_PHY_1113_DATA 0x00000000
+#define DDRSS2_PHY_1114_DATA 0x00000000
+#define DDRSS2_PHY_1115_DATA 0x00000000
+#define DDRSS2_PHY_1116_DATA 0x00000000
+#define DDRSS2_PHY_1117_DATA 0x00000000
+#define DDRSS2_PHY_1118_DATA 0x00000000
+#define DDRSS2_PHY_1119_DATA 0x00000000
+#define DDRSS2_PHY_1120_DATA 0x00000000
+#define DDRSS2_PHY_1121_DATA 0x00000000
+#define DDRSS2_PHY_1122_DATA 0x00000000
+#define DDRSS2_PHY_1123_DATA 0x00000000
+#define DDRSS2_PHY_1124_DATA 0x00000000
+#define DDRSS2_PHY_1125_DATA 0x00000000
+#define DDRSS2_PHY_1126_DATA 0x00000000
+#define DDRSS2_PHY_1127_DATA 0x00000000
+#define DDRSS2_PHY_1128_DATA 0x00000000
+#define DDRSS2_PHY_1129_DATA 0x00000000
+#define DDRSS2_PHY_1130_DATA 0x00000000
+#define DDRSS2_PHY_1131_DATA 0x00000000
+#define DDRSS2_PHY_1132_DATA 0x00000000
+#define DDRSS2_PHY_1133_DATA 0x00000000
+#define DDRSS2_PHY_1134_DATA 0x00000000
+#define DDRSS2_PHY_1135_DATA 0x00000000
+#define DDRSS2_PHY_1136_DATA 0x00000000
+#define DDRSS2_PHY_1137_DATA 0x00000000
+#define DDRSS2_PHY_1138_DATA 0x00000000
+#define DDRSS2_PHY_1139_DATA 0x00000000
+#define DDRSS2_PHY_1140_DATA 0x00000000
+#define DDRSS2_PHY_1141_DATA 0x00000000
+#define DDRSS2_PHY_1142_DATA 0x00000000
+#define DDRSS2_PHY_1143_DATA 0x00000000
+#define DDRSS2_PHY_1144_DATA 0x00000000
+#define DDRSS2_PHY_1145_DATA 0x00000000
+#define DDRSS2_PHY_1146_DATA 0x00000000
+#define DDRSS2_PHY_1147_DATA 0x00000000
+#define DDRSS2_PHY_1148_DATA 0x00000000
+#define DDRSS2_PHY_1149_DATA 0x00000000
+#define DDRSS2_PHY_1150_DATA 0x00000000
+#define DDRSS2_PHY_1151_DATA 0x00000000
+#define DDRSS2_PHY_1152_DATA 0x00000000
+#define DDRSS2_PHY_1153_DATA 0x00000000
+#define DDRSS2_PHY_1154_DATA 0x00000000
+#define DDRSS2_PHY_1155_DATA 0x00000000
+#define DDRSS2_PHY_1156_DATA 0x00000000
+#define DDRSS2_PHY_1157_DATA 0x00000000
+#define DDRSS2_PHY_1158_DATA 0x00000000
+#define DDRSS2_PHY_1159_DATA 0x00000000
+#define DDRSS2_PHY_1160_DATA 0x00000000
+#define DDRSS2_PHY_1161_DATA 0x00000000
+#define DDRSS2_PHY_1162_DATA 0x00000000
+#define DDRSS2_PHY_1163_DATA 0x00000000
+#define DDRSS2_PHY_1164_DATA 0x00000000
+#define DDRSS2_PHY_1165_DATA 0x00000000
+#define DDRSS2_PHY_1166_DATA 0x00000000
+#define DDRSS2_PHY_1167_DATA 0x00000000
+#define DDRSS2_PHY_1168_DATA 0x00000000
+#define DDRSS2_PHY_1169_DATA 0x00000000
+#define DDRSS2_PHY_1170_DATA 0x00000000
+#define DDRSS2_PHY_1171_DATA 0x00000000
+#define DDRSS2_PHY_1172_DATA 0x00000000
+#define DDRSS2_PHY_1173_DATA 0x00000000
+#define DDRSS2_PHY_1174_DATA 0x00000000
+#define DDRSS2_PHY_1175_DATA 0x00000000
+#define DDRSS2_PHY_1176_DATA 0x00000000
+#define DDRSS2_PHY_1177_DATA 0x00000000
+#define DDRSS2_PHY_1178_DATA 0x00000000
+#define DDRSS2_PHY_1179_DATA 0x00000000
+#define DDRSS2_PHY_1180_DATA 0x00000000
+#define DDRSS2_PHY_1181_DATA 0x00000000
+#define DDRSS2_PHY_1182_DATA 0x00000000
+#define DDRSS2_PHY_1183_DATA 0x00000000
+#define DDRSS2_PHY_1184_DATA 0x00000000
+#define DDRSS2_PHY_1185_DATA 0x00000000
+#define DDRSS2_PHY_1186_DATA 0x00000000
+#define DDRSS2_PHY_1187_DATA 0x00000000
+#define DDRSS2_PHY_1188_DATA 0x00000000
+#define DDRSS2_PHY_1189_DATA 0x00000000
+#define DDRSS2_PHY_1190_DATA 0x00000000
+#define DDRSS2_PHY_1191_DATA 0x00000000
+#define DDRSS2_PHY_1192_DATA 0x00000000
+#define DDRSS2_PHY_1193_DATA 0x00000000
+#define DDRSS2_PHY_1194_DATA 0x00000000
+#define DDRSS2_PHY_1195_DATA 0x00000000
+#define DDRSS2_PHY_1196_DATA 0x00000000
+#define DDRSS2_PHY_1197_DATA 0x00000000
+#define DDRSS2_PHY_1198_DATA 0x00000000
+#define DDRSS2_PHY_1199_DATA 0x00000000
+#define DDRSS2_PHY_1200_DATA 0x00000000
+#define DDRSS2_PHY_1201_DATA 0x00000000
+#define DDRSS2_PHY_1202_DATA 0x00000000
+#define DDRSS2_PHY_1203_DATA 0x00000000
+#define DDRSS2_PHY_1204_DATA 0x00000000
+#define DDRSS2_PHY_1205_DATA 0x00000000
+#define DDRSS2_PHY_1206_DATA 0x00000000
+#define DDRSS2_PHY_1207_DATA 0x00000000
+#define DDRSS2_PHY_1208_DATA 0x00000000
+#define DDRSS2_PHY_1209_DATA 0x00000000
+#define DDRSS2_PHY_1210_DATA 0x00000000
+#define DDRSS2_PHY_1211_DATA 0x00000000
+#define DDRSS2_PHY_1212_DATA 0x00000000
+#define DDRSS2_PHY_1213_DATA 0x00000000
+#define DDRSS2_PHY_1214_DATA 0x00000000
+#define DDRSS2_PHY_1215_DATA 0x00000000
+#define DDRSS2_PHY_1216_DATA 0x00000000
+#define DDRSS2_PHY_1217_DATA 0x00000000
+#define DDRSS2_PHY_1218_DATA 0x00000000
+#define DDRSS2_PHY_1219_DATA 0x00000000
+#define DDRSS2_PHY_1220_DATA 0x00000000
+#define DDRSS2_PHY_1221_DATA 0x00000000
+#define DDRSS2_PHY_1222_DATA 0x00000000
+#define DDRSS2_PHY_1223_DATA 0x00000000
+#define DDRSS2_PHY_1224_DATA 0x00000000
+#define DDRSS2_PHY_1225_DATA 0x00000000
+#define DDRSS2_PHY_1226_DATA 0x00000000
+#define DDRSS2_PHY_1227_DATA 0x00000000
+#define DDRSS2_PHY_1228_DATA 0x00000000
+#define DDRSS2_PHY_1229_DATA 0x00000000
+#define DDRSS2_PHY_1230_DATA 0x00000000
+#define DDRSS2_PHY_1231_DATA 0x00000000
+#define DDRSS2_PHY_1232_DATA 0x00000000
+#define DDRSS2_PHY_1233_DATA 0x00000000
+#define DDRSS2_PHY_1234_DATA 0x00000000
+#define DDRSS2_PHY_1235_DATA 0x00000000
+#define DDRSS2_PHY_1236_DATA 0x00000000
+#define DDRSS2_PHY_1237_DATA 0x00000000
+#define DDRSS2_PHY_1238_DATA 0x00000000
+#define DDRSS2_PHY_1239_DATA 0x00000000
+#define DDRSS2_PHY_1240_DATA 0x00000000
+#define DDRSS2_PHY_1241_DATA 0x00000000
+#define DDRSS2_PHY_1242_DATA 0x00000000
+#define DDRSS2_PHY_1243_DATA 0x00000000
+#define DDRSS2_PHY_1244_DATA 0x00000000
+#define DDRSS2_PHY_1245_DATA 0x00000000
+#define DDRSS2_PHY_1246_DATA 0x00000000
+#define DDRSS2_PHY_1247_DATA 0x00000000
+#define DDRSS2_PHY_1248_DATA 0x00000000
+#define DDRSS2_PHY_1249_DATA 0x00000000
+#define DDRSS2_PHY_1250_DATA 0x00000000
+#define DDRSS2_PHY_1251_DATA 0x00000000
+#define DDRSS2_PHY_1252_DATA 0x00000000
+#define DDRSS2_PHY_1253_DATA 0x00000000
+#define DDRSS2_PHY_1254_DATA 0x00000000
+#define DDRSS2_PHY_1255_DATA 0x00000000
+#define DDRSS2_PHY_1256_DATA 0x00000000
+#define DDRSS2_PHY_1257_DATA 0x00000000
+#define DDRSS2_PHY_1258_DATA 0x00000000
+#define DDRSS2_PHY_1259_DATA 0x00000000
+#define DDRSS2_PHY_1260_DATA 0x00000000
+#define DDRSS2_PHY_1261_DATA 0x00000000
+#define DDRSS2_PHY_1262_DATA 0x00000000
+#define DDRSS2_PHY_1263_DATA 0x00000000
+#define DDRSS2_PHY_1264_DATA 0x00000000
+#define DDRSS2_PHY_1265_DATA 0x00000000
+#define DDRSS2_PHY_1266_DATA 0x00000000
+#define DDRSS2_PHY_1267_DATA 0x00000000
+#define DDRSS2_PHY_1268_DATA 0x00000000
+#define DDRSS2_PHY_1269_DATA 0x00000000
+#define DDRSS2_PHY_1270_DATA 0x00000000
+#define DDRSS2_PHY_1271_DATA 0x00000000
+#define DDRSS2_PHY_1272_DATA 0x00000000
+#define DDRSS2_PHY_1273_DATA 0x00000000
+#define DDRSS2_PHY_1274_DATA 0x00000000
+#define DDRSS2_PHY_1275_DATA 0x00000000
+#define DDRSS2_PHY_1276_DATA 0x00000000
+#define DDRSS2_PHY_1277_DATA 0x00000000
+#define DDRSS2_PHY_1278_DATA 0x00000000
+#define DDRSS2_PHY_1279_DATA 0x00000000
+#define DDRSS2_PHY_1280_DATA 0x00000000
+#define DDRSS2_PHY_1281_DATA 0x00010100
+#define DDRSS2_PHY_1282_DATA 0x00000000
+#define DDRSS2_PHY_1283_DATA 0x00000000
+#define DDRSS2_PHY_1284_DATA 0x00050000
+#define DDRSS2_PHY_1285_DATA 0x04000000
+#define DDRSS2_PHY_1286_DATA 0x00000055
+#define DDRSS2_PHY_1287_DATA 0x00000000
+#define DDRSS2_PHY_1288_DATA 0x00000000
+#define DDRSS2_PHY_1289_DATA 0x00000000
+#define DDRSS2_PHY_1290_DATA 0x00000000
+#define DDRSS2_PHY_1291_DATA 0x00002001
+#define DDRSS2_PHY_1292_DATA 0x0000400F
+#define DDRSS2_PHY_1293_DATA 0x50020028
+#define DDRSS2_PHY_1294_DATA 0x01010000
+#define DDRSS2_PHY_1295_DATA 0x80080001
+#define DDRSS2_PHY_1296_DATA 0x10200000
+#define DDRSS2_PHY_1297_DATA 0x00000008
+#define DDRSS2_PHY_1298_DATA 0x00000000
+#define DDRSS2_PHY_1299_DATA 0x01090E00
+#define DDRSS2_PHY_1300_DATA 0x00040101
+#define DDRSS2_PHY_1301_DATA 0x0000010F
+#define DDRSS2_PHY_1302_DATA 0x00000000
+#define DDRSS2_PHY_1303_DATA 0x00000064
+#define DDRSS2_PHY_1304_DATA 0x00000000
+#define DDRSS2_PHY_1305_DATA 0x01010000
+#define DDRSS2_PHY_1306_DATA 0x01080402
+#define DDRSS2_PHY_1307_DATA 0x01200F02
+#define DDRSS2_PHY_1308_DATA 0x00194280
+#define DDRSS2_PHY_1309_DATA 0x00000004
+#define DDRSS2_PHY_1310_DATA 0x00042000
+#define DDRSS2_PHY_1311_DATA 0x00000000
+#define DDRSS2_PHY_1312_DATA 0x00000000
+#define DDRSS2_PHY_1313_DATA 0x00000000
+#define DDRSS2_PHY_1314_DATA 0x00000000
+#define DDRSS2_PHY_1315_DATA 0x00000000
+#define DDRSS2_PHY_1316_DATA 0x00000000
+#define DDRSS2_PHY_1317_DATA 0x01000000
+#define DDRSS2_PHY_1318_DATA 0x00000705
+#define DDRSS2_PHY_1319_DATA 0x00000054
+#define DDRSS2_PHY_1320_DATA 0x00030820
+#define DDRSS2_PHY_1321_DATA 0x00010820
+#define DDRSS2_PHY_1322_DATA 0x00010820
+#define DDRSS2_PHY_1323_DATA 0x00010820
+#define DDRSS2_PHY_1324_DATA 0x00010820
+#define DDRSS2_PHY_1325_DATA 0x00010820
+#define DDRSS2_PHY_1326_DATA 0x00010820
+#define DDRSS2_PHY_1327_DATA 0x00010820
+#define DDRSS2_PHY_1328_DATA 0x00010820
+#define DDRSS2_PHY_1329_DATA 0x00000000
+#define DDRSS2_PHY_1330_DATA 0x00000074
+#define DDRSS2_PHY_1331_DATA 0x00000400
+#define DDRSS2_PHY_1332_DATA 0x00000108
+#define DDRSS2_PHY_1333_DATA 0x00000000
+#define DDRSS2_PHY_1334_DATA 0x00000000
+#define DDRSS2_PHY_1335_DATA 0x00000000
+#define DDRSS2_PHY_1336_DATA 0x00000000
+#define DDRSS2_PHY_1337_DATA 0x00000000
+#define DDRSS2_PHY_1338_DATA 0x03000000
+#define DDRSS2_PHY_1339_DATA 0x00000000
+#define DDRSS2_PHY_1340_DATA 0x00000000
+#define DDRSS2_PHY_1341_DATA 0x00000000
+#define DDRSS2_PHY_1342_DATA 0x04102006
+#define DDRSS2_PHY_1343_DATA 0x00041020
+#define DDRSS2_PHY_1344_DATA 0x01C98C98
+#define DDRSS2_PHY_1345_DATA 0x3F400000
+#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS2_PHY_1347_DATA 0x0000001F
+#define DDRSS2_PHY_1348_DATA 0x00000000
+#define DDRSS2_PHY_1349_DATA 0x00000000
+#define DDRSS2_PHY_1350_DATA 0x00000000
+#define DDRSS2_PHY_1351_DATA 0x00010000
+#define DDRSS2_PHY_1352_DATA 0x00000000
+#define DDRSS2_PHY_1353_DATA 0x00000000
+#define DDRSS2_PHY_1354_DATA 0x00000000
+#define DDRSS2_PHY_1355_DATA 0x00000000
+#define DDRSS2_PHY_1356_DATA 0x76543210
+#define DDRSS2_PHY_1357_DATA 0x00010198
+#define DDRSS2_PHY_1358_DATA 0x00000000
+#define DDRSS2_PHY_1359_DATA 0x00000000
+#define DDRSS2_PHY_1360_DATA 0x00000000
+#define DDRSS2_PHY_1361_DATA 0x00040700
+#define DDRSS2_PHY_1362_DATA 0x00000000
+#define DDRSS2_PHY_1363_DATA 0x00000000
+#define DDRSS2_PHY_1364_DATA 0x00000000
+#define DDRSS2_PHY_1365_DATA 0x00000000
+#define DDRSS2_PHY_1366_DATA 0x00000000
+#define DDRSS2_PHY_1367_DATA 0x00000002
+#define DDRSS2_PHY_1368_DATA 0x00000000
+#define DDRSS2_PHY_1369_DATA 0x00000000
+#define DDRSS2_PHY_1370_DATA 0x00000000
+#define DDRSS2_PHY_1371_DATA 0x00000000
+#define DDRSS2_PHY_1372_DATA 0x00000000
+#define DDRSS2_PHY_1373_DATA 0x00000000
+#define DDRSS2_PHY_1374_DATA 0x00080000
+#define DDRSS2_PHY_1375_DATA 0x000007FF
+#define DDRSS2_PHY_1376_DATA 0x00000000
+#define DDRSS2_PHY_1377_DATA 0x00000000
+#define DDRSS2_PHY_1378_DATA 0x00000000
+#define DDRSS2_PHY_1379_DATA 0x00000000
+#define DDRSS2_PHY_1380_DATA 0x00000000
+#define DDRSS2_PHY_1381_DATA 0x00000000
+#define DDRSS2_PHY_1382_DATA 0x000FFFFF
+#define DDRSS2_PHY_1383_DATA 0x000FFFFF
+#define DDRSS2_PHY_1384_DATA 0x0000FFFF
+#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS2_PHY_1386_DATA 0x030FFFFF
+#define DDRSS2_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS2_PHY_1388_DATA 0x0000FFFF
+#define DDRSS2_PHY_1389_DATA 0x00000000
+#define DDRSS2_PHY_1390_DATA 0x00000000
+#define DDRSS2_PHY_1391_DATA 0x00000000
+#define DDRSS2_PHY_1392_DATA 0x00000000
+#define DDRSS2_PHY_1393_DATA 0x0001F7C0
+#define DDRSS2_PHY_1394_DATA 0x00000003
+#define DDRSS2_PHY_1395_DATA 0x00000000
+#define DDRSS2_PHY_1396_DATA 0x00001142
+#define DDRSS2_PHY_1397_DATA 0x040207AB
+#define DDRSS2_PHY_1398_DATA 0x01000080
+#define DDRSS2_PHY_1399_DATA 0x03900390
+#define DDRSS2_PHY_1400_DATA 0x03900390
+#define DDRSS2_PHY_1401_DATA 0x00000390
+#define DDRSS2_PHY_1402_DATA 0x00000390
+#define DDRSS2_PHY_1403_DATA 0x00000390
+#define DDRSS2_PHY_1404_DATA 0x00000390
+#define DDRSS2_PHY_1405_DATA 0x00000005
+#define DDRSS2_PHY_1406_DATA 0x01813FCC
+#define DDRSS2_PHY_1407_DATA 0x000000CC
+#define DDRSS2_PHY_1408_DATA 0x0C000DFF
+#define DDRSS2_PHY_1409_DATA 0x30000DFF
+#define DDRSS2_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1411_DATA 0x000100F0
+#define DDRSS2_PHY_1412_DATA 0x780DFFCC
+#define DDRSS2_PHY_1413_DATA 0x00007E31
+#define DDRSS2_PHY_1414_DATA 0x000CBF11
+#define DDRSS2_PHY_1415_DATA 0x01990010
+#define DDRSS2_PHY_1416_DATA 0x000CBF11
+#define DDRSS2_PHY_1417_DATA 0x01990010
+#define DDRSS2_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1419_DATA 0x00EF00F0
+#define DDRSS2_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1421_DATA 0x01FF00F0
+#define DDRSS2_PHY_1422_DATA 0x20040006
+
+#define DDRSS3_CTL_00_DATA 0x00000B00
+#define DDRSS3_CTL_01_DATA 0x00000000
+#define DDRSS3_CTL_02_DATA 0x00000000
+#define DDRSS3_CTL_03_DATA 0x00000000
+#define DDRSS3_CTL_04_DATA 0x00000000
+#define DDRSS3_CTL_05_DATA 0x00000000
+#define DDRSS3_CTL_06_DATA 0x00000000
+#define DDRSS3_CTL_07_DATA 0x00002AF8
+#define DDRSS3_CTL_08_DATA 0x0001ADAF
+#define DDRSS3_CTL_09_DATA 0x00000005
+#define DDRSS3_CTL_10_DATA 0x0000006E
+#define DDRSS3_CTL_11_DATA 0x000681C8
+#define DDRSS3_CTL_12_DATA 0x004111C9
+#define DDRSS3_CTL_13_DATA 0x00000005
+#define DDRSS3_CTL_14_DATA 0x000010A9
+#define DDRSS3_CTL_15_DATA 0x000681C8
+#define DDRSS3_CTL_16_DATA 0x004111C9
+#define DDRSS3_CTL_17_DATA 0x00000005
+#define DDRSS3_CTL_18_DATA 0x000010A9
+#define DDRSS3_CTL_19_DATA 0x01010000
+#define DDRSS3_CTL_20_DATA 0x01011001
+#define DDRSS3_CTL_21_DATA 0x02010000
+#define DDRSS3_CTL_22_DATA 0x00020100
+#define DDRSS3_CTL_23_DATA 0x0000000B
+#define DDRSS3_CTL_24_DATA 0x0000001C
+#define DDRSS3_CTL_25_DATA 0x00000000
+#define DDRSS3_CTL_26_DATA 0x00000000
+#define DDRSS3_CTL_27_DATA 0x03020200
+#define DDRSS3_CTL_28_DATA 0x00005656
+#define DDRSS3_CTL_29_DATA 0x00100000
+#define DDRSS3_CTL_30_DATA 0x00000000
+#define DDRSS3_CTL_31_DATA 0x00000000
+#define DDRSS3_CTL_32_DATA 0x00000000
+#define DDRSS3_CTL_33_DATA 0x00000000
+#define DDRSS3_CTL_34_DATA 0x040C0000
+#define DDRSS3_CTL_35_DATA 0x12501250
+#define DDRSS3_CTL_36_DATA 0x00050804
+#define DDRSS3_CTL_37_DATA 0x09040008
+#define DDRSS3_CTL_38_DATA 0x15000204
+#define DDRSS3_CTL_39_DATA 0x1760008B
+#define DDRSS3_CTL_40_DATA 0x1500422B
+#define DDRSS3_CTL_41_DATA 0x1760008B
+#define DDRSS3_CTL_42_DATA 0x2000422B
+#define DDRSS3_CTL_43_DATA 0x000A0A09
+#define DDRSS3_CTL_44_DATA 0x040003C5
+#define DDRSS3_CTL_45_DATA 0x1E161104
+#define DDRSS3_CTL_46_DATA 0x1000922C
+#define DDRSS3_CTL_47_DATA 0x1E161110
+#define DDRSS3_CTL_48_DATA 0x1000922C
+#define DDRSS3_CTL_49_DATA 0x02030410
+#define DDRSS3_CTL_50_DATA 0x2C060500
+#define DDRSS3_CTL_51_DATA 0x08292C29
+#define DDRSS3_CTL_52_DATA 0x14000E0A
+#define DDRSS3_CTL_53_DATA 0x04010A0A
+#define DDRSS3_CTL_54_DATA 0x01010004
+#define DDRSS3_CTL_55_DATA 0x0454540A
+#define DDRSS3_CTL_56_DATA 0x04313104
+#define DDRSS3_CTL_57_DATA 0x00003131
+#define DDRSS3_CTL_58_DATA 0x00010100
+#define DDRSS3_CTL_59_DATA 0x03010000
+#define DDRSS3_CTL_60_DATA 0x00001508
+#define DDRSS3_CTL_61_DATA 0x00000068
+#define DDRSS3_CTL_62_DATA 0x0000032B
+#define DDRSS3_CTL_63_DATA 0x00001035
+#define DDRSS3_CTL_64_DATA 0x0000032B
+#define DDRSS3_CTL_65_DATA 0x00001035
+#define DDRSS3_CTL_66_DATA 0x00000005
+#define DDRSS3_CTL_67_DATA 0x00050000
+#define DDRSS3_CTL_68_DATA 0x00CB0005
+#define DDRSS3_CTL_69_DATA 0x00CB0200
+#define DDRSS3_CTL_70_DATA 0x00400200
+#define DDRSS3_CTL_71_DATA 0x00120103
+#define DDRSS3_CTL_72_DATA 0x00100005
+#define DDRSS3_CTL_73_DATA 0x2F080010
+#define DDRSS3_CTL_74_DATA 0x0505012F
+#define DDRSS3_CTL_75_DATA 0x0401030A
+#define DDRSS3_CTL_76_DATA 0x041E100B
+#define DDRSS3_CTL_77_DATA 0x100B0401
+#define DDRSS3_CTL_78_DATA 0x0001041E
+#define DDRSS3_CTL_79_DATA 0x00160016
+#define DDRSS3_CTL_80_DATA 0x033B033B
+#define DDRSS3_CTL_81_DATA 0x033B033B
+#define DDRSS3_CTL_82_DATA 0x03050505
+#define DDRSS3_CTL_83_DATA 0x03010303
+#define DDRSS3_CTL_84_DATA 0x200B100B
+#define DDRSS3_CTL_85_DATA 0x04041004
+#define DDRSS3_CTL_86_DATA 0x200B100B
+#define DDRSS3_CTL_87_DATA 0x04041004
+#define DDRSS3_CTL_88_DATA 0x03010000
+#define DDRSS3_CTL_89_DATA 0x00010000
+#define DDRSS3_CTL_90_DATA 0x00000000
+#define DDRSS3_CTL_91_DATA 0x00000000
+#define DDRSS3_CTL_92_DATA 0x01000000
+#define DDRSS3_CTL_93_DATA 0x80104002
+#define DDRSS3_CTL_94_DATA 0x00000000
+#define DDRSS3_CTL_95_DATA 0x00040005
+#define DDRSS3_CTL_96_DATA 0x00000000
+#define DDRSS3_CTL_97_DATA 0x00050000
+#define DDRSS3_CTL_98_DATA 0x00000004
+#define DDRSS3_CTL_99_DATA 0x00000000
+#define DDRSS3_CTL_100_DATA 0x00040005
+#define DDRSS3_CTL_101_DATA 0x00000000
+#define DDRSS3_CTL_102_DATA 0x000018C0
+#define DDRSS3_CTL_103_DATA 0x000018C0
+#define DDRSS3_CTL_104_DATA 0x000018C0
+#define DDRSS3_CTL_105_DATA 0x000018C0
+#define DDRSS3_CTL_106_DATA 0x000018C0
+#define DDRSS3_CTL_107_DATA 0x00000000
+#define DDRSS3_CTL_108_DATA 0x000002B5
+#define DDRSS3_CTL_109_DATA 0x00040D40
+#define DDRSS3_CTL_110_DATA 0x00040D40
+#define DDRSS3_CTL_111_DATA 0x00040D40
+#define DDRSS3_CTL_112_DATA 0x00040D40
+#define DDRSS3_CTL_113_DATA 0x00040D40
+#define DDRSS3_CTL_114_DATA 0x00000000
+#define DDRSS3_CTL_115_DATA 0x00007173
+#define DDRSS3_CTL_116_DATA 0x00040D40
+#define DDRSS3_CTL_117_DATA 0x00040D40
+#define DDRSS3_CTL_118_DATA 0x00040D40
+#define DDRSS3_CTL_119_DATA 0x00040D40
+#define DDRSS3_CTL_120_DATA 0x00040D40
+#define DDRSS3_CTL_121_DATA 0x00000000
+#define DDRSS3_CTL_122_DATA 0x00007173
+#define DDRSS3_CTL_123_DATA 0x00000000
+#define DDRSS3_CTL_124_DATA 0x00000000
+#define DDRSS3_CTL_125_DATA 0x00000000
+#define DDRSS3_CTL_126_DATA 0x00000000
+#define DDRSS3_CTL_127_DATA 0x00000000
+#define DDRSS3_CTL_128_DATA 0x00000000
+#define DDRSS3_CTL_129_DATA 0x00000000
+#define DDRSS3_CTL_130_DATA 0x00000000
+#define DDRSS3_CTL_131_DATA 0x0B030500
+#define DDRSS3_CTL_132_DATA 0x00040B04
+#define DDRSS3_CTL_133_DATA 0x0A090000
+#define DDRSS3_CTL_134_DATA 0x0A090701
+#define DDRSS3_CTL_135_DATA 0x0900000E
+#define DDRSS3_CTL_136_DATA 0x0907010A
+#define DDRSS3_CTL_137_DATA 0x00000E0A
+#define DDRSS3_CTL_138_DATA 0x07010A09
+#define DDRSS3_CTL_139_DATA 0x000E0A09
+#define DDRSS3_CTL_140_DATA 0x07000401
+#define DDRSS3_CTL_141_DATA 0x00000000
+#define DDRSS3_CTL_142_DATA 0x00000000
+#define DDRSS3_CTL_143_DATA 0x00000000
+#define DDRSS3_CTL_144_DATA 0x00000000
+#define DDRSS3_CTL_145_DATA 0x00000000
+#define DDRSS3_CTL_146_DATA 0x00000000
+#define DDRSS3_CTL_147_DATA 0x00000000
+#define DDRSS3_CTL_148_DATA 0x08080000
+#define DDRSS3_CTL_149_DATA 0x01000000
+#define DDRSS3_CTL_150_DATA 0x800000C0
+#define DDRSS3_CTL_151_DATA 0x800000C0
+#define DDRSS3_CTL_152_DATA 0x800000C0
+#define DDRSS3_CTL_153_DATA 0x00000000
+#define DDRSS3_CTL_154_DATA 0x00001500
+#define DDRSS3_CTL_155_DATA 0x00000000
+#define DDRSS3_CTL_156_DATA 0x00000001
+#define DDRSS3_CTL_157_DATA 0x00000002
+#define DDRSS3_CTL_158_DATA 0x0000100E
+#define DDRSS3_CTL_159_DATA 0x00000000
+#define DDRSS3_CTL_160_DATA 0x00000000
+#define DDRSS3_CTL_161_DATA 0x00000000
+#define DDRSS3_CTL_162_DATA 0x00000000
+#define DDRSS3_CTL_163_DATA 0x00000000
+#define DDRSS3_CTL_164_DATA 0x000B0000
+#define DDRSS3_CTL_165_DATA 0x000E0006
+#define DDRSS3_CTL_166_DATA 0x000E0404
+#define DDRSS3_CTL_167_DATA 0x00D601AB
+#define DDRSS3_CTL_168_DATA 0x10100216
+#define DDRSS3_CTL_169_DATA 0x01AB0216
+#define DDRSS3_CTL_170_DATA 0x021600D6
+#define DDRSS3_CTL_171_DATA 0x02161010
+#define DDRSS3_CTL_172_DATA 0x00000000
+#define DDRSS3_CTL_173_DATA 0x00000000
+#define DDRSS3_CTL_174_DATA 0x00000000
+#define DDRSS3_CTL_175_DATA 0x3FF40084
+#define DDRSS3_CTL_176_DATA 0xF3003FF4
+#define DDRSS3_CTL_177_DATA 0x0000F3F3
+#define DDRSS3_CTL_178_DATA 0x35000000
+#define DDRSS3_CTL_179_DATA 0x27270035
+#define DDRSS3_CTL_180_DATA 0x0F0F0000
+#define DDRSS3_CTL_181_DATA 0x16000000
+#define DDRSS3_CTL_182_DATA 0x00841616
+#define DDRSS3_CTL_183_DATA 0x3FF43FF4
+#define DDRSS3_CTL_184_DATA 0xF3F3F300
+#define DDRSS3_CTL_185_DATA 0x00000000
+#define DDRSS3_CTL_186_DATA 0x00353500
+#define DDRSS3_CTL_187_DATA 0x00002727
+#define DDRSS3_CTL_188_DATA 0x00000F0F
+#define DDRSS3_CTL_189_DATA 0x16161600
+#define DDRSS3_CTL_190_DATA 0x00000020
+#define DDRSS3_CTL_191_DATA 0x01000000
+#define DDRSS3_CTL_192_DATA 0x00000001
+#define DDRSS3_CTL_193_DATA 0x00000000
+#define DDRSS3_CTL_194_DATA 0x01000000
+#define DDRSS3_CTL_195_DATA 0x00000001
+#define DDRSS3_CTL_196_DATA 0x00000000
+#define DDRSS3_CTL_197_DATA 0x00000000
+#define DDRSS3_CTL_198_DATA 0x00000000
+#define DDRSS3_CTL_199_DATA 0x00000000
+#define DDRSS3_CTL_200_DATA 0x00000000
+#define DDRSS3_CTL_201_DATA 0x00000000
+#define DDRSS3_CTL_202_DATA 0x00000000
+#define DDRSS3_CTL_203_DATA 0x00000000
+#define DDRSS3_CTL_204_DATA 0x00000000
+#define DDRSS3_CTL_205_DATA 0x00000000
+#define DDRSS3_CTL_206_DATA 0x02000000
+#define DDRSS3_CTL_207_DATA 0x01080101
+#define DDRSS3_CTL_208_DATA 0x00000000
+#define DDRSS3_CTL_209_DATA 0x00000000
+#define DDRSS3_CTL_210_DATA 0x00000000
+#define DDRSS3_CTL_211_DATA 0x00000000
+#define DDRSS3_CTL_212_DATA 0x00000000
+#define DDRSS3_CTL_213_DATA 0x00000000
+#define DDRSS3_CTL_214_DATA 0x00000000
+#define DDRSS3_CTL_215_DATA 0x00000000
+#define DDRSS3_CTL_216_DATA 0x00000000
+#define DDRSS3_CTL_217_DATA 0x00000000
+#define DDRSS3_CTL_218_DATA 0x00000000
+#define DDRSS3_CTL_219_DATA 0x00000000
+#define DDRSS3_CTL_220_DATA 0x00000000
+#define DDRSS3_CTL_221_DATA 0x00000000
+#define DDRSS3_CTL_222_DATA 0x00001000
+#define DDRSS3_CTL_223_DATA 0x006403E8
+#define DDRSS3_CTL_224_DATA 0x00000000
+#define DDRSS3_CTL_225_DATA 0x00000000
+#define DDRSS3_CTL_226_DATA 0x00000000
+#define DDRSS3_CTL_227_DATA 0x15110000
+#define DDRSS3_CTL_228_DATA 0x00040C18
+#define DDRSS3_CTL_229_DATA 0xF000C000
+#define DDRSS3_CTL_230_DATA 0x0000F000
+#define DDRSS3_CTL_231_DATA 0x00000000
+#define DDRSS3_CTL_232_DATA 0x00000000
+#define DDRSS3_CTL_233_DATA 0xC0000000
+#define DDRSS3_CTL_234_DATA 0xF000F000
+#define DDRSS3_CTL_235_DATA 0x00000000
+#define DDRSS3_CTL_236_DATA 0x00000000
+#define DDRSS3_CTL_237_DATA 0x00000000
+#define DDRSS3_CTL_238_DATA 0xF000C000
+#define DDRSS3_CTL_239_DATA 0x0000F000
+#define DDRSS3_CTL_240_DATA 0x00000000
+#define DDRSS3_CTL_241_DATA 0x00000000
+#define DDRSS3_CTL_242_DATA 0x00030000
+#define DDRSS3_CTL_243_DATA 0x00000000
+#define DDRSS3_CTL_244_DATA 0x00000000
+#define DDRSS3_CTL_245_DATA 0x00000000
+#define DDRSS3_CTL_246_DATA 0x00000000
+#define DDRSS3_CTL_247_DATA 0x00000000
+#define DDRSS3_CTL_248_DATA 0x00000000
+#define DDRSS3_CTL_249_DATA 0x00000000
+#define DDRSS3_CTL_250_DATA 0x00000000
+#define DDRSS3_CTL_251_DATA 0x00000000
+#define DDRSS3_CTL_252_DATA 0x00000000
+#define DDRSS3_CTL_253_DATA 0x00000000
+#define DDRSS3_CTL_254_DATA 0x00000000
+#define DDRSS3_CTL_255_DATA 0x00000000
+#define DDRSS3_CTL_256_DATA 0x00000000
+#define DDRSS3_CTL_257_DATA 0x01000200
+#define DDRSS3_CTL_258_DATA 0x00370040
+#define DDRSS3_CTL_259_DATA 0x00020008
+#define DDRSS3_CTL_260_DATA 0x00400100
+#define DDRSS3_CTL_261_DATA 0x00400855
+#define DDRSS3_CTL_262_DATA 0x01000200
+#define DDRSS3_CTL_263_DATA 0x08550040
+#define DDRSS3_CTL_264_DATA 0x00000040
+#define DDRSS3_CTL_265_DATA 0x006B0003
+#define DDRSS3_CTL_266_DATA 0x0100006B
+#define DDRSS3_CTL_267_DATA 0x03030303
+#define DDRSS3_CTL_268_DATA 0x00000000
+#define DDRSS3_CTL_269_DATA 0x00000202
+#define DDRSS3_CTL_270_DATA 0x00001FFF
+#define DDRSS3_CTL_271_DATA 0x3FFF2000
+#define DDRSS3_CTL_272_DATA 0x03FF0000
+#define DDRSS3_CTL_273_DATA 0x000103FF
+#define DDRSS3_CTL_274_DATA 0x0FFF0B00
+#define DDRSS3_CTL_275_DATA 0x01010001
+#define DDRSS3_CTL_276_DATA 0x01010101
+#define DDRSS3_CTL_277_DATA 0x01180101
+#define DDRSS3_CTL_278_DATA 0x00030000
+#define DDRSS3_CTL_279_DATA 0x00000000
+#define DDRSS3_CTL_280_DATA 0x00000000
+#define DDRSS3_CTL_281_DATA 0x00000000
+#define DDRSS3_CTL_282_DATA 0x00000000
+#define DDRSS3_CTL_283_DATA 0x00000000
+#define DDRSS3_CTL_284_DATA 0x00000000
+#define DDRSS3_CTL_285_DATA 0x00000000
+#define DDRSS3_CTL_286_DATA 0x00040101
+#define DDRSS3_CTL_287_DATA 0x04010100
+#define DDRSS3_CTL_288_DATA 0x00000000
+#define DDRSS3_CTL_289_DATA 0x00000000
+#define DDRSS3_CTL_290_DATA 0x03030300
+#define DDRSS3_CTL_291_DATA 0x00010101
+#define DDRSS3_CTL_292_DATA 0x00000000
+#define DDRSS3_CTL_293_DATA 0x00000000
+#define DDRSS3_CTL_294_DATA 0x00000000
+#define DDRSS3_CTL_295_DATA 0x00000000
+#define DDRSS3_CTL_296_DATA 0x00000000
+#define DDRSS3_CTL_297_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_298_DATA 0x00000FFF
+#define DDRSS3_CTL_299_DATA 0x00000000
+#define DDRSS3_CTL_300_DATA 0x00000000
+#define DDRSS3_CTL_301_DATA 0x00000000
+#define DDRSS3_CTL_302_DATA 0x00000000
+#define DDRSS3_CTL_303_DATA 0x00000000
+#define DDRSS3_CTL_304_DATA 0x00000000
+#define DDRSS3_CTL_305_DATA 0x00000000
+#define DDRSS3_CTL_306_DATA 0x00000000
+#define DDRSS3_CTL_307_DATA 0x00000000
+#define DDRSS3_CTL_308_DATA 0x00000000
+#define DDRSS3_CTL_309_DATA 0x00000000
+#define DDRSS3_CTL_310_DATA 0x00000000
+#define DDRSS3_CTL_311_DATA 0x00000000
+#define DDRSS3_CTL_312_DATA 0x00000000
+#define DDRSS3_CTL_313_DATA 0x01000000
+#define DDRSS3_CTL_314_DATA 0x00020201
+#define DDRSS3_CTL_315_DATA 0x01000101
+#define DDRSS3_CTL_316_DATA 0x01010001
+#define DDRSS3_CTL_317_DATA 0x00010101
+#define DDRSS3_CTL_318_DATA 0x050A0A03
+#define DDRSS3_CTL_319_DATA 0x10082323
+#define DDRSS3_CTL_320_DATA 0x00090310
+#define DDRSS3_CTL_321_DATA 0x0B0C030F
+#define DDRSS3_CTL_322_DATA 0x0B0C0306
+#define DDRSS3_CTL_323_DATA 0x0C090006
+#define DDRSS3_CTL_324_DATA 0x0100000C
+#define DDRSS3_CTL_325_DATA 0x08040801
+#define DDRSS3_CTL_326_DATA 0x00000004
+#define DDRSS3_CTL_327_DATA 0x00000000
+#define DDRSS3_CTL_328_DATA 0x00010000
+#define DDRSS3_CTL_329_DATA 0x00280D00
+#define DDRSS3_CTL_330_DATA 0x00000001
+#define DDRSS3_CTL_331_DATA 0x00030001
+#define DDRSS3_CTL_332_DATA 0x00000000
+#define DDRSS3_CTL_333_DATA 0x00000000
+#define DDRSS3_CTL_334_DATA 0x00000000
+#define DDRSS3_CTL_335_DATA 0x00000000
+#define DDRSS3_CTL_336_DATA 0x00000000
+#define DDRSS3_CTL_337_DATA 0x00000000
+#define DDRSS3_CTL_338_DATA 0x00000000
+#define DDRSS3_CTL_339_DATA 0x00000000
+#define DDRSS3_CTL_340_DATA 0x01000000
+#define DDRSS3_CTL_341_DATA 0x00000001
+#define DDRSS3_CTL_342_DATA 0x00010100
+#define DDRSS3_CTL_343_DATA 0x03030000
+#define DDRSS3_CTL_344_DATA 0x00000000
+#define DDRSS3_CTL_345_DATA 0x00000000
+#define DDRSS3_CTL_346_DATA 0x00000000
+#define DDRSS3_CTL_347_DATA 0x00000000
+#define DDRSS3_CTL_348_DATA 0x00000000
+#define DDRSS3_CTL_349_DATA 0x00000000
+#define DDRSS3_CTL_350_DATA 0x00000000
+#define DDRSS3_CTL_351_DATA 0x00000000
+#define DDRSS3_CTL_352_DATA 0x00000000
+#define DDRSS3_CTL_353_DATA 0x00000000
+#define DDRSS3_CTL_354_DATA 0x00000000
+#define DDRSS3_CTL_355_DATA 0x00000000
+#define DDRSS3_CTL_356_DATA 0x00000000
+#define DDRSS3_CTL_357_DATA 0x00000000
+#define DDRSS3_CTL_358_DATA 0x00000000
+#define DDRSS3_CTL_359_DATA 0x00000000
+#define DDRSS3_CTL_360_DATA 0x000556AA
+#define DDRSS3_CTL_361_DATA 0x000AAAAA
+#define DDRSS3_CTL_362_DATA 0x000AA955
+#define DDRSS3_CTL_363_DATA 0x00055555
+#define DDRSS3_CTL_364_DATA 0x000B3133
+#define DDRSS3_CTL_365_DATA 0x0004CD33
+#define DDRSS3_CTL_366_DATA 0x0004CECC
+#define DDRSS3_CTL_367_DATA 0x000B32CC
+#define DDRSS3_CTL_368_DATA 0x00010300
+#define DDRSS3_CTL_369_DATA 0x03000100
+#define DDRSS3_CTL_370_DATA 0x00000000
+#define DDRSS3_CTL_371_DATA 0x00000000
+#define DDRSS3_CTL_372_DATA 0x00000000
+#define DDRSS3_CTL_373_DATA 0x00000000
+#define DDRSS3_CTL_374_DATA 0x00000000
+#define DDRSS3_CTL_375_DATA 0x00000000
+#define DDRSS3_CTL_376_DATA 0x00000000
+#define DDRSS3_CTL_377_DATA 0x00010000
+#define DDRSS3_CTL_378_DATA 0x00000404
+#define DDRSS3_CTL_379_DATA 0x00000000
+#define DDRSS3_CTL_380_DATA 0x00000000
+#define DDRSS3_CTL_381_DATA 0x00000000
+#define DDRSS3_CTL_382_DATA 0x00000000
+#define DDRSS3_CTL_383_DATA 0x00000000
+#define DDRSS3_CTL_384_DATA 0x00000000
+#define DDRSS3_CTL_385_DATA 0x00000000
+#define DDRSS3_CTL_386_DATA 0x00000000
+#define DDRSS3_CTL_387_DATA 0x3A3A1B00
+#define DDRSS3_CTL_388_DATA 0x000A0000
+#define DDRSS3_CTL_389_DATA 0x000000C6
+#define DDRSS3_CTL_390_DATA 0x00000200
+#define DDRSS3_CTL_391_DATA 0x00000200
+#define DDRSS3_CTL_392_DATA 0x00000200
+#define DDRSS3_CTL_393_DATA 0x00000200
+#define DDRSS3_CTL_394_DATA 0x00000270
+#define DDRSS3_CTL_395_DATA 0x000007BC
+#define DDRSS3_CTL_396_DATA 0x00000204
+#define DDRSS3_CTL_397_DATA 0x0000206A
+#define DDRSS3_CTL_398_DATA 0x00000200
+#define DDRSS3_CTL_399_DATA 0x00000200
+#define DDRSS3_CTL_400_DATA 0x00000200
+#define DDRSS3_CTL_401_DATA 0x00000200
+#define DDRSS3_CTL_402_DATA 0x0000613E
+#define DDRSS3_CTL_403_DATA 0x00014424
+#define DDRSS3_CTL_404_DATA 0x00000E19
+#define DDRSS3_CTL_405_DATA 0x0000206A
+#define DDRSS3_CTL_406_DATA 0x00000200
+#define DDRSS3_CTL_407_DATA 0x00000200
+#define DDRSS3_CTL_408_DATA 0x00000200
+#define DDRSS3_CTL_409_DATA 0x00000200
+#define DDRSS3_CTL_410_DATA 0x0000613E
+#define DDRSS3_CTL_411_DATA 0x00014424
+#define DDRSS3_CTL_412_DATA 0x02020E19
+#define DDRSS3_CTL_413_DATA 0x03030202
+#define DDRSS3_CTL_414_DATA 0x00000022
+#define DDRSS3_CTL_415_DATA 0x00000000
+#define DDRSS3_CTL_416_DATA 0x00000000
+#define DDRSS3_CTL_417_DATA 0x00001403
+#define DDRSS3_CTL_418_DATA 0x000007D0
+#define DDRSS3_CTL_419_DATA 0x00000000
+#define DDRSS3_CTL_420_DATA 0x00000000
+#define DDRSS3_CTL_421_DATA 0x00030000
+#define DDRSS3_CTL_422_DATA 0x0007001F
+#define DDRSS3_CTL_423_DATA 0x001B0033
+#define DDRSS3_CTL_424_DATA 0x001B0033
+#define DDRSS3_CTL_425_DATA 0x00000000
+#define DDRSS3_CTL_426_DATA 0x00000000
+#define DDRSS3_CTL_427_DATA 0x02000000
+#define DDRSS3_CTL_428_DATA 0x01000404
+#define DDRSS3_CTL_429_DATA 0x0B220B22
+#define DDRSS3_CTL_430_DATA 0x00000105
+#define DDRSS3_CTL_431_DATA 0x00010101
+#define DDRSS3_CTL_432_DATA 0x00010101
+#define DDRSS3_CTL_433_DATA 0x00010001
+#define DDRSS3_CTL_434_DATA 0x00000101
+#define DDRSS3_CTL_435_DATA 0x02000201
+#define DDRSS3_CTL_436_DATA 0x02010000
+#define DDRSS3_CTL_437_DATA 0x00000200
+#define DDRSS3_CTL_438_DATA 0x28060000
+#define DDRSS3_CTL_439_DATA 0x00000128
+#define DDRSS3_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_442_DATA 0x00000000
+#define DDRSS3_CTL_443_DATA 0x00000000
+#define DDRSS3_CTL_444_DATA 0x00000000
+#define DDRSS3_CTL_445_DATA 0x00000000
+#define DDRSS3_CTL_446_DATA 0x00000000
+#define DDRSS3_CTL_447_DATA 0x00000000
+#define DDRSS3_CTL_448_DATA 0x00000000
+#define DDRSS3_CTL_449_DATA 0x00000000
+#define DDRSS3_CTL_450_DATA 0x00000000
+#define DDRSS3_CTL_451_DATA 0x00000000
+#define DDRSS3_CTL_452_DATA 0x00000000
+#define DDRSS3_CTL_453_DATA 0x00000000
+#define DDRSS3_CTL_454_DATA 0x00000000
+#define DDRSS3_CTL_455_DATA 0x00000000
+#define DDRSS3_CTL_456_DATA 0x00000000
+#define DDRSS3_CTL_457_DATA 0x00000000
+#define DDRSS3_CTL_458_DATA 0x00000000
+
+#define DDRSS3_PI_00_DATA 0x00000B00
+#define DDRSS3_PI_01_DATA 0x00000000
+#define DDRSS3_PI_02_DATA 0x00000000
+#define DDRSS3_PI_03_DATA 0x00000000
+#define DDRSS3_PI_04_DATA 0x00000000
+#define DDRSS3_PI_05_DATA 0x00000101
+#define DDRSS3_PI_06_DATA 0x00640000
+#define DDRSS3_PI_07_DATA 0x00000001
+#define DDRSS3_PI_08_DATA 0x00000000
+#define DDRSS3_PI_09_DATA 0x00000000
+#define DDRSS3_PI_10_DATA 0x00000000
+#define DDRSS3_PI_11_DATA 0x00000000
+#define DDRSS3_PI_12_DATA 0x00000003
+#define DDRSS3_PI_13_DATA 0x00010001
+#define DDRSS3_PI_14_DATA 0x0800000F
+#define DDRSS3_PI_15_DATA 0x00000103
+#define DDRSS3_PI_16_DATA 0x00000005
+#define DDRSS3_PI_17_DATA 0x00000000
+#define DDRSS3_PI_18_DATA 0x00000000
+#define DDRSS3_PI_19_DATA 0x00000000
+#define DDRSS3_PI_20_DATA 0x00000000
+#define DDRSS3_PI_21_DATA 0x00000000
+#define DDRSS3_PI_22_DATA 0x00000000
+#define DDRSS3_PI_23_DATA 0x00000000
+#define DDRSS3_PI_24_DATA 0x00000000
+#define DDRSS3_PI_25_DATA 0x00000000
+#define DDRSS3_PI_26_DATA 0x00010100
+#define DDRSS3_PI_27_DATA 0x00280A00
+#define DDRSS3_PI_28_DATA 0x00000000
+#define DDRSS3_PI_29_DATA 0x0F000000
+#define DDRSS3_PI_30_DATA 0x00003200
+#define DDRSS3_PI_31_DATA 0x00000000
+#define DDRSS3_PI_32_DATA 0x00000000
+#define DDRSS3_PI_33_DATA 0x01010102
+#define DDRSS3_PI_34_DATA 0x00000000
+#define DDRSS3_PI_35_DATA 0x000000AA
+#define DDRSS3_PI_36_DATA 0x00000055
+#define DDRSS3_PI_37_DATA 0x000000B5
+#define DDRSS3_PI_38_DATA 0x0000004A
+#define DDRSS3_PI_39_DATA 0x00000056
+#define DDRSS3_PI_40_DATA 0x000000A9
+#define DDRSS3_PI_41_DATA 0x000000A9
+#define DDRSS3_PI_42_DATA 0x000000B5
+#define DDRSS3_PI_43_DATA 0x00000000
+#define DDRSS3_PI_44_DATA 0x00000000
+#define DDRSS3_PI_45_DATA 0x000F0F00
+#define DDRSS3_PI_46_DATA 0x0000001B
+#define DDRSS3_PI_47_DATA 0x000007D0
+#define DDRSS3_PI_48_DATA 0x00000300
+#define DDRSS3_PI_49_DATA 0x00000000
+#define DDRSS3_PI_50_DATA 0x00000000
+#define DDRSS3_PI_51_DATA 0x01000000
+#define DDRSS3_PI_52_DATA 0x00010101
+#define DDRSS3_PI_53_DATA 0x00000000
+#define DDRSS3_PI_54_DATA 0x00030000
+#define DDRSS3_PI_55_DATA 0x0F000000
+#define DDRSS3_PI_56_DATA 0x00000017
+#define DDRSS3_PI_57_DATA 0x00000000
+#define DDRSS3_PI_58_DATA 0x00000000
+#define DDRSS3_PI_59_DATA 0x00000000
+#define DDRSS3_PI_60_DATA 0x0A0A140A
+#define DDRSS3_PI_61_DATA 0x10020201
+#define DDRSS3_PI_62_DATA 0x00020805
+#define DDRSS3_PI_63_DATA 0x01000404
+#define DDRSS3_PI_64_DATA 0x00000000
+#define DDRSS3_PI_65_DATA 0x00000000
+#define DDRSS3_PI_66_DATA 0x00000100
+#define DDRSS3_PI_67_DATA 0x0002020F
+#define DDRSS3_PI_68_DATA 0x00340000
+#define DDRSS3_PI_69_DATA 0x00000000
+#define DDRSS3_PI_70_DATA 0x00000000
+#define DDRSS3_PI_71_DATA 0x0000FFFF
+#define DDRSS3_PI_72_DATA 0x01000000
+#define DDRSS3_PI_73_DATA 0x00080000
+#define DDRSS3_PI_74_DATA 0x02000200
+#define DDRSS3_PI_75_DATA 0x01000100
+#define DDRSS3_PI_76_DATA 0x01000000
+#define DDRSS3_PI_77_DATA 0x02000200
+#define DDRSS3_PI_78_DATA 0x00000200
+#define DDRSS3_PI_79_DATA 0x00000000
+#define DDRSS3_PI_80_DATA 0x00000000
+#define DDRSS3_PI_81_DATA 0x00000000
+#define DDRSS3_PI_82_DATA 0x00000000
+#define DDRSS3_PI_83_DATA 0x00000000
+#define DDRSS3_PI_84_DATA 0x00000000
+#define DDRSS3_PI_85_DATA 0x00000000
+#define DDRSS3_PI_86_DATA 0x00000000
+#define DDRSS3_PI_87_DATA 0x00000000
+#define DDRSS3_PI_88_DATA 0x00000000
+#define DDRSS3_PI_89_DATA 0x00000000
+#define DDRSS3_PI_90_DATA 0x00000000
+#define DDRSS3_PI_91_DATA 0x00000400
+#define DDRSS3_PI_92_DATA 0x02010000
+#define DDRSS3_PI_93_DATA 0x00080003
+#define DDRSS3_PI_94_DATA 0x00080000
+#define DDRSS3_PI_95_DATA 0x00000001
+#define DDRSS3_PI_96_DATA 0x00000000
+#define DDRSS3_PI_97_DATA 0x0000AA00
+#define DDRSS3_PI_98_DATA 0x00000000
+#define DDRSS3_PI_99_DATA 0x00000000
+#define DDRSS3_PI_100_DATA 0x00010000
+#define DDRSS3_PI_101_DATA 0x00000000
+#define DDRSS3_PI_102_DATA 0x00000000
+#define DDRSS3_PI_103_DATA 0x00000000
+#define DDRSS3_PI_104_DATA 0x00000000
+#define DDRSS3_PI_105_DATA 0x00000000
+#define DDRSS3_PI_106_DATA 0x00000000
+#define DDRSS3_PI_107_DATA 0x00000000
+#define DDRSS3_PI_108_DATA 0x00000000
+#define DDRSS3_PI_109_DATA 0x00000000
+#define DDRSS3_PI_110_DATA 0x00000000
+#define DDRSS3_PI_111_DATA 0x00000000
+#define DDRSS3_PI_112_DATA 0x00000000
+#define DDRSS3_PI_113_DATA 0x00000000
+#define DDRSS3_PI_114_DATA 0x00000000
+#define DDRSS3_PI_115_DATA 0x00000000
+#define DDRSS3_PI_116_DATA 0x00000000
+#define DDRSS3_PI_117_DATA 0x00000000
+#define DDRSS3_PI_118_DATA 0x00000000
+#define DDRSS3_PI_119_DATA 0x00000000
+#define DDRSS3_PI_120_DATA 0x00000000
+#define DDRSS3_PI_121_DATA 0x00000000
+#define DDRSS3_PI_122_DATA 0x00000000
+#define DDRSS3_PI_123_DATA 0x00000000
+#define DDRSS3_PI_124_DATA 0x00000000
+#define DDRSS3_PI_125_DATA 0x00000008
+#define DDRSS3_PI_126_DATA 0x00000000
+#define DDRSS3_PI_127_DATA 0x00000000
+#define DDRSS3_PI_128_DATA 0x00000000
+#define DDRSS3_PI_129_DATA 0x00000000
+#define DDRSS3_PI_130_DATA 0x00000000
+#define DDRSS3_PI_131_DATA 0x00000000
+#define DDRSS3_PI_132_DATA 0x00000000
+#define DDRSS3_PI_133_DATA 0x00000000
+#define DDRSS3_PI_134_DATA 0x00000002
+#define DDRSS3_PI_135_DATA 0x00000000
+#define DDRSS3_PI_136_DATA 0x00000000
+#define DDRSS3_PI_137_DATA 0x0000000A
+#define DDRSS3_PI_138_DATA 0x00000019
+#define DDRSS3_PI_139_DATA 0x00000100
+#define DDRSS3_PI_140_DATA 0x00000000
+#define DDRSS3_PI_141_DATA 0x00000000
+#define DDRSS3_PI_142_DATA 0x00000000
+#define DDRSS3_PI_143_DATA 0x00000000
+#define DDRSS3_PI_144_DATA 0x01000000
+#define DDRSS3_PI_145_DATA 0x00010003
+#define DDRSS3_PI_146_DATA 0x02000101
+#define DDRSS3_PI_147_DATA 0x01030001
+#define DDRSS3_PI_148_DATA 0x00010400
+#define DDRSS3_PI_149_DATA 0x06000105
+#define DDRSS3_PI_150_DATA 0x01070001
+#define DDRSS3_PI_151_DATA 0x00000000
+#define DDRSS3_PI_152_DATA 0x00000000
+#define DDRSS3_PI_153_DATA 0x00000000
+#define DDRSS3_PI_154_DATA 0x00010001
+#define DDRSS3_PI_155_DATA 0x00000000
+#define DDRSS3_PI_156_DATA 0x00000000
+#define DDRSS3_PI_157_DATA 0x00000000
+#define DDRSS3_PI_158_DATA 0x00000000
+#define DDRSS3_PI_159_DATA 0x00000401
+#define DDRSS3_PI_160_DATA 0x00000000
+#define DDRSS3_PI_161_DATA 0x05010000
+#define DDRSS3_PI_162_DATA 0x00000001
+#define DDRSS3_PI_163_DATA 0x2B2B0201
+#define DDRSS3_PI_164_DATA 0x00000034
+#define DDRSS3_PI_165_DATA 0x00000068
+#define DDRSS3_PI_166_DATA 0x00020068
+#define DDRSS3_PI_167_DATA 0x02000200
+#define DDRSS3_PI_168_DATA 0x50120C04
+#define DDRSS3_PI_169_DATA 0x00155012
+#define DDRSS3_PI_170_DATA 0x00000068
+#define DDRSS3_PI_171_DATA 0x0000032B
+#define DDRSS3_PI_172_DATA 0x00001035
+#define DDRSS3_PI_173_DATA 0x0000032B
+#define DDRSS3_PI_174_DATA 0x04001035
+#define DDRSS3_PI_175_DATA 0x01010404
+#define DDRSS3_PI_176_DATA 0x00001500
+#define DDRSS3_PI_177_DATA 0x00150015
+#define DDRSS3_PI_178_DATA 0x01000100
+#define DDRSS3_PI_179_DATA 0x00000100
+#define DDRSS3_PI_180_DATA 0x00000000
+#define DDRSS3_PI_181_DATA 0x01010101
+#define DDRSS3_PI_182_DATA 0x00000000
+#define DDRSS3_PI_183_DATA 0x00000000
+#define DDRSS3_PI_184_DATA 0x00000000
+#define DDRSS3_PI_185_DATA 0x19040000
+#define DDRSS3_PI_186_DATA 0x0E0E0219
+#define DDRSS3_PI_187_DATA 0x00040402
+#define DDRSS3_PI_188_DATA 0x000D0035
+#define DDRSS3_PI_189_DATA 0x00218049
+#define DDRSS3_PI_190_DATA 0x00218049
+#define DDRSS3_PI_191_DATA 0x01000101
+#define DDRSS3_PI_192_DATA 0x0004000E
+#define DDRSS3_PI_193_DATA 0x00040216
+#define DDRSS3_PI_194_DATA 0x01000216
+#define DDRSS3_PI_195_DATA 0x000F000F
+#define DDRSS3_PI_196_DATA 0x02170100
+#define DDRSS3_PI_197_DATA 0x01000217
+#define DDRSS3_PI_198_DATA 0x02170217
+#define DDRSS3_PI_199_DATA 0x2F1B3200
+#define DDRSS3_PI_200_DATA 0x01012F1B
+#define DDRSS3_PI_201_DATA 0x0A070601
+#define DDRSS3_PI_202_DATA 0x1F130A0D
+#define DDRSS3_PI_203_DATA 0x1F130A14
+#define DDRSS3_PI_204_DATA 0x0000C014
+#define DDRSS3_PI_205_DATA 0x00C01000
+#define DDRSS3_PI_206_DATA 0x00C01000
+#define DDRSS3_PI_207_DATA 0x00021000
+#define DDRSS3_PI_208_DATA 0x0024000E
+#define DDRSS3_PI_209_DATA 0x00240216
+#define DDRSS3_PI_210_DATA 0x00110216
+#define DDRSS3_PI_211_DATA 0x32000056
+#define DDRSS3_PI_212_DATA 0x00000101
+#define DDRSS3_PI_213_DATA 0x005F0036
+#define DDRSS3_PI_214_DATA 0x03013212
+#define DDRSS3_PI_215_DATA 0x00003600
+#define DDRSS3_PI_216_DATA 0x3212005F
+#define DDRSS3_PI_217_DATA 0x09000001
+#define DDRSS3_PI_218_DATA 0x06010504
+#define DDRSS3_PI_219_DATA 0x04000364
+#define DDRSS3_PI_220_DATA 0x0A032001
+#define DDRSS3_PI_221_DATA 0x2C31110A
+#define DDRSS3_PI_222_DATA 0x00002918
+#define DDRSS3_PI_223_DATA 0x6000838E
+#define DDRSS3_PI_224_DATA 0x1E202008
+#define DDRSS3_PI_225_DATA 0x2C311116
+#define DDRSS3_PI_226_DATA 0x00002918
+#define DDRSS3_PI_227_DATA 0x6000838E
+#define DDRSS3_PI_228_DATA 0x1E202008
+#define DDRSS3_PI_229_DATA 0x0000C616
+#define DDRSS3_PI_230_DATA 0x000007BC
+#define DDRSS3_PI_231_DATA 0x0000206A
+#define DDRSS3_PI_232_DATA 0x00014424
+#define DDRSS3_PI_233_DATA 0x0000206A
+#define DDRSS3_PI_234_DATA 0x00014424
+#define DDRSS3_PI_235_DATA 0x033B0016
+#define DDRSS3_PI_236_DATA 0x0303033B
+#define DDRSS3_PI_237_DATA 0x002AF803
+#define DDRSS3_PI_238_DATA 0x0001ADAF
+#define DDRSS3_PI_239_DATA 0x00000005
+#define DDRSS3_PI_240_DATA 0x0000006E
+#define DDRSS3_PI_241_DATA 0x00000016
+#define DDRSS3_PI_242_DATA 0x000681C8
+#define DDRSS3_PI_243_DATA 0x0001ADAF
+#define DDRSS3_PI_244_DATA 0x00000005
+#define DDRSS3_PI_245_DATA 0x000010A9
+#define DDRSS3_PI_246_DATA 0x0000033B
+#define DDRSS3_PI_247_DATA 0x000681C8
+#define DDRSS3_PI_248_DATA 0x0001ADAF
+#define DDRSS3_PI_249_DATA 0x00000005
+#define DDRSS3_PI_250_DATA 0x000010A9
+#define DDRSS3_PI_251_DATA 0x0100033B
+#define DDRSS3_PI_252_DATA 0x00370040
+#define DDRSS3_PI_253_DATA 0x00010008
+#define DDRSS3_PI_254_DATA 0x08550040
+#define DDRSS3_PI_255_DATA 0x00010040
+#define DDRSS3_PI_256_DATA 0x08550040
+#define DDRSS3_PI_257_DATA 0x00000340
+#define DDRSS3_PI_258_DATA 0x006B006B
+#define DDRSS3_PI_259_DATA 0x08040404
+#define DDRSS3_PI_260_DATA 0x00000055
+#define DDRSS3_PI_261_DATA 0x55083C5A
+#define DDRSS3_PI_262_DATA 0x5A000000
+#define DDRSS3_PI_263_DATA 0x0055083C
+#define DDRSS3_PI_264_DATA 0x3C5A0000
+#define DDRSS3_PI_265_DATA 0x00005508
+#define DDRSS3_PI_266_DATA 0x0C3C5A00
+#define DDRSS3_PI_267_DATA 0x080F0E0D
+#define DDRSS3_PI_268_DATA 0x000B0A09
+#define DDRSS3_PI_269_DATA 0x00030201
+#define DDRSS3_PI_270_DATA 0x01000000
+#define DDRSS3_PI_271_DATA 0x04020201
+#define DDRSS3_PI_272_DATA 0x00080804
+#define DDRSS3_PI_273_DATA 0x00000000
+#define DDRSS3_PI_274_DATA 0x00000000
+#define DDRSS3_PI_275_DATA 0x00F30084
+#define DDRSS3_PI_276_DATA 0x00160000
+#define DDRSS3_PI_277_DATA 0x35F33FF4
+#define DDRSS3_PI_278_DATA 0x00160F27
+#define DDRSS3_PI_279_DATA 0x35F33FF4
+#define DDRSS3_PI_280_DATA 0x00160F27
+#define DDRSS3_PI_281_DATA 0x00F30084
+#define DDRSS3_PI_282_DATA 0x00160000
+#define DDRSS3_PI_283_DATA 0x35F33FF4
+#define DDRSS3_PI_284_DATA 0x00160F27
+#define DDRSS3_PI_285_DATA 0x35F33FF4
+#define DDRSS3_PI_286_DATA 0x00160F27
+#define DDRSS3_PI_287_DATA 0x00F30084
+#define DDRSS3_PI_288_DATA 0x00160000
+#define DDRSS3_PI_289_DATA 0x35F33FF4
+#define DDRSS3_PI_290_DATA 0x00160F27
+#define DDRSS3_PI_291_DATA 0x35F33FF4
+#define DDRSS3_PI_292_DATA 0x00160F27
+#define DDRSS3_PI_293_DATA 0x00F30084
+#define DDRSS3_PI_294_DATA 0x00160000
+#define DDRSS3_PI_295_DATA 0x35F33FF4
+#define DDRSS3_PI_296_DATA 0x00160F27
+#define DDRSS3_PI_297_DATA 0x35F33FF4
+#define DDRSS3_PI_298_DATA 0x00160F27
+#define DDRSS3_PI_299_DATA 0x00000000
+
+#define DDRSS3_PHY_00_DATA 0x000004F0
+#define DDRSS3_PHY_01_DATA 0x00000000
+#define DDRSS3_PHY_02_DATA 0x00030200
+#define DDRSS3_PHY_03_DATA 0x00000000
+#define DDRSS3_PHY_04_DATA 0x00000000
+#define DDRSS3_PHY_05_DATA 0x01030000
+#define DDRSS3_PHY_06_DATA 0x00010000
+#define DDRSS3_PHY_07_DATA 0x01030004
+#define DDRSS3_PHY_08_DATA 0x01000000
+#define DDRSS3_PHY_09_DATA 0x00000000
+#define DDRSS3_PHY_10_DATA 0x00000000
+#define DDRSS3_PHY_11_DATA 0x01000001
+#define DDRSS3_PHY_12_DATA 0x00000200
+#define DDRSS3_PHY_13_DATA 0x000800C0
+#define DDRSS3_PHY_14_DATA 0x060100CC
+#define DDRSS3_PHY_15_DATA 0x00030066
+#define DDRSS3_PHY_16_DATA 0x00000000
+#define DDRSS3_PHY_17_DATA 0x00000301
+#define DDRSS3_PHY_18_DATA 0x0000AAAA
+#define DDRSS3_PHY_19_DATA 0x00005555
+#define DDRSS3_PHY_20_DATA 0x0000B5B5
+#define DDRSS3_PHY_21_DATA 0x00004A4A
+#define DDRSS3_PHY_22_DATA 0x00005656
+#define DDRSS3_PHY_23_DATA 0x0000A9A9
+#define DDRSS3_PHY_24_DATA 0x0000A9A9
+#define DDRSS3_PHY_25_DATA 0x0000B5B5
+#define DDRSS3_PHY_26_DATA 0x00000000
+#define DDRSS3_PHY_27_DATA 0x00000000
+#define DDRSS3_PHY_28_DATA 0x2A000000
+#define DDRSS3_PHY_29_DATA 0x00000808
+#define DDRSS3_PHY_30_DATA 0x0F000000
+#define DDRSS3_PHY_31_DATA 0x00000F08
+#define DDRSS3_PHY_32_DATA 0x10400000
+#define DDRSS3_PHY_33_DATA 0x0C002006
+#define DDRSS3_PHY_34_DATA 0x00000000
+#define DDRSS3_PHY_35_DATA 0x00000000
+#define DDRSS3_PHY_36_DATA 0x55555555
+#define DDRSS3_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_38_DATA 0x55555555
+#define DDRSS3_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_40_DATA 0x00005555
+#define DDRSS3_PHY_41_DATA 0x01000100
+#define DDRSS3_PHY_42_DATA 0x00800180
+#define DDRSS3_PHY_43_DATA 0x00000001
+#define DDRSS3_PHY_44_DATA 0x00000000
+#define DDRSS3_PHY_45_DATA 0x00000000
+#define DDRSS3_PHY_46_DATA 0x00000000
+#define DDRSS3_PHY_47_DATA 0x00000000
+#define DDRSS3_PHY_48_DATA 0x00000000
+#define DDRSS3_PHY_49_DATA 0x00000000
+#define DDRSS3_PHY_50_DATA 0x00000000
+#define DDRSS3_PHY_51_DATA 0x00000000
+#define DDRSS3_PHY_52_DATA 0x00000000
+#define DDRSS3_PHY_53_DATA 0x00000000
+#define DDRSS3_PHY_54_DATA 0x00000000
+#define DDRSS3_PHY_55_DATA 0x00000000
+#define DDRSS3_PHY_56_DATA 0x00000000
+#define DDRSS3_PHY_57_DATA 0x00000000
+#define DDRSS3_PHY_58_DATA 0x00000000
+#define DDRSS3_PHY_59_DATA 0x00000000
+#define DDRSS3_PHY_60_DATA 0x00000000
+#define DDRSS3_PHY_61_DATA 0x00000000
+#define DDRSS3_PHY_62_DATA 0x00000000
+#define DDRSS3_PHY_63_DATA 0x00000000
+#define DDRSS3_PHY_64_DATA 0x00000000
+#define DDRSS3_PHY_65_DATA 0x00000000
+#define DDRSS3_PHY_66_DATA 0x00000104
+#define DDRSS3_PHY_67_DATA 0x00000120
+#define DDRSS3_PHY_68_DATA 0x00000000
+#define DDRSS3_PHY_69_DATA 0x00000000
+#define DDRSS3_PHY_70_DATA 0x00000000
+#define DDRSS3_PHY_71_DATA 0x00000000
+#define DDRSS3_PHY_72_DATA 0x00000000
+#define DDRSS3_PHY_73_DATA 0x00000000
+#define DDRSS3_PHY_74_DATA 0x00000000
+#define DDRSS3_PHY_75_DATA 0x00000001
+#define DDRSS3_PHY_76_DATA 0x07FF0000
+#define DDRSS3_PHY_77_DATA 0x0080081F
+#define DDRSS3_PHY_78_DATA 0x00081020
+#define DDRSS3_PHY_79_DATA 0x04010000
+#define DDRSS3_PHY_80_DATA 0x00000000
+#define DDRSS3_PHY_81_DATA 0x00000000
+#define DDRSS3_PHY_82_DATA 0x00000000
+#define DDRSS3_PHY_83_DATA 0x00000100
+#define DDRSS3_PHY_84_DATA 0x01CC0C01
+#define DDRSS3_PHY_85_DATA 0x1003CC0C
+#define DDRSS3_PHY_86_DATA 0x20000140
+#define DDRSS3_PHY_87_DATA 0x07FF0200
+#define DDRSS3_PHY_88_DATA 0x0000DD01
+#define DDRSS3_PHY_89_DATA 0x10100303
+#define DDRSS3_PHY_90_DATA 0x10101010
+#define DDRSS3_PHY_91_DATA 0x10101010
+#define DDRSS3_PHY_92_DATA 0x00021010
+#define DDRSS3_PHY_93_DATA 0x00100010
+#define DDRSS3_PHY_94_DATA 0x00100010
+#define DDRSS3_PHY_95_DATA 0x00100010
+#define DDRSS3_PHY_96_DATA 0x00100010
+#define DDRSS3_PHY_97_DATA 0x00050010
+#define DDRSS3_PHY_98_DATA 0x51517041
+#define DDRSS3_PHY_99_DATA 0x31C06001
+#define DDRSS3_PHY_100_DATA 0x07AB01AB
+#define DDRSS3_PHY_101_DATA 0x00C0C001
+#define DDRSS3_PHY_102_DATA 0x0E0D0101
+#define DDRSS3_PHY_103_DATA 0x10001000
+#define DDRSS3_PHY_104_DATA 0x0C083E42
+#define DDRSS3_PHY_105_DATA 0x0F0C3701
+#define DDRSS3_PHY_106_DATA 0x01000140
+#define DDRSS3_PHY_107_DATA 0x0C000420
+#define DDRSS3_PHY_108_DATA 0x00000198
+#define DDRSS3_PHY_109_DATA 0x0A0000D0
+#define DDRSS3_PHY_110_DATA 0x00030200
+#define DDRSS3_PHY_111_DATA 0x02800000
+#define DDRSS3_PHY_112_DATA 0x80800000
+#define DDRSS3_PHY_113_DATA 0x000E2010
+#define DDRSS3_PHY_114_DATA 0x76543210
+#define DDRSS3_PHY_115_DATA 0x00000008
+#define DDRSS3_PHY_116_DATA 0x02800280
+#define DDRSS3_PHY_117_DATA 0x02800280
+#define DDRSS3_PHY_118_DATA 0x02800280
+#define DDRSS3_PHY_119_DATA 0x02800280
+#define DDRSS3_PHY_120_DATA 0x00000280
+#define DDRSS3_PHY_121_DATA 0x0000A000
+#define DDRSS3_PHY_122_DATA 0x00A000A0
+#define DDRSS3_PHY_123_DATA 0x00A000A0
+#define DDRSS3_PHY_124_DATA 0x00A000A0
+#define DDRSS3_PHY_125_DATA 0x00A000A0
+#define DDRSS3_PHY_126_DATA 0x00A000A0
+#define DDRSS3_PHY_127_DATA 0x00A000A0
+#define DDRSS3_PHY_128_DATA 0x00A000A0
+#define DDRSS3_PHY_129_DATA 0x00A000A0
+#define DDRSS3_PHY_130_DATA 0x01C200A0
+#define DDRSS3_PHY_131_DATA 0x01A00005
+#define DDRSS3_PHY_132_DATA 0x00000000
+#define DDRSS3_PHY_133_DATA 0x00000000
+#define DDRSS3_PHY_134_DATA 0x00080200
+#define DDRSS3_PHY_135_DATA 0x00000000
+#define DDRSS3_PHY_136_DATA 0x20202000
+#define DDRSS3_PHY_137_DATA 0x20202020
+#define DDRSS3_PHY_138_DATA 0xF0F02020
+#define DDRSS3_PHY_139_DATA 0x00000000
+#define DDRSS3_PHY_140_DATA 0x00000000
+#define DDRSS3_PHY_141_DATA 0x00000000
+#define DDRSS3_PHY_142_DATA 0x00000000
+#define DDRSS3_PHY_143_DATA 0x00000000
+#define DDRSS3_PHY_144_DATA 0x00000000
+#define DDRSS3_PHY_145_DATA 0x00000000
+#define DDRSS3_PHY_146_DATA 0x00000000
+#define DDRSS3_PHY_147_DATA 0x00000000
+#define DDRSS3_PHY_148_DATA 0x00000000
+#define DDRSS3_PHY_149_DATA 0x00000000
+#define DDRSS3_PHY_150_DATA 0x00000000
+#define DDRSS3_PHY_151_DATA 0x00000000
+#define DDRSS3_PHY_152_DATA 0x00000000
+#define DDRSS3_PHY_153_DATA 0x00000000
+#define DDRSS3_PHY_154_DATA 0x00000000
+#define DDRSS3_PHY_155_DATA 0x00000000
+#define DDRSS3_PHY_156_DATA 0x00000000
+#define DDRSS3_PHY_157_DATA 0x00000000
+#define DDRSS3_PHY_158_DATA 0x00000000
+#define DDRSS3_PHY_159_DATA 0x00000000
+#define DDRSS3_PHY_160_DATA 0x00000000
+#define DDRSS3_PHY_161_DATA 0x00000000
+#define DDRSS3_PHY_162_DATA 0x00000000
+#define DDRSS3_PHY_163_DATA 0x00000000
+#define DDRSS3_PHY_164_DATA 0x00000000
+#define DDRSS3_PHY_165_DATA 0x00000000
+#define DDRSS3_PHY_166_DATA 0x00000000
+#define DDRSS3_PHY_167_DATA 0x00000000
+#define DDRSS3_PHY_168_DATA 0x00000000
+#define DDRSS3_PHY_169_DATA 0x00000000
+#define DDRSS3_PHY_170_DATA 0x00000000
+#define DDRSS3_PHY_171_DATA 0x00000000
+#define DDRSS3_PHY_172_DATA 0x00000000
+#define DDRSS3_PHY_173_DATA 0x00000000
+#define DDRSS3_PHY_174_DATA 0x00000000
+#define DDRSS3_PHY_175_DATA 0x00000000
+#define DDRSS3_PHY_176_DATA 0x00000000
+#define DDRSS3_PHY_177_DATA 0x00000000
+#define DDRSS3_PHY_178_DATA 0x00000000
+#define DDRSS3_PHY_179_DATA 0x00000000
+#define DDRSS3_PHY_180_DATA 0x00000000
+#define DDRSS3_PHY_181_DATA 0x00000000
+#define DDRSS3_PHY_182_DATA 0x00000000
+#define DDRSS3_PHY_183_DATA 0x00000000
+#define DDRSS3_PHY_184_DATA 0x00000000
+#define DDRSS3_PHY_185_DATA 0x00000000
+#define DDRSS3_PHY_186_DATA 0x00000000
+#define DDRSS3_PHY_187_DATA 0x00000000
+#define DDRSS3_PHY_188_DATA 0x00000000
+#define DDRSS3_PHY_189_DATA 0x00000000
+#define DDRSS3_PHY_190_DATA 0x00000000
+#define DDRSS3_PHY_191_DATA 0x00000000
+#define DDRSS3_PHY_192_DATA 0x00000000
+#define DDRSS3_PHY_193_DATA 0x00000000
+#define DDRSS3_PHY_194_DATA 0x00000000
+#define DDRSS3_PHY_195_DATA 0x00000000
+#define DDRSS3_PHY_196_DATA 0x00000000
+#define DDRSS3_PHY_197_DATA 0x00000000
+#define DDRSS3_PHY_198_DATA 0x00000000
+#define DDRSS3_PHY_199_DATA 0x00000000
+#define DDRSS3_PHY_200_DATA 0x00000000
+#define DDRSS3_PHY_201_DATA 0x00000000
+#define DDRSS3_PHY_202_DATA 0x00000000
+#define DDRSS3_PHY_203_DATA 0x00000000
+#define DDRSS3_PHY_204_DATA 0x00000000
+#define DDRSS3_PHY_205_DATA 0x00000000
+#define DDRSS3_PHY_206_DATA 0x00000000
+#define DDRSS3_PHY_207_DATA 0x00000000
+#define DDRSS3_PHY_208_DATA 0x00000000
+#define DDRSS3_PHY_209_DATA 0x00000000
+#define DDRSS3_PHY_210_DATA 0x00000000
+#define DDRSS3_PHY_211_DATA 0x00000000
+#define DDRSS3_PHY_212_DATA 0x00000000
+#define DDRSS3_PHY_213_DATA 0x00000000
+#define DDRSS3_PHY_214_DATA 0x00000000
+#define DDRSS3_PHY_215_DATA 0x00000000
+#define DDRSS3_PHY_216_DATA 0x00000000
+#define DDRSS3_PHY_217_DATA 0x00000000
+#define DDRSS3_PHY_218_DATA 0x00000000
+#define DDRSS3_PHY_219_DATA 0x00000000
+#define DDRSS3_PHY_220_DATA 0x00000000
+#define DDRSS3_PHY_221_DATA 0x00000000
+#define DDRSS3_PHY_222_DATA 0x00000000
+#define DDRSS3_PHY_223_DATA 0x00000000
+#define DDRSS3_PHY_224_DATA 0x00000000
+#define DDRSS3_PHY_225_DATA 0x00000000
+#define DDRSS3_PHY_226_DATA 0x00000000
+#define DDRSS3_PHY_227_DATA 0x00000000
+#define DDRSS3_PHY_228_DATA 0x00000000
+#define DDRSS3_PHY_229_DATA 0x00000000
+#define DDRSS3_PHY_230_DATA 0x00000000
+#define DDRSS3_PHY_231_DATA 0x00000000
+#define DDRSS3_PHY_232_DATA 0x00000000
+#define DDRSS3_PHY_233_DATA 0x00000000
+#define DDRSS3_PHY_234_DATA 0x00000000
+#define DDRSS3_PHY_235_DATA 0x00000000
+#define DDRSS3_PHY_236_DATA 0x00000000
+#define DDRSS3_PHY_237_DATA 0x00000000
+#define DDRSS3_PHY_238_DATA 0x00000000
+#define DDRSS3_PHY_239_DATA 0x00000000
+#define DDRSS3_PHY_240_DATA 0x00000000
+#define DDRSS3_PHY_241_DATA 0x00000000
+#define DDRSS3_PHY_242_DATA 0x00000000
+#define DDRSS3_PHY_243_DATA 0x00000000
+#define DDRSS3_PHY_244_DATA 0x00000000
+#define DDRSS3_PHY_245_DATA 0x00000000
+#define DDRSS3_PHY_246_DATA 0x00000000
+#define DDRSS3_PHY_247_DATA 0x00000000
+#define DDRSS3_PHY_248_DATA 0x00000000
+#define DDRSS3_PHY_249_DATA 0x00000000
+#define DDRSS3_PHY_250_DATA 0x00000000
+#define DDRSS3_PHY_251_DATA 0x00000000
+#define DDRSS3_PHY_252_DATA 0x00000000
+#define DDRSS3_PHY_253_DATA 0x00000000
+#define DDRSS3_PHY_254_DATA 0x00000000
+#define DDRSS3_PHY_255_DATA 0x00000000
+#define DDRSS3_PHY_256_DATA 0x000004F0
+#define DDRSS3_PHY_257_DATA 0x00000000
+#define DDRSS3_PHY_258_DATA 0x00030200
+#define DDRSS3_PHY_259_DATA 0x00000000
+#define DDRSS3_PHY_260_DATA 0x00000000
+#define DDRSS3_PHY_261_DATA 0x01030000
+#define DDRSS3_PHY_262_DATA 0x00010000
+#define DDRSS3_PHY_263_DATA 0x01030004
+#define DDRSS3_PHY_264_DATA 0x01000000
+#define DDRSS3_PHY_265_DATA 0x00000000
+#define DDRSS3_PHY_266_DATA 0x00000000
+#define DDRSS3_PHY_267_DATA 0x01000001
+#define DDRSS3_PHY_268_DATA 0x00000200
+#define DDRSS3_PHY_269_DATA 0x000800C0
+#define DDRSS3_PHY_270_DATA 0x060100CC
+#define DDRSS3_PHY_271_DATA 0x00030066
+#define DDRSS3_PHY_272_DATA 0x00000000
+#define DDRSS3_PHY_273_DATA 0x00000301
+#define DDRSS3_PHY_274_DATA 0x0000AAAA
+#define DDRSS3_PHY_275_DATA 0x00005555
+#define DDRSS3_PHY_276_DATA 0x0000B5B5
+#define DDRSS3_PHY_277_DATA 0x00004A4A
+#define DDRSS3_PHY_278_DATA 0x00005656
+#define DDRSS3_PHY_279_DATA 0x0000A9A9
+#define DDRSS3_PHY_280_DATA 0x0000A9A9
+#define DDRSS3_PHY_281_DATA 0x0000B5B5
+#define DDRSS3_PHY_282_DATA 0x00000000
+#define DDRSS3_PHY_283_DATA 0x00000000
+#define DDRSS3_PHY_284_DATA 0x2A000000
+#define DDRSS3_PHY_285_DATA 0x00000808
+#define DDRSS3_PHY_286_DATA 0x0F000000
+#define DDRSS3_PHY_287_DATA 0x00000F08
+#define DDRSS3_PHY_288_DATA 0x10400000
+#define DDRSS3_PHY_289_DATA 0x0C002006
+#define DDRSS3_PHY_290_DATA 0x00000000
+#define DDRSS3_PHY_291_DATA 0x00000000
+#define DDRSS3_PHY_292_DATA 0x55555555
+#define DDRSS3_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_294_DATA 0x55555555
+#define DDRSS3_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_296_DATA 0x00005555
+#define DDRSS3_PHY_297_DATA 0x01000100
+#define DDRSS3_PHY_298_DATA 0x00800180
+#define DDRSS3_PHY_299_DATA 0x00000000
+#define DDRSS3_PHY_300_DATA 0x00000000
+#define DDRSS3_PHY_301_DATA 0x00000000
+#define DDRSS3_PHY_302_DATA 0x00000000
+#define DDRSS3_PHY_303_DATA 0x00000000
+#define DDRSS3_PHY_304_DATA 0x00000000
+#define DDRSS3_PHY_305_DATA 0x00000000
+#define DDRSS3_PHY_306_DATA 0x00000000
+#define DDRSS3_PHY_307_DATA 0x00000000
+#define DDRSS3_PHY_308_DATA 0x00000000
+#define DDRSS3_PHY_309_DATA 0x00000000
+#define DDRSS3_PHY_310_DATA 0x00000000
+#define DDRSS3_PHY_311_DATA 0x00000000
+#define DDRSS3_PHY_312_DATA 0x00000000
+#define DDRSS3_PHY_313_DATA 0x00000000
+#define DDRSS3_PHY_314_DATA 0x00000000
+#define DDRSS3_PHY_315_DATA 0x00000000
+#define DDRSS3_PHY_316_DATA 0x00000000
+#define DDRSS3_PHY_317_DATA 0x00000000
+#define DDRSS3_PHY_318_DATA 0x00000000
+#define DDRSS3_PHY_319_DATA 0x00000000
+#define DDRSS3_PHY_320_DATA 0x00000000
+#define DDRSS3_PHY_321_DATA 0x00000000
+#define DDRSS3_PHY_322_DATA 0x00000104
+#define DDRSS3_PHY_323_DATA 0x00000120
+#define DDRSS3_PHY_324_DATA 0x00000000
+#define DDRSS3_PHY_325_DATA 0x00000000
+#define DDRSS3_PHY_326_DATA 0x00000000
+#define DDRSS3_PHY_327_DATA 0x00000000
+#define DDRSS3_PHY_328_DATA 0x00000000
+#define DDRSS3_PHY_329_DATA 0x00000000
+#define DDRSS3_PHY_330_DATA 0x00000000
+#define DDRSS3_PHY_331_DATA 0x00000001
+#define DDRSS3_PHY_332_DATA 0x07FF0000
+#define DDRSS3_PHY_333_DATA 0x0080081F
+#define DDRSS3_PHY_334_DATA 0x00081020
+#define DDRSS3_PHY_335_DATA 0x04010000
+#define DDRSS3_PHY_336_DATA 0x00000000
+#define DDRSS3_PHY_337_DATA 0x00000000
+#define DDRSS3_PHY_338_DATA 0x00000000
+#define DDRSS3_PHY_339_DATA 0x00000100
+#define DDRSS3_PHY_340_DATA 0x01CC0C01
+#define DDRSS3_PHY_341_DATA 0x1003CC0C
+#define DDRSS3_PHY_342_DATA 0x20000140
+#define DDRSS3_PHY_343_DATA 0x07FF0200
+#define DDRSS3_PHY_344_DATA 0x0000DD01
+#define DDRSS3_PHY_345_DATA 0x10100303
+#define DDRSS3_PHY_346_DATA 0x10101010
+#define DDRSS3_PHY_347_DATA 0x10101010
+#define DDRSS3_PHY_348_DATA 0x00021010
+#define DDRSS3_PHY_349_DATA 0x00100010
+#define DDRSS3_PHY_350_DATA 0x00100010
+#define DDRSS3_PHY_351_DATA 0x00100010
+#define DDRSS3_PHY_352_DATA 0x00100010
+#define DDRSS3_PHY_353_DATA 0x00050010
+#define DDRSS3_PHY_354_DATA 0x51517041
+#define DDRSS3_PHY_355_DATA 0x31C06001
+#define DDRSS3_PHY_356_DATA 0x07AB01AB
+#define DDRSS3_PHY_357_DATA 0x00C0C001
+#define DDRSS3_PHY_358_DATA 0x0E0D0101
+#define DDRSS3_PHY_359_DATA 0x10001000
+#define DDRSS3_PHY_360_DATA 0x0C083E42
+#define DDRSS3_PHY_361_DATA 0x0F0C3701
+#define DDRSS3_PHY_362_DATA 0x01000140
+#define DDRSS3_PHY_363_DATA 0x0C000420
+#define DDRSS3_PHY_364_DATA 0x00000198
+#define DDRSS3_PHY_365_DATA 0x0A0000D0
+#define DDRSS3_PHY_366_DATA 0x00030200
+#define DDRSS3_PHY_367_DATA 0x02800000
+#define DDRSS3_PHY_368_DATA 0x80800000
+#define DDRSS3_PHY_369_DATA 0x000E2010
+#define DDRSS3_PHY_370_DATA 0x76543210
+#define DDRSS3_PHY_371_DATA 0x00000008
+#define DDRSS3_PHY_372_DATA 0x02800280
+#define DDRSS3_PHY_373_DATA 0x02800280
+#define DDRSS3_PHY_374_DATA 0x02800280
+#define DDRSS3_PHY_375_DATA 0x02800280
+#define DDRSS3_PHY_376_DATA 0x00000280
+#define DDRSS3_PHY_377_DATA 0x0000A000
+#define DDRSS3_PHY_378_DATA 0x00A000A0
+#define DDRSS3_PHY_379_DATA 0x00A000A0
+#define DDRSS3_PHY_380_DATA 0x00A000A0
+#define DDRSS3_PHY_381_DATA 0x00A000A0
+#define DDRSS3_PHY_382_DATA 0x00A000A0
+#define DDRSS3_PHY_383_DATA 0x00A000A0
+#define DDRSS3_PHY_384_DATA 0x00A000A0
+#define DDRSS3_PHY_385_DATA 0x00A000A0
+#define DDRSS3_PHY_386_DATA 0x01C200A0
+#define DDRSS3_PHY_387_DATA 0x01A00005
+#define DDRSS3_PHY_388_DATA 0x00000000
+#define DDRSS3_PHY_389_DATA 0x00000000
+#define DDRSS3_PHY_390_DATA 0x00080200
+#define DDRSS3_PHY_391_DATA 0x00000000
+#define DDRSS3_PHY_392_DATA 0x20202000
+#define DDRSS3_PHY_393_DATA 0x20202020
+#define DDRSS3_PHY_394_DATA 0xF0F02020
+#define DDRSS3_PHY_395_DATA 0x00000000
+#define DDRSS3_PHY_396_DATA 0x00000000
+#define DDRSS3_PHY_397_DATA 0x00000000
+#define DDRSS3_PHY_398_DATA 0x00000000
+#define DDRSS3_PHY_399_DATA 0x00000000
+#define DDRSS3_PHY_400_DATA 0x00000000
+#define DDRSS3_PHY_401_DATA 0x00000000
+#define DDRSS3_PHY_402_DATA 0x00000000
+#define DDRSS3_PHY_403_DATA 0x00000000
+#define DDRSS3_PHY_404_DATA 0x00000000
+#define DDRSS3_PHY_405_DATA 0x00000000
+#define DDRSS3_PHY_406_DATA 0x00000000
+#define DDRSS3_PHY_407_DATA 0x00000000
+#define DDRSS3_PHY_408_DATA 0x00000000
+#define DDRSS3_PHY_409_DATA 0x00000000
+#define DDRSS3_PHY_410_DATA 0x00000000
+#define DDRSS3_PHY_411_DATA 0x00000000
+#define DDRSS3_PHY_412_DATA 0x00000000
+#define DDRSS3_PHY_413_DATA 0x00000000
+#define DDRSS3_PHY_414_DATA 0x00000000
+#define DDRSS3_PHY_415_DATA 0x00000000
+#define DDRSS3_PHY_416_DATA 0x00000000
+#define DDRSS3_PHY_417_DATA 0x00000000
+#define DDRSS3_PHY_418_DATA 0x00000000
+#define DDRSS3_PHY_419_DATA 0x00000000
+#define DDRSS3_PHY_420_DATA 0x00000000
+#define DDRSS3_PHY_421_DATA 0x00000000
+#define DDRSS3_PHY_422_DATA 0x00000000
+#define DDRSS3_PHY_423_DATA 0x00000000
+#define DDRSS3_PHY_424_DATA 0x00000000
+#define DDRSS3_PHY_425_DATA 0x00000000
+#define DDRSS3_PHY_426_DATA 0x00000000
+#define DDRSS3_PHY_427_DATA 0x00000000
+#define DDRSS3_PHY_428_DATA 0x00000000
+#define DDRSS3_PHY_429_DATA 0x00000000
+#define DDRSS3_PHY_430_DATA 0x00000000
+#define DDRSS3_PHY_431_DATA 0x00000000
+#define DDRSS3_PHY_432_DATA 0x00000000
+#define DDRSS3_PHY_433_DATA 0x00000000
+#define DDRSS3_PHY_434_DATA 0x00000000
+#define DDRSS3_PHY_435_DATA 0x00000000
+#define DDRSS3_PHY_436_DATA 0x00000000
+#define DDRSS3_PHY_437_DATA 0x00000000
+#define DDRSS3_PHY_438_DATA 0x00000000
+#define DDRSS3_PHY_439_DATA 0x00000000
+#define DDRSS3_PHY_440_DATA 0x00000000
+#define DDRSS3_PHY_441_DATA 0x00000000
+#define DDRSS3_PHY_442_DATA 0x00000000
+#define DDRSS3_PHY_443_DATA 0x00000000
+#define DDRSS3_PHY_444_DATA 0x00000000
+#define DDRSS3_PHY_445_DATA 0x00000000
+#define DDRSS3_PHY_446_DATA 0x00000000
+#define DDRSS3_PHY_447_DATA 0x00000000
+#define DDRSS3_PHY_448_DATA 0x00000000
+#define DDRSS3_PHY_449_DATA 0x00000000
+#define DDRSS3_PHY_450_DATA 0x00000000
+#define DDRSS3_PHY_451_DATA 0x00000000
+#define DDRSS3_PHY_452_DATA 0x00000000
+#define DDRSS3_PHY_453_DATA 0x00000000
+#define DDRSS3_PHY_454_DATA 0x00000000
+#define DDRSS3_PHY_455_DATA 0x00000000
+#define DDRSS3_PHY_456_DATA 0x00000000
+#define DDRSS3_PHY_457_DATA 0x00000000
+#define DDRSS3_PHY_458_DATA 0x00000000
+#define DDRSS3_PHY_459_DATA 0x00000000
+#define DDRSS3_PHY_460_DATA 0x00000000
+#define DDRSS3_PHY_461_DATA 0x00000000
+#define DDRSS3_PHY_462_DATA 0x00000000
+#define DDRSS3_PHY_463_DATA 0x00000000
+#define DDRSS3_PHY_464_DATA 0x00000000
+#define DDRSS3_PHY_465_DATA 0x00000000
+#define DDRSS3_PHY_466_DATA 0x00000000
+#define DDRSS3_PHY_467_DATA 0x00000000
+#define DDRSS3_PHY_468_DATA 0x00000000
+#define DDRSS3_PHY_469_DATA 0x00000000
+#define DDRSS3_PHY_470_DATA 0x00000000
+#define DDRSS3_PHY_471_DATA 0x00000000
+#define DDRSS3_PHY_472_DATA 0x00000000
+#define DDRSS3_PHY_473_DATA 0x00000000
+#define DDRSS3_PHY_474_DATA 0x00000000
+#define DDRSS3_PHY_475_DATA 0x00000000
+#define DDRSS3_PHY_476_DATA 0x00000000
+#define DDRSS3_PHY_477_DATA 0x00000000
+#define DDRSS3_PHY_478_DATA 0x00000000
+#define DDRSS3_PHY_479_DATA 0x00000000
+#define DDRSS3_PHY_480_DATA 0x00000000
+#define DDRSS3_PHY_481_DATA 0x00000000
+#define DDRSS3_PHY_482_DATA 0x00000000
+#define DDRSS3_PHY_483_DATA 0x00000000
+#define DDRSS3_PHY_484_DATA 0x00000000
+#define DDRSS3_PHY_485_DATA 0x00000000
+#define DDRSS3_PHY_486_DATA 0x00000000
+#define DDRSS3_PHY_487_DATA 0x00000000
+#define DDRSS3_PHY_488_DATA 0x00000000
+#define DDRSS3_PHY_489_DATA 0x00000000
+#define DDRSS3_PHY_490_DATA 0x00000000
+#define DDRSS3_PHY_491_DATA 0x00000000
+#define DDRSS3_PHY_492_DATA 0x00000000
+#define DDRSS3_PHY_493_DATA 0x00000000
+#define DDRSS3_PHY_494_DATA 0x00000000
+#define DDRSS3_PHY_495_DATA 0x00000000
+#define DDRSS3_PHY_496_DATA 0x00000000
+#define DDRSS3_PHY_497_DATA 0x00000000
+#define DDRSS3_PHY_498_DATA 0x00000000
+#define DDRSS3_PHY_499_DATA 0x00000000
+#define DDRSS3_PHY_500_DATA 0x00000000
+#define DDRSS3_PHY_501_DATA 0x00000000
+#define DDRSS3_PHY_502_DATA 0x00000000
+#define DDRSS3_PHY_503_DATA 0x00000000
+#define DDRSS3_PHY_504_DATA 0x00000000
+#define DDRSS3_PHY_505_DATA 0x00000000
+#define DDRSS3_PHY_506_DATA 0x00000000
+#define DDRSS3_PHY_507_DATA 0x00000000
+#define DDRSS3_PHY_508_DATA 0x00000000
+#define DDRSS3_PHY_509_DATA 0x00000000
+#define DDRSS3_PHY_510_DATA 0x00000000
+#define DDRSS3_PHY_511_DATA 0x00000000
+#define DDRSS3_PHY_512_DATA 0x000004F0
+#define DDRSS3_PHY_513_DATA 0x00000000
+#define DDRSS3_PHY_514_DATA 0x00030200
+#define DDRSS3_PHY_515_DATA 0x00000000
+#define DDRSS3_PHY_516_DATA 0x00000000
+#define DDRSS3_PHY_517_DATA 0x01030000
+#define DDRSS3_PHY_518_DATA 0x00010000
+#define DDRSS3_PHY_519_DATA 0x01030004
+#define DDRSS3_PHY_520_DATA 0x01000000
+#define DDRSS3_PHY_521_DATA 0x00000000
+#define DDRSS3_PHY_522_DATA 0x00000000
+#define DDRSS3_PHY_523_DATA 0x01000001
+#define DDRSS3_PHY_524_DATA 0x00000200
+#define DDRSS3_PHY_525_DATA 0x000800C0
+#define DDRSS3_PHY_526_DATA 0x060100CC
+#define DDRSS3_PHY_527_DATA 0x00030066
+#define DDRSS3_PHY_528_DATA 0x00000000
+#define DDRSS3_PHY_529_DATA 0x00000301
+#define DDRSS3_PHY_530_DATA 0x0000AAAA
+#define DDRSS3_PHY_531_DATA 0x00005555
+#define DDRSS3_PHY_532_DATA 0x0000B5B5
+#define DDRSS3_PHY_533_DATA 0x00004A4A
+#define DDRSS3_PHY_534_DATA 0x00005656
+#define DDRSS3_PHY_535_DATA 0x0000A9A9
+#define DDRSS3_PHY_536_DATA 0x0000A9A9
+#define DDRSS3_PHY_537_DATA 0x0000B5B5
+#define DDRSS3_PHY_538_DATA 0x00000000
+#define DDRSS3_PHY_539_DATA 0x00000000
+#define DDRSS3_PHY_540_DATA 0x2A000000
+#define DDRSS3_PHY_541_DATA 0x00000808
+#define DDRSS3_PHY_542_DATA 0x0F000000
+#define DDRSS3_PHY_543_DATA 0x00000F08
+#define DDRSS3_PHY_544_DATA 0x10400000
+#define DDRSS3_PHY_545_DATA 0x0C002006
+#define DDRSS3_PHY_546_DATA 0x00000000
+#define DDRSS3_PHY_547_DATA 0x00000000
+#define DDRSS3_PHY_548_DATA 0x55555555
+#define DDRSS3_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_550_DATA 0x55555555
+#define DDRSS3_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_552_DATA 0x00005555
+#define DDRSS3_PHY_553_DATA 0x01000100
+#define DDRSS3_PHY_554_DATA 0x00800180
+#define DDRSS3_PHY_555_DATA 0x00000001
+#define DDRSS3_PHY_556_DATA 0x00000000
+#define DDRSS3_PHY_557_DATA 0x00000000
+#define DDRSS3_PHY_558_DATA 0x00000000
+#define DDRSS3_PHY_559_DATA 0x00000000
+#define DDRSS3_PHY_560_DATA 0x00000000
+#define DDRSS3_PHY_561_DATA 0x00000000
+#define DDRSS3_PHY_562_DATA 0x00000000
+#define DDRSS3_PHY_563_DATA 0x00000000
+#define DDRSS3_PHY_564_DATA 0x00000000
+#define DDRSS3_PHY_565_DATA 0x00000000
+#define DDRSS3_PHY_566_DATA 0x00000000
+#define DDRSS3_PHY_567_DATA 0x00000000
+#define DDRSS3_PHY_568_DATA 0x00000000
+#define DDRSS3_PHY_569_DATA 0x00000000
+#define DDRSS3_PHY_570_DATA 0x00000000
+#define DDRSS3_PHY_571_DATA 0x00000000
+#define DDRSS3_PHY_572_DATA 0x00000000
+#define DDRSS3_PHY_573_DATA 0x00000000
+#define DDRSS3_PHY_574_DATA 0x00000000
+#define DDRSS3_PHY_575_DATA 0x00000000
+#define DDRSS3_PHY_576_DATA 0x00000000
+#define DDRSS3_PHY_577_DATA 0x00000000
+#define DDRSS3_PHY_578_DATA 0x00000104
+#define DDRSS3_PHY_579_DATA 0x00000120
+#define DDRSS3_PHY_580_DATA 0x00000000
+#define DDRSS3_PHY_581_DATA 0x00000000
+#define DDRSS3_PHY_582_DATA 0x00000000
+#define DDRSS3_PHY_583_DATA 0x00000000
+#define DDRSS3_PHY_584_DATA 0x00000000
+#define DDRSS3_PHY_585_DATA 0x00000000
+#define DDRSS3_PHY_586_DATA 0x00000000
+#define DDRSS3_PHY_587_DATA 0x00000001
+#define DDRSS3_PHY_588_DATA 0x07FF0000
+#define DDRSS3_PHY_589_DATA 0x0080081F
+#define DDRSS3_PHY_590_DATA 0x00081020
+#define DDRSS3_PHY_591_DATA 0x04010000
+#define DDRSS3_PHY_592_DATA 0x00000000
+#define DDRSS3_PHY_593_DATA 0x00000000
+#define DDRSS3_PHY_594_DATA 0x00000000
+#define DDRSS3_PHY_595_DATA 0x00000100
+#define DDRSS3_PHY_596_DATA 0x01CC0C01
+#define DDRSS3_PHY_597_DATA 0x1003CC0C
+#define DDRSS3_PHY_598_DATA 0x20000140
+#define DDRSS3_PHY_599_DATA 0x07FF0200
+#define DDRSS3_PHY_600_DATA 0x0000DD01
+#define DDRSS3_PHY_601_DATA 0x10100303
+#define DDRSS3_PHY_602_DATA 0x10101010
+#define DDRSS3_PHY_603_DATA 0x10101010
+#define DDRSS3_PHY_604_DATA 0x00021010
+#define DDRSS3_PHY_605_DATA 0x00100010
+#define DDRSS3_PHY_606_DATA 0x00100010
+#define DDRSS3_PHY_607_DATA 0x00100010
+#define DDRSS3_PHY_608_DATA 0x00100010
+#define DDRSS3_PHY_609_DATA 0x00050010
+#define DDRSS3_PHY_610_DATA 0x51517041
+#define DDRSS3_PHY_611_DATA 0x31C06001
+#define DDRSS3_PHY_612_DATA 0x07AB01AB
+#define DDRSS3_PHY_613_DATA 0x00C0C001
+#define DDRSS3_PHY_614_DATA 0x0E0D0101
+#define DDRSS3_PHY_615_DATA 0x10001000
+#define DDRSS3_PHY_616_DATA 0x0C083E42
+#define DDRSS3_PHY_617_DATA 0x0F0C3701
+#define DDRSS3_PHY_618_DATA 0x01000140
+#define DDRSS3_PHY_619_DATA 0x0C000420
+#define DDRSS3_PHY_620_DATA 0x00000198
+#define DDRSS3_PHY_621_DATA 0x0A0000D0
+#define DDRSS3_PHY_622_DATA 0x00030200
+#define DDRSS3_PHY_623_DATA 0x02800000
+#define DDRSS3_PHY_624_DATA 0x80800000
+#define DDRSS3_PHY_625_DATA 0x000E2010
+#define DDRSS3_PHY_626_DATA 0x76543210
+#define DDRSS3_PHY_627_DATA 0x00000008
+#define DDRSS3_PHY_628_DATA 0x02800280
+#define DDRSS3_PHY_629_DATA 0x02800280
+#define DDRSS3_PHY_630_DATA 0x02800280
+#define DDRSS3_PHY_631_DATA 0x02800280
+#define DDRSS3_PHY_632_DATA 0x00000280
+#define DDRSS3_PHY_633_DATA 0x0000A000
+#define DDRSS3_PHY_634_DATA 0x00A000A0
+#define DDRSS3_PHY_635_DATA 0x00A000A0
+#define DDRSS3_PHY_636_DATA 0x00A000A0
+#define DDRSS3_PHY_637_DATA 0x00A000A0
+#define DDRSS3_PHY_638_DATA 0x00A000A0
+#define DDRSS3_PHY_639_DATA 0x00A000A0
+#define DDRSS3_PHY_640_DATA 0x00A000A0
+#define DDRSS3_PHY_641_DATA 0x00A000A0
+#define DDRSS3_PHY_642_DATA 0x01C200A0
+#define DDRSS3_PHY_643_DATA 0x01A00005
+#define DDRSS3_PHY_644_DATA 0x00000000
+#define DDRSS3_PHY_645_DATA 0x00000000
+#define DDRSS3_PHY_646_DATA 0x00080200
+#define DDRSS3_PHY_647_DATA 0x00000000
+#define DDRSS3_PHY_648_DATA 0x20202000
+#define DDRSS3_PHY_649_DATA 0x20202020
+#define DDRSS3_PHY_650_DATA 0xF0F02020
+#define DDRSS3_PHY_651_DATA 0x00000000
+#define DDRSS3_PHY_652_DATA 0x00000000
+#define DDRSS3_PHY_653_DATA 0x00000000
+#define DDRSS3_PHY_654_DATA 0x00000000
+#define DDRSS3_PHY_655_DATA 0x00000000
+#define DDRSS3_PHY_656_DATA 0x00000000
+#define DDRSS3_PHY_657_DATA 0x00000000
+#define DDRSS3_PHY_658_DATA 0x00000000
+#define DDRSS3_PHY_659_DATA 0x00000000
+#define DDRSS3_PHY_660_DATA 0x00000000
+#define DDRSS3_PHY_661_DATA 0x00000000
+#define DDRSS3_PHY_662_DATA 0x00000000
+#define DDRSS3_PHY_663_DATA 0x00000000
+#define DDRSS3_PHY_664_DATA 0x00000000
+#define DDRSS3_PHY_665_DATA 0x00000000
+#define DDRSS3_PHY_666_DATA 0x00000000
+#define DDRSS3_PHY_667_DATA 0x00000000
+#define DDRSS3_PHY_668_DATA 0x00000000
+#define DDRSS3_PHY_669_DATA 0x00000000
+#define DDRSS3_PHY_670_DATA 0x00000000
+#define DDRSS3_PHY_671_DATA 0x00000000
+#define DDRSS3_PHY_672_DATA 0x00000000
+#define DDRSS3_PHY_673_DATA 0x00000000
+#define DDRSS3_PHY_674_DATA 0x00000000
+#define DDRSS3_PHY_675_DATA 0x00000000
+#define DDRSS3_PHY_676_DATA 0x00000000
+#define DDRSS3_PHY_677_DATA 0x00000000
+#define DDRSS3_PHY_678_DATA 0x00000000
+#define DDRSS3_PHY_679_DATA 0x00000000
+#define DDRSS3_PHY_680_DATA 0x00000000
+#define DDRSS3_PHY_681_DATA 0x00000000
+#define DDRSS3_PHY_682_DATA 0x00000000
+#define DDRSS3_PHY_683_DATA 0x00000000
+#define DDRSS3_PHY_684_DATA 0x00000000
+#define DDRSS3_PHY_685_DATA 0x00000000
+#define DDRSS3_PHY_686_DATA 0x00000000
+#define DDRSS3_PHY_687_DATA 0x00000000
+#define DDRSS3_PHY_688_DATA 0x00000000
+#define DDRSS3_PHY_689_DATA 0x00000000
+#define DDRSS3_PHY_690_DATA 0x00000000
+#define DDRSS3_PHY_691_DATA 0x00000000
+#define DDRSS3_PHY_692_DATA 0x00000000
+#define DDRSS3_PHY_693_DATA 0x00000000
+#define DDRSS3_PHY_694_DATA 0x00000000
+#define DDRSS3_PHY_695_DATA 0x00000000
+#define DDRSS3_PHY_696_DATA 0x00000000
+#define DDRSS3_PHY_697_DATA 0x00000000
+#define DDRSS3_PHY_698_DATA 0x00000000
+#define DDRSS3_PHY_699_DATA 0x00000000
+#define DDRSS3_PHY_700_DATA 0x00000000
+#define DDRSS3_PHY_701_DATA 0x00000000
+#define DDRSS3_PHY_702_DATA 0x00000000
+#define DDRSS3_PHY_703_DATA 0x00000000
+#define DDRSS3_PHY_704_DATA 0x00000000
+#define DDRSS3_PHY_705_DATA 0x00000000
+#define DDRSS3_PHY_706_DATA 0x00000000
+#define DDRSS3_PHY_707_DATA 0x00000000
+#define DDRSS3_PHY_708_DATA 0x00000000
+#define DDRSS3_PHY_709_DATA 0x00000000
+#define DDRSS3_PHY_710_DATA 0x00000000
+#define DDRSS3_PHY_711_DATA 0x00000000
+#define DDRSS3_PHY_712_DATA 0x00000000
+#define DDRSS3_PHY_713_DATA 0x00000000
+#define DDRSS3_PHY_714_DATA 0x00000000
+#define DDRSS3_PHY_715_DATA 0x00000000
+#define DDRSS3_PHY_716_DATA 0x00000000
+#define DDRSS3_PHY_717_DATA 0x00000000
+#define DDRSS3_PHY_718_DATA 0x00000000
+#define DDRSS3_PHY_719_DATA 0x00000000
+#define DDRSS3_PHY_720_DATA 0x00000000
+#define DDRSS3_PHY_721_DATA 0x00000000
+#define DDRSS3_PHY_722_DATA 0x00000000
+#define DDRSS3_PHY_723_DATA 0x00000000
+#define DDRSS3_PHY_724_DATA 0x00000000
+#define DDRSS3_PHY_725_DATA 0x00000000
+#define DDRSS3_PHY_726_DATA 0x00000000
+#define DDRSS3_PHY_727_DATA 0x00000000
+#define DDRSS3_PHY_728_DATA 0x00000000
+#define DDRSS3_PHY_729_DATA 0x00000000
+#define DDRSS3_PHY_730_DATA 0x00000000
+#define DDRSS3_PHY_731_DATA 0x00000000
+#define DDRSS3_PHY_732_DATA 0x00000000
+#define DDRSS3_PHY_733_DATA 0x00000000
+#define DDRSS3_PHY_734_DATA 0x00000000
+#define DDRSS3_PHY_735_DATA 0x00000000
+#define DDRSS3_PHY_736_DATA 0x00000000
+#define DDRSS3_PHY_737_DATA 0x00000000
+#define DDRSS3_PHY_738_DATA 0x00000000
+#define DDRSS3_PHY_739_DATA 0x00000000
+#define DDRSS3_PHY_740_DATA 0x00000000
+#define DDRSS3_PHY_741_DATA 0x00000000
+#define DDRSS3_PHY_742_DATA 0x00000000
+#define DDRSS3_PHY_743_DATA 0x00000000
+#define DDRSS3_PHY_744_DATA 0x00000000
+#define DDRSS3_PHY_745_DATA 0x00000000
+#define DDRSS3_PHY_746_DATA 0x00000000
+#define DDRSS3_PHY_747_DATA 0x00000000
+#define DDRSS3_PHY_748_DATA 0x00000000
+#define DDRSS3_PHY_749_DATA 0x00000000
+#define DDRSS3_PHY_750_DATA 0x00000000
+#define DDRSS3_PHY_751_DATA 0x00000000
+#define DDRSS3_PHY_752_DATA 0x00000000
+#define DDRSS3_PHY_753_DATA 0x00000000
+#define DDRSS3_PHY_754_DATA 0x00000000
+#define DDRSS3_PHY_755_DATA 0x00000000
+#define DDRSS3_PHY_756_DATA 0x00000000
+#define DDRSS3_PHY_757_DATA 0x00000000
+#define DDRSS3_PHY_758_DATA 0x00000000
+#define DDRSS3_PHY_759_DATA 0x00000000
+#define DDRSS3_PHY_760_DATA 0x00000000
+#define DDRSS3_PHY_761_DATA 0x00000000
+#define DDRSS3_PHY_762_DATA 0x00000000
+#define DDRSS3_PHY_763_DATA 0x00000000
+#define DDRSS3_PHY_764_DATA 0x00000000
+#define DDRSS3_PHY_765_DATA 0x00000000
+#define DDRSS3_PHY_766_DATA 0x00000000
+#define DDRSS3_PHY_767_DATA 0x00000000
+#define DDRSS3_PHY_768_DATA 0x000004F0
+#define DDRSS3_PHY_769_DATA 0x00000000
+#define DDRSS3_PHY_770_DATA 0x00030200
+#define DDRSS3_PHY_771_DATA 0x00000000
+#define DDRSS3_PHY_772_DATA 0x00000000
+#define DDRSS3_PHY_773_DATA 0x01030000
+#define DDRSS3_PHY_774_DATA 0x00010000
+#define DDRSS3_PHY_775_DATA 0x01030004
+#define DDRSS3_PHY_776_DATA 0x01000000
+#define DDRSS3_PHY_777_DATA 0x00000000
+#define DDRSS3_PHY_778_DATA 0x00000000
+#define DDRSS3_PHY_779_DATA 0x01000001
+#define DDRSS3_PHY_780_DATA 0x00000200
+#define DDRSS3_PHY_781_DATA 0x000800C0
+#define DDRSS3_PHY_782_DATA 0x060100CC
+#define DDRSS3_PHY_783_DATA 0x00030066
+#define DDRSS3_PHY_784_DATA 0x00000000
+#define DDRSS3_PHY_785_DATA 0x00000301
+#define DDRSS3_PHY_786_DATA 0x0000AAAA
+#define DDRSS3_PHY_787_DATA 0x00005555
+#define DDRSS3_PHY_788_DATA 0x0000B5B5
+#define DDRSS3_PHY_789_DATA 0x00004A4A
+#define DDRSS3_PHY_790_DATA 0x00005656
+#define DDRSS3_PHY_791_DATA 0x0000A9A9
+#define DDRSS3_PHY_792_DATA 0x0000A9A9
+#define DDRSS3_PHY_793_DATA 0x0000B5B5
+#define DDRSS3_PHY_794_DATA 0x00000000
+#define DDRSS3_PHY_795_DATA 0x00000000
+#define DDRSS3_PHY_796_DATA 0x2A000000
+#define DDRSS3_PHY_797_DATA 0x00000808
+#define DDRSS3_PHY_798_DATA 0x0F000000
+#define DDRSS3_PHY_799_DATA 0x00000F08
+#define DDRSS3_PHY_800_DATA 0x10400000
+#define DDRSS3_PHY_801_DATA 0x0C002006
+#define DDRSS3_PHY_802_DATA 0x00000000
+#define DDRSS3_PHY_803_DATA 0x00000000
+#define DDRSS3_PHY_804_DATA 0x55555555
+#define DDRSS3_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_806_DATA 0x55555555
+#define DDRSS3_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_808_DATA 0x00005555
+#define DDRSS3_PHY_809_DATA 0x01000100
+#define DDRSS3_PHY_810_DATA 0x00800180
+#define DDRSS3_PHY_811_DATA 0x00000000
+#define DDRSS3_PHY_812_DATA 0x00000000
+#define DDRSS3_PHY_813_DATA 0x00000000
+#define DDRSS3_PHY_814_DATA 0x00000000
+#define DDRSS3_PHY_815_DATA 0x00000000
+#define DDRSS3_PHY_816_DATA 0x00000000
+#define DDRSS3_PHY_817_DATA 0x00000000
+#define DDRSS3_PHY_818_DATA 0x00000000
+#define DDRSS3_PHY_819_DATA 0x00000000
+#define DDRSS3_PHY_820_DATA 0x00000000
+#define DDRSS3_PHY_821_DATA 0x00000000
+#define DDRSS3_PHY_822_DATA 0x00000000
+#define DDRSS3_PHY_823_DATA 0x00000000
+#define DDRSS3_PHY_824_DATA 0x00000000
+#define DDRSS3_PHY_825_DATA 0x00000000
+#define DDRSS3_PHY_826_DATA 0x00000000
+#define DDRSS3_PHY_827_DATA 0x00000000
+#define DDRSS3_PHY_828_DATA 0x00000000
+#define DDRSS3_PHY_829_DATA 0x00000000
+#define DDRSS3_PHY_830_DATA 0x00000000
+#define DDRSS3_PHY_831_DATA 0x00000000
+#define DDRSS3_PHY_832_DATA 0x00000000
+#define DDRSS3_PHY_833_DATA 0x00000000
+#define DDRSS3_PHY_834_DATA 0x00000104
+#define DDRSS3_PHY_835_DATA 0x00000120
+#define DDRSS3_PHY_836_DATA 0x00000000
+#define DDRSS3_PHY_837_DATA 0x00000000
+#define DDRSS3_PHY_838_DATA 0x00000000
+#define DDRSS3_PHY_839_DATA 0x00000000
+#define DDRSS3_PHY_840_DATA 0x00000000
+#define DDRSS3_PHY_841_DATA 0x00000000
+#define DDRSS3_PHY_842_DATA 0x00000000
+#define DDRSS3_PHY_843_DATA 0x00000001
+#define DDRSS3_PHY_844_DATA 0x07FF0000
+#define DDRSS3_PHY_845_DATA 0x0080081F
+#define DDRSS3_PHY_846_DATA 0x00081020
+#define DDRSS3_PHY_847_DATA 0x04010000
+#define DDRSS3_PHY_848_DATA 0x00000000
+#define DDRSS3_PHY_849_DATA 0x00000000
+#define DDRSS3_PHY_850_DATA 0x00000000
+#define DDRSS3_PHY_851_DATA 0x00000100
+#define DDRSS3_PHY_852_DATA 0x01CC0C01
+#define DDRSS3_PHY_853_DATA 0x1003CC0C
+#define DDRSS3_PHY_854_DATA 0x20000140
+#define DDRSS3_PHY_855_DATA 0x07FF0200
+#define DDRSS3_PHY_856_DATA 0x0000DD01
+#define DDRSS3_PHY_857_DATA 0x10100303
+#define DDRSS3_PHY_858_DATA 0x10101010
+#define DDRSS3_PHY_859_DATA 0x10101010
+#define DDRSS3_PHY_860_DATA 0x00021010
+#define DDRSS3_PHY_861_DATA 0x00100010
+#define DDRSS3_PHY_862_DATA 0x00100010
+#define DDRSS3_PHY_863_DATA 0x00100010
+#define DDRSS3_PHY_864_DATA 0x00100010
+#define DDRSS3_PHY_865_DATA 0x00050010
+#define DDRSS3_PHY_866_DATA 0x51517041
+#define DDRSS3_PHY_867_DATA 0x31C06001
+#define DDRSS3_PHY_868_DATA 0x07AB01AB
+#define DDRSS3_PHY_869_DATA 0x00C0C001
+#define DDRSS3_PHY_870_DATA 0x0E0D0101
+#define DDRSS3_PHY_871_DATA 0x10001000
+#define DDRSS3_PHY_872_DATA 0x0C083E42
+#define DDRSS3_PHY_873_DATA 0x0F0C3701
+#define DDRSS3_PHY_874_DATA 0x01000140
+#define DDRSS3_PHY_875_DATA 0x0C000420
+#define DDRSS3_PHY_876_DATA 0x00000198
+#define DDRSS3_PHY_877_DATA 0x0A0000D0
+#define DDRSS3_PHY_878_DATA 0x00030200
+#define DDRSS3_PHY_879_DATA 0x02800000
+#define DDRSS3_PHY_880_DATA 0x80800000
+#define DDRSS3_PHY_881_DATA 0x000E2010
+#define DDRSS3_PHY_882_DATA 0x76543210
+#define DDRSS3_PHY_883_DATA 0x00000008
+#define DDRSS3_PHY_884_DATA 0x02800280
+#define DDRSS3_PHY_885_DATA 0x02800280
+#define DDRSS3_PHY_886_DATA 0x02800280
+#define DDRSS3_PHY_887_DATA 0x02800280
+#define DDRSS3_PHY_888_DATA 0x00000280
+#define DDRSS3_PHY_889_DATA 0x0000A000
+#define DDRSS3_PHY_890_DATA 0x00A000A0
+#define DDRSS3_PHY_891_DATA 0x00A000A0
+#define DDRSS3_PHY_892_DATA 0x00A000A0
+#define DDRSS3_PHY_893_DATA 0x00A000A0
+#define DDRSS3_PHY_894_DATA 0x00A000A0
+#define DDRSS3_PHY_895_DATA 0x00A000A0
+#define DDRSS3_PHY_896_DATA 0x00A000A0
+#define DDRSS3_PHY_897_DATA 0x00A000A0
+#define DDRSS3_PHY_898_DATA 0x01C200A0
+#define DDRSS3_PHY_899_DATA 0x01A00005
+#define DDRSS3_PHY_900_DATA 0x00000000
+#define DDRSS3_PHY_901_DATA 0x00000000
+#define DDRSS3_PHY_902_DATA 0x00080200
+#define DDRSS3_PHY_903_DATA 0x00000000
+#define DDRSS3_PHY_904_DATA 0x20202000
+#define DDRSS3_PHY_905_DATA 0x20202020
+#define DDRSS3_PHY_906_DATA 0xF0F02020
+#define DDRSS3_PHY_907_DATA 0x00000000
+#define DDRSS3_PHY_908_DATA 0x00000000
+#define DDRSS3_PHY_909_DATA 0x00000000
+#define DDRSS3_PHY_910_DATA 0x00000000
+#define DDRSS3_PHY_911_DATA 0x00000000
+#define DDRSS3_PHY_912_DATA 0x00000000
+#define DDRSS3_PHY_913_DATA 0x00000000
+#define DDRSS3_PHY_914_DATA 0x00000000
+#define DDRSS3_PHY_915_DATA 0x00000000
+#define DDRSS3_PHY_916_DATA 0x00000000
+#define DDRSS3_PHY_917_DATA 0x00000000
+#define DDRSS3_PHY_918_DATA 0x00000000
+#define DDRSS3_PHY_919_DATA 0x00000000
+#define DDRSS3_PHY_920_DATA 0x00000000
+#define DDRSS3_PHY_921_DATA 0x00000000
+#define DDRSS3_PHY_922_DATA 0x00000000
+#define DDRSS3_PHY_923_DATA 0x00000000
+#define DDRSS3_PHY_924_DATA 0x00000000
+#define DDRSS3_PHY_925_DATA 0x00000000
+#define DDRSS3_PHY_926_DATA 0x00000000
+#define DDRSS3_PHY_927_DATA 0x00000000
+#define DDRSS3_PHY_928_DATA 0x00000000
+#define DDRSS3_PHY_929_DATA 0x00000000
+#define DDRSS3_PHY_930_DATA 0x00000000
+#define DDRSS3_PHY_931_DATA 0x00000000
+#define DDRSS3_PHY_932_DATA 0x00000000
+#define DDRSS3_PHY_933_DATA 0x00000000
+#define DDRSS3_PHY_934_DATA 0x00000000
+#define DDRSS3_PHY_935_DATA 0x00000000
+#define DDRSS3_PHY_936_DATA 0x00000000
+#define DDRSS3_PHY_937_DATA 0x00000000
+#define DDRSS3_PHY_938_DATA 0x00000000
+#define DDRSS3_PHY_939_DATA 0x00000000
+#define DDRSS3_PHY_940_DATA 0x00000000
+#define DDRSS3_PHY_941_DATA 0x00000000
+#define DDRSS3_PHY_942_DATA 0x00000000
+#define DDRSS3_PHY_943_DATA 0x00000000
+#define DDRSS3_PHY_944_DATA 0x00000000
+#define DDRSS3_PHY_945_DATA 0x00000000
+#define DDRSS3_PHY_946_DATA 0x00000000
+#define DDRSS3_PHY_947_DATA 0x00000000
+#define DDRSS3_PHY_948_DATA 0x00000000
+#define DDRSS3_PHY_949_DATA 0x00000000
+#define DDRSS3_PHY_950_DATA 0x00000000
+#define DDRSS3_PHY_951_DATA 0x00000000
+#define DDRSS3_PHY_952_DATA 0x00000000
+#define DDRSS3_PHY_953_DATA 0x00000000
+#define DDRSS3_PHY_954_DATA 0x00000000
+#define DDRSS3_PHY_955_DATA 0x00000000
+#define DDRSS3_PHY_956_DATA 0x00000000
+#define DDRSS3_PHY_957_DATA 0x00000000
+#define DDRSS3_PHY_958_DATA 0x00000000
+#define DDRSS3_PHY_959_DATA 0x00000000
+#define DDRSS3_PHY_960_DATA 0x00000000
+#define DDRSS3_PHY_961_DATA 0x00000000
+#define DDRSS3_PHY_962_DATA 0x00000000
+#define DDRSS3_PHY_963_DATA 0x00000000
+#define DDRSS3_PHY_964_DATA 0x00000000
+#define DDRSS3_PHY_965_DATA 0x00000000
+#define DDRSS3_PHY_966_DATA 0x00000000
+#define DDRSS3_PHY_967_DATA 0x00000000
+#define DDRSS3_PHY_968_DATA 0x00000000
+#define DDRSS3_PHY_969_DATA 0x00000000
+#define DDRSS3_PHY_970_DATA 0x00000000
+#define DDRSS3_PHY_971_DATA 0x00000000
+#define DDRSS3_PHY_972_DATA 0x00000000
+#define DDRSS3_PHY_973_DATA 0x00000000
+#define DDRSS3_PHY_974_DATA 0x00000000
+#define DDRSS3_PHY_975_DATA 0x00000000
+#define DDRSS3_PHY_976_DATA 0x00000000
+#define DDRSS3_PHY_977_DATA 0x00000000
+#define DDRSS3_PHY_978_DATA 0x00000000
+#define DDRSS3_PHY_979_DATA 0x00000000
+#define DDRSS3_PHY_980_DATA 0x00000000
+#define DDRSS3_PHY_981_DATA 0x00000000
+#define DDRSS3_PHY_982_DATA 0x00000000
+#define DDRSS3_PHY_983_DATA 0x00000000
+#define DDRSS3_PHY_984_DATA 0x00000000
+#define DDRSS3_PHY_985_DATA 0x00000000
+#define DDRSS3_PHY_986_DATA 0x00000000
+#define DDRSS3_PHY_987_DATA 0x00000000
+#define DDRSS3_PHY_988_DATA 0x00000000
+#define DDRSS3_PHY_989_DATA 0x00000000
+#define DDRSS3_PHY_990_DATA 0x00000000
+#define DDRSS3_PHY_991_DATA 0x00000000
+#define DDRSS3_PHY_992_DATA 0x00000000
+#define DDRSS3_PHY_993_DATA 0x00000000
+#define DDRSS3_PHY_994_DATA 0x00000000
+#define DDRSS3_PHY_995_DATA 0x00000000
+#define DDRSS3_PHY_996_DATA 0x00000000
+#define DDRSS3_PHY_997_DATA 0x00000000
+#define DDRSS3_PHY_998_DATA 0x00000000
+#define DDRSS3_PHY_999_DATA 0x00000000
+#define DDRSS3_PHY_1000_DATA 0x00000000
+#define DDRSS3_PHY_1001_DATA 0x00000000
+#define DDRSS3_PHY_1002_DATA 0x00000000
+#define DDRSS3_PHY_1003_DATA 0x00000000
+#define DDRSS3_PHY_1004_DATA 0x00000000
+#define DDRSS3_PHY_1005_DATA 0x00000000
+#define DDRSS3_PHY_1006_DATA 0x00000000
+#define DDRSS3_PHY_1007_DATA 0x00000000
+#define DDRSS3_PHY_1008_DATA 0x00000000
+#define DDRSS3_PHY_1009_DATA 0x00000000
+#define DDRSS3_PHY_1010_DATA 0x00000000
+#define DDRSS3_PHY_1011_DATA 0x00000000
+#define DDRSS3_PHY_1012_DATA 0x00000000
+#define DDRSS3_PHY_1013_DATA 0x00000000
+#define DDRSS3_PHY_1014_DATA 0x00000000
+#define DDRSS3_PHY_1015_DATA 0x00000000
+#define DDRSS3_PHY_1016_DATA 0x00000000
+#define DDRSS3_PHY_1017_DATA 0x00000000
+#define DDRSS3_PHY_1018_DATA 0x00000000
+#define DDRSS3_PHY_1019_DATA 0x00000000
+#define DDRSS3_PHY_1020_DATA 0x00000000
+#define DDRSS3_PHY_1021_DATA 0x00000000
+#define DDRSS3_PHY_1022_DATA 0x00000000
+#define DDRSS3_PHY_1023_DATA 0x00000000
+#define DDRSS3_PHY_1024_DATA 0x00000000
+#define DDRSS3_PHY_1025_DATA 0x00000000
+#define DDRSS3_PHY_1026_DATA 0x00000000
+#define DDRSS3_PHY_1027_DATA 0x00000000
+#define DDRSS3_PHY_1028_DATA 0x00000000
+#define DDRSS3_PHY_1029_DATA 0x00000100
+#define DDRSS3_PHY_1030_DATA 0x00000200
+#define DDRSS3_PHY_1031_DATA 0x00000000
+#define DDRSS3_PHY_1032_DATA 0x00000000
+#define DDRSS3_PHY_1033_DATA 0x00000000
+#define DDRSS3_PHY_1034_DATA 0x00000000
+#define DDRSS3_PHY_1035_DATA 0x00400000
+#define DDRSS3_PHY_1036_DATA 0x00000080
+#define DDRSS3_PHY_1037_DATA 0x00DCBA98
+#define DDRSS3_PHY_1038_DATA 0x03000000
+#define DDRSS3_PHY_1039_DATA 0x00200000
+#define DDRSS3_PHY_1040_DATA 0x00000000
+#define DDRSS3_PHY_1041_DATA 0x00000000
+#define DDRSS3_PHY_1042_DATA 0x00000000
+#define DDRSS3_PHY_1043_DATA 0x00000000
+#define DDRSS3_PHY_1044_DATA 0x00000000
+#define DDRSS3_PHY_1045_DATA 0x0000002A
+#define DDRSS3_PHY_1046_DATA 0x00000015
+#define DDRSS3_PHY_1047_DATA 0x00000015
+#define DDRSS3_PHY_1048_DATA 0x0000002A
+#define DDRSS3_PHY_1049_DATA 0x00000033
+#define DDRSS3_PHY_1050_DATA 0x0000000C
+#define DDRSS3_PHY_1051_DATA 0x0000000C
+#define DDRSS3_PHY_1052_DATA 0x00000033
+#define DDRSS3_PHY_1053_DATA 0x00543210
+#define DDRSS3_PHY_1054_DATA 0x003F0000
+#define DDRSS3_PHY_1055_DATA 0x000F3F3F
+#define DDRSS3_PHY_1056_DATA 0x20202003
+#define DDRSS3_PHY_1057_DATA 0x00202020
+#define DDRSS3_PHY_1058_DATA 0x20008008
+#define DDRSS3_PHY_1059_DATA 0x00000810
+#define DDRSS3_PHY_1060_DATA 0x00000F00
+#define DDRSS3_PHY_1061_DATA 0x00000000
+#define DDRSS3_PHY_1062_DATA 0x00000000
+#define DDRSS3_PHY_1063_DATA 0x00000000
+#define DDRSS3_PHY_1064_DATA 0x000305CC
+#define DDRSS3_PHY_1065_DATA 0x00030000
+#define DDRSS3_PHY_1066_DATA 0x00000300
+#define DDRSS3_PHY_1067_DATA 0x00000300
+#define DDRSS3_PHY_1068_DATA 0x00000300
+#define DDRSS3_PHY_1069_DATA 0x00000300
+#define DDRSS3_PHY_1070_DATA 0x00000300
+#define DDRSS3_PHY_1071_DATA 0x42080010
+#define DDRSS3_PHY_1072_DATA 0x0000803E
+#define DDRSS3_PHY_1073_DATA 0x00000001
+#define DDRSS3_PHY_1074_DATA 0x01000102
+#define DDRSS3_PHY_1075_DATA 0x00008000
+#define DDRSS3_PHY_1076_DATA 0x00000000
+#define DDRSS3_PHY_1077_DATA 0x00000000
+#define DDRSS3_PHY_1078_DATA 0x00000000
+#define DDRSS3_PHY_1079_DATA 0x00000000
+#define DDRSS3_PHY_1080_DATA 0x00000000
+#define DDRSS3_PHY_1081_DATA 0x00000000
+#define DDRSS3_PHY_1082_DATA 0x00000000
+#define DDRSS3_PHY_1083_DATA 0x00000000
+#define DDRSS3_PHY_1084_DATA 0x00000000
+#define DDRSS3_PHY_1085_DATA 0x00000000
+#define DDRSS3_PHY_1086_DATA 0x00000000
+#define DDRSS3_PHY_1087_DATA 0x00000000
+#define DDRSS3_PHY_1088_DATA 0x00000000
+#define DDRSS3_PHY_1089_DATA 0x00000000
+#define DDRSS3_PHY_1090_DATA 0x00000000
+#define DDRSS3_PHY_1091_DATA 0x00000000
+#define DDRSS3_PHY_1092_DATA 0x00000000
+#define DDRSS3_PHY_1093_DATA 0x00000000
+#define DDRSS3_PHY_1094_DATA 0x00000000
+#define DDRSS3_PHY_1095_DATA 0x00000000
+#define DDRSS3_PHY_1096_DATA 0x00000000
+#define DDRSS3_PHY_1097_DATA 0x00000000
+#define DDRSS3_PHY_1098_DATA 0x00000000
+#define DDRSS3_PHY_1099_DATA 0x00000000
+#define DDRSS3_PHY_1100_DATA 0x00000000
+#define DDRSS3_PHY_1101_DATA 0x00000000
+#define DDRSS3_PHY_1102_DATA 0x00000000
+#define DDRSS3_PHY_1103_DATA 0x00000000
+#define DDRSS3_PHY_1104_DATA 0x00000000
+#define DDRSS3_PHY_1105_DATA 0x00000000
+#define DDRSS3_PHY_1106_DATA 0x00000000
+#define DDRSS3_PHY_1107_DATA 0x00000000
+#define DDRSS3_PHY_1108_DATA 0x00000000
+#define DDRSS3_PHY_1109_DATA 0x00000000
+#define DDRSS3_PHY_1110_DATA 0x00000000
+#define DDRSS3_PHY_1111_DATA 0x00000000
+#define DDRSS3_PHY_1112_DATA 0x00000000
+#define DDRSS3_PHY_1113_DATA 0x00000000
+#define DDRSS3_PHY_1114_DATA 0x00000000
+#define DDRSS3_PHY_1115_DATA 0x00000000
+#define DDRSS3_PHY_1116_DATA 0x00000000
+#define DDRSS3_PHY_1117_DATA 0x00000000
+#define DDRSS3_PHY_1118_DATA 0x00000000
+#define DDRSS3_PHY_1119_DATA 0x00000000
+#define DDRSS3_PHY_1120_DATA 0x00000000
+#define DDRSS3_PHY_1121_DATA 0x00000000
+#define DDRSS3_PHY_1122_DATA 0x00000000
+#define DDRSS3_PHY_1123_DATA 0x00000000
+#define DDRSS3_PHY_1124_DATA 0x00000000
+#define DDRSS3_PHY_1125_DATA 0x00000000
+#define DDRSS3_PHY_1126_DATA 0x00000000
+#define DDRSS3_PHY_1127_DATA 0x00000000
+#define DDRSS3_PHY_1128_DATA 0x00000000
+#define DDRSS3_PHY_1129_DATA 0x00000000
+#define DDRSS3_PHY_1130_DATA 0x00000000
+#define DDRSS3_PHY_1131_DATA 0x00000000
+#define DDRSS3_PHY_1132_DATA 0x00000000
+#define DDRSS3_PHY_1133_DATA 0x00000000
+#define DDRSS3_PHY_1134_DATA 0x00000000
+#define DDRSS3_PHY_1135_DATA 0x00000000
+#define DDRSS3_PHY_1136_DATA 0x00000000
+#define DDRSS3_PHY_1137_DATA 0x00000000
+#define DDRSS3_PHY_1138_DATA 0x00000000
+#define DDRSS3_PHY_1139_DATA 0x00000000
+#define DDRSS3_PHY_1140_DATA 0x00000000
+#define DDRSS3_PHY_1141_DATA 0x00000000
+#define DDRSS3_PHY_1142_DATA 0x00000000
+#define DDRSS3_PHY_1143_DATA 0x00000000
+#define DDRSS3_PHY_1144_DATA 0x00000000
+#define DDRSS3_PHY_1145_DATA 0x00000000
+#define DDRSS3_PHY_1146_DATA 0x00000000
+#define DDRSS3_PHY_1147_DATA 0x00000000
+#define DDRSS3_PHY_1148_DATA 0x00000000
+#define DDRSS3_PHY_1149_DATA 0x00000000
+#define DDRSS3_PHY_1150_DATA 0x00000000
+#define DDRSS3_PHY_1151_DATA 0x00000000
+#define DDRSS3_PHY_1152_DATA 0x00000000
+#define DDRSS3_PHY_1153_DATA 0x00000000
+#define DDRSS3_PHY_1154_DATA 0x00000000
+#define DDRSS3_PHY_1155_DATA 0x00000000
+#define DDRSS3_PHY_1156_DATA 0x00000000
+#define DDRSS3_PHY_1157_DATA 0x00000000
+#define DDRSS3_PHY_1158_DATA 0x00000000
+#define DDRSS3_PHY_1159_DATA 0x00000000
+#define DDRSS3_PHY_1160_DATA 0x00000000
+#define DDRSS3_PHY_1161_DATA 0x00000000
+#define DDRSS3_PHY_1162_DATA 0x00000000
+#define DDRSS3_PHY_1163_DATA 0x00000000
+#define DDRSS3_PHY_1164_DATA 0x00000000
+#define DDRSS3_PHY_1165_DATA 0x00000000
+#define DDRSS3_PHY_1166_DATA 0x00000000
+#define DDRSS3_PHY_1167_DATA 0x00000000
+#define DDRSS3_PHY_1168_DATA 0x00000000
+#define DDRSS3_PHY_1169_DATA 0x00000000
+#define DDRSS3_PHY_1170_DATA 0x00000000
+#define DDRSS3_PHY_1171_DATA 0x00000000
+#define DDRSS3_PHY_1172_DATA 0x00000000
+#define DDRSS3_PHY_1173_DATA 0x00000000
+#define DDRSS3_PHY_1174_DATA 0x00000000
+#define DDRSS3_PHY_1175_DATA 0x00000000
+#define DDRSS3_PHY_1176_DATA 0x00000000
+#define DDRSS3_PHY_1177_DATA 0x00000000
+#define DDRSS3_PHY_1178_DATA 0x00000000
+#define DDRSS3_PHY_1179_DATA 0x00000000
+#define DDRSS3_PHY_1180_DATA 0x00000000
+#define DDRSS3_PHY_1181_DATA 0x00000000
+#define DDRSS3_PHY_1182_DATA 0x00000000
+#define DDRSS3_PHY_1183_DATA 0x00000000
+#define DDRSS3_PHY_1184_DATA 0x00000000
+#define DDRSS3_PHY_1185_DATA 0x00000000
+#define DDRSS3_PHY_1186_DATA 0x00000000
+#define DDRSS3_PHY_1187_DATA 0x00000000
+#define DDRSS3_PHY_1188_DATA 0x00000000
+#define DDRSS3_PHY_1189_DATA 0x00000000
+#define DDRSS3_PHY_1190_DATA 0x00000000
+#define DDRSS3_PHY_1191_DATA 0x00000000
+#define DDRSS3_PHY_1192_DATA 0x00000000
+#define DDRSS3_PHY_1193_DATA 0x00000000
+#define DDRSS3_PHY_1194_DATA 0x00000000
+#define DDRSS3_PHY_1195_DATA 0x00000000
+#define DDRSS3_PHY_1196_DATA 0x00000000
+#define DDRSS3_PHY_1197_DATA 0x00000000
+#define DDRSS3_PHY_1198_DATA 0x00000000
+#define DDRSS3_PHY_1199_DATA 0x00000000
+#define DDRSS3_PHY_1200_DATA 0x00000000
+#define DDRSS3_PHY_1201_DATA 0x00000000
+#define DDRSS3_PHY_1202_DATA 0x00000000
+#define DDRSS3_PHY_1203_DATA 0x00000000
+#define DDRSS3_PHY_1204_DATA 0x00000000
+#define DDRSS3_PHY_1205_DATA 0x00000000
+#define DDRSS3_PHY_1206_DATA 0x00000000
+#define DDRSS3_PHY_1207_DATA 0x00000000
+#define DDRSS3_PHY_1208_DATA 0x00000000
+#define DDRSS3_PHY_1209_DATA 0x00000000
+#define DDRSS3_PHY_1210_DATA 0x00000000
+#define DDRSS3_PHY_1211_DATA 0x00000000
+#define DDRSS3_PHY_1212_DATA 0x00000000
+#define DDRSS3_PHY_1213_DATA 0x00000000
+#define DDRSS3_PHY_1214_DATA 0x00000000
+#define DDRSS3_PHY_1215_DATA 0x00000000
+#define DDRSS3_PHY_1216_DATA 0x00000000
+#define DDRSS3_PHY_1217_DATA 0x00000000
+#define DDRSS3_PHY_1218_DATA 0x00000000
+#define DDRSS3_PHY_1219_DATA 0x00000000
+#define DDRSS3_PHY_1220_DATA 0x00000000
+#define DDRSS3_PHY_1221_DATA 0x00000000
+#define DDRSS3_PHY_1222_DATA 0x00000000
+#define DDRSS3_PHY_1223_DATA 0x00000000
+#define DDRSS3_PHY_1224_DATA 0x00000000
+#define DDRSS3_PHY_1225_DATA 0x00000000
+#define DDRSS3_PHY_1226_DATA 0x00000000
+#define DDRSS3_PHY_1227_DATA 0x00000000
+#define DDRSS3_PHY_1228_DATA 0x00000000
+#define DDRSS3_PHY_1229_DATA 0x00000000
+#define DDRSS3_PHY_1230_DATA 0x00000000
+#define DDRSS3_PHY_1231_DATA 0x00000000
+#define DDRSS3_PHY_1232_DATA 0x00000000
+#define DDRSS3_PHY_1233_DATA 0x00000000
+#define DDRSS3_PHY_1234_DATA 0x00000000
+#define DDRSS3_PHY_1235_DATA 0x00000000
+#define DDRSS3_PHY_1236_DATA 0x00000000
+#define DDRSS3_PHY_1237_DATA 0x00000000
+#define DDRSS3_PHY_1238_DATA 0x00000000
+#define DDRSS3_PHY_1239_DATA 0x00000000
+#define DDRSS3_PHY_1240_DATA 0x00000000
+#define DDRSS3_PHY_1241_DATA 0x00000000
+#define DDRSS3_PHY_1242_DATA 0x00000000
+#define DDRSS3_PHY_1243_DATA 0x00000000
+#define DDRSS3_PHY_1244_DATA 0x00000000
+#define DDRSS3_PHY_1245_DATA 0x00000000
+#define DDRSS3_PHY_1246_DATA 0x00000000
+#define DDRSS3_PHY_1247_DATA 0x00000000
+#define DDRSS3_PHY_1248_DATA 0x00000000
+#define DDRSS3_PHY_1249_DATA 0x00000000
+#define DDRSS3_PHY_1250_DATA 0x00000000
+#define DDRSS3_PHY_1251_DATA 0x00000000
+#define DDRSS3_PHY_1252_DATA 0x00000000
+#define DDRSS3_PHY_1253_DATA 0x00000000
+#define DDRSS3_PHY_1254_DATA 0x00000000
+#define DDRSS3_PHY_1255_DATA 0x00000000
+#define DDRSS3_PHY_1256_DATA 0x00000000
+#define DDRSS3_PHY_1257_DATA 0x00000000
+#define DDRSS3_PHY_1258_DATA 0x00000000
+#define DDRSS3_PHY_1259_DATA 0x00000000
+#define DDRSS3_PHY_1260_DATA 0x00000000
+#define DDRSS3_PHY_1261_DATA 0x00000000
+#define DDRSS3_PHY_1262_DATA 0x00000000
+#define DDRSS3_PHY_1263_DATA 0x00000000
+#define DDRSS3_PHY_1264_DATA 0x00000000
+#define DDRSS3_PHY_1265_DATA 0x00000000
+#define DDRSS3_PHY_1266_DATA 0x00000000
+#define DDRSS3_PHY_1267_DATA 0x00000000
+#define DDRSS3_PHY_1268_DATA 0x00000000
+#define DDRSS3_PHY_1269_DATA 0x00000000
+#define DDRSS3_PHY_1270_DATA 0x00000000
+#define DDRSS3_PHY_1271_DATA 0x00000000
+#define DDRSS3_PHY_1272_DATA 0x00000000
+#define DDRSS3_PHY_1273_DATA 0x00000000
+#define DDRSS3_PHY_1274_DATA 0x00000000
+#define DDRSS3_PHY_1275_DATA 0x00000000
+#define DDRSS3_PHY_1276_DATA 0x00000000
+#define DDRSS3_PHY_1277_DATA 0x00000000
+#define DDRSS3_PHY_1278_DATA 0x00000000
+#define DDRSS3_PHY_1279_DATA 0x00000000
+#define DDRSS3_PHY_1280_DATA 0x00000000
+#define DDRSS3_PHY_1281_DATA 0x00010100
+#define DDRSS3_PHY_1282_DATA 0x00000000
+#define DDRSS3_PHY_1283_DATA 0x00000000
+#define DDRSS3_PHY_1284_DATA 0x00050000
+#define DDRSS3_PHY_1285_DATA 0x04000000
+#define DDRSS3_PHY_1286_DATA 0x00000055
+#define DDRSS3_PHY_1287_DATA 0x00000000
+#define DDRSS3_PHY_1288_DATA 0x00000000
+#define DDRSS3_PHY_1289_DATA 0x00000000
+#define DDRSS3_PHY_1290_DATA 0x00000000
+#define DDRSS3_PHY_1291_DATA 0x00002001
+#define DDRSS3_PHY_1292_DATA 0x0000400F
+#define DDRSS3_PHY_1293_DATA 0x50020028
+#define DDRSS3_PHY_1294_DATA 0x01010000
+#define DDRSS3_PHY_1295_DATA 0x80080001
+#define DDRSS3_PHY_1296_DATA 0x10200000
+#define DDRSS3_PHY_1297_DATA 0x00000008
+#define DDRSS3_PHY_1298_DATA 0x00000000
+#define DDRSS3_PHY_1299_DATA 0x01090E00
+#define DDRSS3_PHY_1300_DATA 0x00040101
+#define DDRSS3_PHY_1301_DATA 0x0000010F
+#define DDRSS3_PHY_1302_DATA 0x00000000
+#define DDRSS3_PHY_1303_DATA 0x00000064
+#define DDRSS3_PHY_1304_DATA 0x00000000
+#define DDRSS3_PHY_1305_DATA 0x01010000
+#define DDRSS3_PHY_1306_DATA 0x01080402
+#define DDRSS3_PHY_1307_DATA 0x01200F02
+#define DDRSS3_PHY_1308_DATA 0x00194280
+#define DDRSS3_PHY_1309_DATA 0x00000004
+#define DDRSS3_PHY_1310_DATA 0x00042000
+#define DDRSS3_PHY_1311_DATA 0x00000000
+#define DDRSS3_PHY_1312_DATA 0x00000000
+#define DDRSS3_PHY_1313_DATA 0x00000000
+#define DDRSS3_PHY_1314_DATA 0x00000000
+#define DDRSS3_PHY_1315_DATA 0x00000000
+#define DDRSS3_PHY_1316_DATA 0x00000000
+#define DDRSS3_PHY_1317_DATA 0x01000000
+#define DDRSS3_PHY_1318_DATA 0x00000705
+#define DDRSS3_PHY_1319_DATA 0x00000054
+#define DDRSS3_PHY_1320_DATA 0x00030820
+#define DDRSS3_PHY_1321_DATA 0x00010820
+#define DDRSS3_PHY_1322_DATA 0x00010820
+#define DDRSS3_PHY_1323_DATA 0x00010820
+#define DDRSS3_PHY_1324_DATA 0x00010820
+#define DDRSS3_PHY_1325_DATA 0x00010820
+#define DDRSS3_PHY_1326_DATA 0x00010820
+#define DDRSS3_PHY_1327_DATA 0x00010820
+#define DDRSS3_PHY_1328_DATA 0x00010820
+#define DDRSS3_PHY_1329_DATA 0x00000000
+#define DDRSS3_PHY_1330_DATA 0x00000074
+#define DDRSS3_PHY_1331_DATA 0x00000400
+#define DDRSS3_PHY_1332_DATA 0x00000108
+#define DDRSS3_PHY_1333_DATA 0x00000000
+#define DDRSS3_PHY_1334_DATA 0x00000000
+#define DDRSS3_PHY_1335_DATA 0x00000000
+#define DDRSS3_PHY_1336_DATA 0x00000000
+#define DDRSS3_PHY_1337_DATA 0x00000000
+#define DDRSS3_PHY_1338_DATA 0x03000000
+#define DDRSS3_PHY_1339_DATA 0x00000000
+#define DDRSS3_PHY_1340_DATA 0x00000000
+#define DDRSS3_PHY_1341_DATA 0x00000000
+#define DDRSS3_PHY_1342_DATA 0x04102006
+#define DDRSS3_PHY_1343_DATA 0x00041020
+#define DDRSS3_PHY_1344_DATA 0x01C98C98
+#define DDRSS3_PHY_1345_DATA 0x3F400000
+#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS3_PHY_1347_DATA 0x0000001F
+#define DDRSS3_PHY_1348_DATA 0x00000000
+#define DDRSS3_PHY_1349_DATA 0x00000000
+#define DDRSS3_PHY_1350_DATA 0x00000000
+#define DDRSS3_PHY_1351_DATA 0x00010000
+#define DDRSS3_PHY_1352_DATA 0x00000000
+#define DDRSS3_PHY_1353_DATA 0x00000000
+#define DDRSS3_PHY_1354_DATA 0x00000000
+#define DDRSS3_PHY_1355_DATA 0x00000000
+#define DDRSS3_PHY_1356_DATA 0x76543210
+#define DDRSS3_PHY_1357_DATA 0x00010198
+#define DDRSS3_PHY_1358_DATA 0x00000000
+#define DDRSS3_PHY_1359_DATA 0x00000000
+#define DDRSS3_PHY_1360_DATA 0x00000000
+#define DDRSS3_PHY_1361_DATA 0x00040700
+#define DDRSS3_PHY_1362_DATA 0x00000000
+#define DDRSS3_PHY_1363_DATA 0x00000000
+#define DDRSS3_PHY_1364_DATA 0x00000000
+#define DDRSS3_PHY_1365_DATA 0x00000000
+#define DDRSS3_PHY_1366_DATA 0x00000000
+#define DDRSS3_PHY_1367_DATA 0x00000002
+#define DDRSS3_PHY_1368_DATA 0x00000000
+#define DDRSS3_PHY_1369_DATA 0x00000000
+#define DDRSS3_PHY_1370_DATA 0x00000000
+#define DDRSS3_PHY_1371_DATA 0x00000000
+#define DDRSS3_PHY_1372_DATA 0x00000000
+#define DDRSS3_PHY_1373_DATA 0x00000000
+#define DDRSS3_PHY_1374_DATA 0x00080000
+#define DDRSS3_PHY_1375_DATA 0x000007FF
+#define DDRSS3_PHY_1376_DATA 0x00000000
+#define DDRSS3_PHY_1377_DATA 0x00000000
+#define DDRSS3_PHY_1378_DATA 0x00000000
+#define DDRSS3_PHY_1379_DATA 0x00000000
+#define DDRSS3_PHY_1380_DATA 0x00000000
+#define DDRSS3_PHY_1381_DATA 0x00000000
+#define DDRSS3_PHY_1382_DATA 0x000FFFFF
+#define DDRSS3_PHY_1383_DATA 0x000FFFFF
+#define DDRSS3_PHY_1384_DATA 0x0000FFFF
+#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS3_PHY_1386_DATA 0x030FFFFF
+#define DDRSS3_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS3_PHY_1388_DATA 0x0000FFFF
+#define DDRSS3_PHY_1389_DATA 0x00000000
+#define DDRSS3_PHY_1390_DATA 0x00000000
+#define DDRSS3_PHY_1391_DATA 0x00000000
+#define DDRSS3_PHY_1392_DATA 0x00000000
+#define DDRSS3_PHY_1393_DATA 0x0001F7C0
+#define DDRSS3_PHY_1394_DATA 0x00000003
+#define DDRSS3_PHY_1395_DATA 0x00000000
+#define DDRSS3_PHY_1396_DATA 0x00001142
+#define DDRSS3_PHY_1397_DATA 0x040207AB
+#define DDRSS3_PHY_1398_DATA 0x01000080
+#define DDRSS3_PHY_1399_DATA 0x03900390
+#define DDRSS3_PHY_1400_DATA 0x03900390
+#define DDRSS3_PHY_1401_DATA 0x00000390
+#define DDRSS3_PHY_1402_DATA 0x00000390
+#define DDRSS3_PHY_1403_DATA 0x00000390
+#define DDRSS3_PHY_1404_DATA 0x00000390
+#define DDRSS3_PHY_1405_DATA 0x00000005
+#define DDRSS3_PHY_1406_DATA 0x01813FCC
+#define DDRSS3_PHY_1407_DATA 0x000000CC
+#define DDRSS3_PHY_1408_DATA 0x0C000DFF
+#define DDRSS3_PHY_1409_DATA 0x30000DFF
+#define DDRSS3_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1411_DATA 0x000100F0
+#define DDRSS3_PHY_1412_DATA 0x780DFFCC
+#define DDRSS3_PHY_1413_DATA 0x00007E31
+#define DDRSS3_PHY_1414_DATA 0x000CBF11
+#define DDRSS3_PHY_1415_DATA 0x01990010
+#define DDRSS3_PHY_1416_DATA 0x000CBF11
+#define DDRSS3_PHY_1417_DATA 0x01990010
+#define DDRSS3_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1419_DATA 0x00EF00F0
+#define DDRSS3_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1421_DATA 0x01FF00F0
+#define DDRSS3_PHY_1422_DATA 0x20040006
diff --git a/arch/arm/dts/k3-am69-aquila.dtsi b/arch/arm/dts/k3-am69-aquila.dtsi
new file mode 100644
index 000000000000..5e1f92fc85f6
--- /dev/null
+++ b/arch/arm/dts/k3-am69-aquila.dtsi
@@ -0,0 +1,1837 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/usb/pd.h>
+#include "k3-j784s4.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ aliases {
+ can0 = &main_mcan10;
+ can1 = &mcu_mcan0;
+ can2 = &main_mcan13;
+ can3 = &mcu_mcan1;
+ eeprom0 = &som_eeprom;
+ ethernet0 = &mcu_cpsw_port1;
+ ethernet1 = &main_cpsw0_port8;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &mcu_i2c1;
+ i2c3 = &main_i2c0;
+ i2c4 = &main_i2c1;
+ i2c5 = &main_i2c2;
+ i2c6 = &main_i2c5;
+ mmc0 = &main_sdhci0;
+ mmc1 = &main_sdhci1;
+ rtc0 = &rtc_i2c;
+ serial0 = &main_uart4;
+ serial1 = &wkup_uart0;
+ serial2 = &main_uart8;
+ serial3 = &mcu_uart0;
+ usb0 = &usb0;
+ };
+
+ aquila_key_power: gpio-key-power {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwr_btn_int>;
+ status = "disabled";
+
+ key-power {
+ /* Aquila CTRL_PWR_BTN_MICO# (AQUILA B93) */
+ gpios = <&wkup_gpio0 36 GPIO_ACTIVE_LOW>;
+ label = "Power Button";
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ aquila_key_wake: gpio-key-wakeup {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_wake1_mico>;
+ status = "disabled";
+
+ key-wakeup {
+ /* Aquila CTRL_WAKE1_MICO# (AQUILA D6) */
+ gpios = <&wkup_gpio0 49 GPIO_ACTIVE_LOW>;
+ label = "Wake Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ /* Aquila CTRL_RESET_MICO# (AQUILA B92) */
+ gpio-restart {
+ compatible = "gpio-restart";
+ /* COLD_RESET_REQ */
+ gpios = <&som_gpio_expander 1 GPIO_ACTIVE_HIGH>;
+ priority = <192>;
+ };
+
+ /* PWR_DOWN_REQ */
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ /* PWR_DOWN_REQ */
+ gpios = <&som_gpio_expander 2 GPIO_ACTIVE_HIGH>;
+ timeout-ms = <3000>;
+ };
+
+ memory at 80000000 {
+ device_type = "memory";
+ /* 32G RAM */
+ reg = <0x00 0x80000000 0x00 0x80000000>,
+ <0x08 0x80000000 0x07 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee at 9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_dma_memory_region: memory at a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ mcu_r5fss0_core0_memory_region: memory at a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+ };
+
+ /* Module Power Supply (VCC) */
+ reg_vin: regulator-vin {
+ compatible = "regulator-fixed";
+ regulator-name = "+V_IN";
+ };
+
+ /* Enabled by EN_3V3_VIO (PMIC_GPIO_9) */
+ reg_1v1_usb_bridge: regulator-1v1-vio {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-name = "+V1.1_VIO";
+ vin-supply = <®_vin>;
+ };
+
+ reg_3v3_wifi: regulator-3v3-wifi {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_en_3v3_wifi>;
+ gpio = <&wkup_gpio0 57 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_WIFI";
+ startup-delay-us = <20000>;
+ vin-supply = <®_vin>;
+ };
+
+ reg_1v8_stby: regulator-1v8-stby {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_STBY";
+ vin-supply = <®_vin>;
+ };
+
+ /* Aquila SD_1_PWR_EN */
+ reg_sdhc1_vmmc: regulator-sdhci1 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sd1_pwr_en>;
+ /* Aquila SD_1_PWR_EN (AQUILA A6) */
+ gpio = <&main_gpio0 52 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+3V3_SD";
+ startup-delay-us = <20000>;
+ };
+
+ reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc {
+ compatible = "regulator-gpio";
+ /* SDIO_PWR_SEL_3.3V */
+ gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+VDD_SD_DV";
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+
+ /* On-module USB_1_SS mux */
+ usb0ss_mux: gpio-sbu-mux {
+ compatible = "ti,tmuxhs4212", "gpio-sbu-mux";
+ orientation-switch;
+ /* USB_MUX_SEL */
+ select-gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+};
+
+&main_pmx0 {
+ /* Aquila DP_1_HPD */
+ pinctrl_main_dp0_hpd: main-dp0-hpd-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ /* AQUILA B59 */
+ >;
+ };
+
+ /* Aquila PWM_1 */
+ pinctrl_main_ehrpwm0_b: main-ehrpwm0b-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x064, PIN_OUTPUT, 9) /* (AF38) MCAN0_TX.EHRPWM0_B */ /* AQUILA C25 */
+ >;
+ };
+
+ /* Aquila PWM_2 */
+ pinctrl_main_ehrpwm1_a: main-ehrpwm1a-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x060, PIN_OUTPUT, 9) /* (AE36) MCASP2_AXR1.EHRPWM1_A */ /* AQUILA C26 */
+ >;
+ };
+
+ /* Aquila PWM_3_DSI */
+ pinctrl_main_ehrpwm5_a: main-ehrpwm5a-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x084, PIN_OUTPUT, 9) /* (AG38) MCASP0_AXR5.EHRPWM5_A */ /* AQUILA B46 */
+ >;
+ };
+
+ /* Aquila PWM_4_DP */
+ pinctrl_main_ehrpwm2_a: main-ehrpwm2a-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x040, PIN_INPUT, 9) /* (AF37) MCASP0_AXR0.EHRPWM2_A */ /* AQUILA B58 */
+ >;
+ };
+
+ /* PMIC_INT# */
+ pinctrl_pmic_int: main-gpio0-0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTn.GPIO0_0 */
+ >;
+ };
+
+ /* Aquila GPIO_09_CSI_1 */
+ pinctrl_gpio_09_csi_1: main-gpio0-1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ /* AQUILA B17 */
+ >;
+ };
+
+ /* Aquila GPIO_10_CSI_1 */
+ pinctrl_gpio_10_csi_1: main-gpio0-2-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ /* AQUILA B18 */
+ >;
+ };
+
+ /* Aquila USB_1_OC# */
+ pinctrl_usb1_oc: main-gpio0-10-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x028, PIN_INPUT, 7) /* (AE33) MCAN16_RX.GPIO0_10 */ /* AQUILA B75 */
+ >;
+ };
+
+ /* Aquila USB_1_EN */
+ pinctrl_usb1_en_gpio: main-gpio0-11-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x02c, PIN_INPUT, 7) /* (AL32) GPIO0_11 */ /* AQUILA B77 */
+ >;
+ };
+
+ /* Aquila GPIO_17_DSI_1 */
+ pinctrl_gpio_17_dsi_1: main-gpio0-12-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x030, PIN_INPUT, 7) /* (AK37) GPIO0_12 */ /* AQUILA B42 */
+ >;
+ };
+
+ /* Aquila GPIO_19_DSI_1 */
+ pinctrl_gpio_19_dsi_1: main-gpio0-13-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ /* AQUILA B44 */
+ >;
+ };
+
+ /* Aquila GPIO_02 */
+ pinctrl_gpio_02: main-gpio0-17-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x044, PIN_INPUT, 7) /* (AG37) MCASP0_AXR1.GPIO0_17 */ /* AQUILA D24 */
+ >;
+ };
+
+ /* Aquila GPIO_20_DSI_1 */
+ pinctrl_gpio_20_dsi_1: main-gpio0-18-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x048, PIN_INPUT, 7) /* (AK33) MCASP0_AXR2.GPIO0_18 */ /* AQUILA B45 */
+ >;
+ };
+
+ /* Aquila GPIO_21_DP */
+ pinctrl_gpio_21_dp: main-gpio0-21-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x054, PIN_INPUT, 7) /* (AD37) MCASP2_ACLKX.GPIO0_21 */ /* AQUILA B57 */
+ >;
+ };
+
+ /* Aquila USB_1_INT# */
+ pinctrl_usb1_int: main-gpio0-28-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x070, PIN_INPUT, 7) /* (AH38) MCAN1_RX.GPIO0_28 */ /* AQUILA B74 */
+ >;
+ };
+
+ /* Aquila GPIO_03 */
+ pinctrl_gpio_03: main-gpio0-29-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x074, PIN_INPUT, 7) /* (AC33) MCAN2_TX.GPIO0_29 */ /* AQUILA D25 */
+ >;
+ };
+
+ /* Aquila GPIO_18_DSI_1 */
+ pinctrl_gpio_18_dsi_1: main-gpio0-31-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x07c, PIN_INPUT, 7) /* (AJ38) MCASP0_AXR3.GPIO0_31 */ /* AQUILA B43 */
+ >;
+ };
+
+ /* Aquila PCIE_1_RESET# */
+ pinctrl_pcie0_reset: main-gpio0-32-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x080, PIN_INPUT, 7) /* (AK34) MCASP0_AXR4.GPIO0_32 */ /* AQUILA C38 */
+ >;
+ };
+
+ /* Aquila PWM_3_DSI as GPIO */
+ pinctrl_pwm3_dsi_gpio: main-gpio0-33-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x084, PIN_INPUT, 7) /* (AG38) MCASP0_AXR5.GPIO0_33 */ /* AQUILA B46 */
+ >;
+ };
+
+ /* Aquila GPIO_01 */
+ pinctrl_gpio_01: main-gpio0-34-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x088, PIN_INPUT, 7) /* (AF36) MCASP0_AXR6.GPIO0_34 */ /* AQUILA D23 */
+ >;
+ };
+
+ /* Aquila PCIE_2_RESET# */
+ pinctrl_pcie1_reset: main-gpio0-41-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0a4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ /* AQUILA C35 */
+ >;
+ };
+
+ /* Aquila ETH_2_xGMII_INT# */
+ pinctrl_eth2_int: main-gpio0-44-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 7) /* (AL33) MCASP1_AXR3.GPIO0_44 */ /* AQUILA B81 */
+ >;
+ };
+
+ /* Aquila GPIO_11_CSI_1 */
+ pinctrl_gpio_11_csi_1: main-gpio0-47-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0bc, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ /* AQUILA A11 */
+ >;
+ };
+
+ /* Aquila GPIO_12_CSI_1 */
+ pinctrl_gpio_12_csi_1: main-gpio0-48-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0c0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ /* AQUILA B19 */
+ >;
+ };
+
+ /* Aquila SD_1_PWR_EN */
+ pinctrl_sd1_pwr_en: main-gpio0-52-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0d0, PIN_INPUT, 7) /* (AP38) SPI0_CS1.GPIO0_52 */ /* AQUILA A6 */
+ >;
+ };
+
+ /* Aquila SD_1_CD# as GPIO */
+ pinctrl_sd1_cd_gpio: main-gpio0-58-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0e8, PIN_INPUT_PULLUP, 7) /* (AR38) TIMER_IO0.GPIO0_58 */ /* AQUILA A1 */
+ >;
+ };
+
+ /* Aquila I2C_3_DSI1 */
+ pinctrl_main_i2c0: main-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0e0, PIN_INPUT, 0) /* (AN36) I2C0_SCL */ /* AQUILA B41 */
+ J784S4_IOPAD(0x0e4, PIN_INPUT, 0) /* (AP37) I2C0_SDA */ /* AQUILA B40 */
+ >;
+ };
+
+ /* Aquila I2C_4_CSI1 */
+ pinctrl_main_i2c1: main-i2c1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x020, PIN_INPUT_PULLUP, 12) /* (AJ35) MCAN15_RX.I2C1_SCL */ /* AQUILA A13 */
+ J784S4_IOPAD(0x024, PIN_INPUT_PULLUP, 12) /* (AH34) MCAN16_TX.I2C1_SDA */ /* AQUILA A12 */
+ >;
+ };
+
+ /* Aquila I2C_5_CSI2 */
+ pinctrl_main_i2c2: main-i2c2-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x04c, PIN_INPUT_PULLUP, 13) /* (AC32) MCASP1_AXR1.I2C2_SCL */ /* AQUILA C6 */
+ J784S4_IOPAD(0x050, PIN_INPUT_PULLUP, 13) /* (AC37) MCASP1_AXR2.I2C2_SDA */ /* AQUILA C5 */
+ >;
+ };
+
+ /* Aquila I2C_6 */
+ pinctrl_main_i2c5: main-i2c5-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x01c, PIN_INPUT_PULLUP, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ /* AQUILA C19 */
+ J784S4_IOPAD(0x018, PIN_INPUT_PULLUP, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ /* AQUILA C18 */
+ >;
+ };
+
+ /* Aquila I2S_1_MCLK */
+ pinctrl_audio_extrefclk1: audio-extrefclk1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ /* AQUILA B24 */
+ >;
+ };
+
+ /* Aquila CAN_1 */
+ pinctrl_main_mcan10: main-mcan10-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0b8, PIN_INPUT, 0) /* (AC34) MCASP1_ACLKX.MCAN10_RX */ /* AQUILA B49 */
+ J784S4_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (AL34) MCASP1_AXR4.MCAN10_TX */ /* AQUILA B48 */
+ >;
+ };
+
+ /* Aquila CAN_3 */
+ pinctrl_main_mcan13: main-mcan13-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x010, PIN_INPUT, 0) /* (AH33) MCAN13_RX */ /* AQUILA B54 */
+ J784S4_IOPAD(0x00c, PIN_OUTPUT, 0) /* (AF33) MCAN13_TX */ /* AQUILA B53 */
+ >;
+ };
+
+ /* Aquila I2S_1 */
+ pinctrl_main_mcasp4: main-mcasp4-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0c8, PIN_INPUT, 1) /* (AJ32) EXT_REFCLK1.MCASP4_ACLKX */ /* AQUILA B20 */
+ J784S4_IOPAD(0x06c, PIN_INPUT, 1) /* (AJ37) MCAN1_TX.MCASP4_AFSX */ /* AQUILA B21 */
+ J784S4_IOPAD(0x068, PIN_OUTPUT, 1) /* (AE38) MCAN0_RX.MCASP4_AXR1 */ /* AQUILA B22 */
+ J784S4_IOPAD(0x0c4, PIN_INPUT, 1) /* (AD36) ECAP0_IN_APWM_OUT.MCASP4_AXR2 */ /* AQUILA B23 */
+ >;
+ };
+
+ /* Aquila ETH_2_XGMII_MDIO */
+ pinctrl_main_mdio1: main-mdio1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x058, PIN_OUTPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ /* AQUILA B90 */
+ J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ /* AQUILA B89 */
+ >;
+ };
+
+ /* Aquila SD_1 */
+ pinctrl_main_mmc1: main-mmc1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ /* AQUILA A5 */
+ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ /* AQUILA A7 */
+ J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
+ J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ /* AQUILA A3 */
+ J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ /* AQUILA A2 */
+ J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ /* AQUILA A10 */
+ J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ /* AQUILA A8 */
+ >;
+ };
+
+ /* Aquila SPI_2 */
+ pinctrl_main_spi0: main-spi0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AN38) SPI0_CLK */ /* AQUILA D14 */
+ J784S4_IOPAD(0x0d8, PIN_INPUT, 0) /* (AM35) SPI0_D0 */ /* AQUILA D15 */
+ J784S4_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (AM36) SPI0_D1 */ /* AQUILA D17 */
+ >;
+ };
+
+ /* Aquila SPI_2 CS */
+ pinctrl_main_spi0_cs0: main-spi0-cs0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (AM37) SPI0_CS0 */ /* AQUILA D16 */
+ >;
+ };
+
+ /* Aquila SPI_1 */
+ pinctrl_main_spi2: main-spi2-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0a0, PIN_OUTPUT, 10) /* (AD34) MCASP0_AXR12.SPI2_CLK */ /* AQUILA D12 */
+ J784S4_IOPAD(0x0a8, PIN_INPUT, 10) /* (AF34) MCASP0_AXR14.SPI2_D0 */ /* AQUILA D10 */
+ J784S4_IOPAD(0x0ac, PIN_OUTPUT, 10) /* (AE34) MCASP0_AXR15.SPI2_D1 */ /* AQUILA D11 */
+ >;
+ };
+
+ /* Aquila SPI_1 CS */
+ pinctrl_main_spi2_cs0: main-spi2-cs0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x09c, PIN_OUTPUT, 10) /* (AF35) MCASP0_AXR11.SPI2_CS1 */ /* AQUILA D9 */
+ >;
+ };
+
+ /* Aquila UART_1 */
+ pinctrl_main_uart4: main-uart4-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x094, PIN_INPUT, 11) /* (AG35) MCASP0_AXR9.UART4_CTSn */ /* AQUILA B36 */
+ J784S4_IOPAD(0x098, PIN_OUTPUT, 11) /* (AH36) MCASP0_AXR10.UART4_RTSn */ /* AQUILA B38 */
+ J784S4_IOPAD(0x08c, PIN_INPUT, 11) /* (AE35) MCASP0_AXR7.UART4_RXD */ /* AQUILA B35 */
+ J784S4_IOPAD(0x090, PIN_OUTPUT, 11) /* (AC35) MCASP0_AXR8.UART4_TXD */ /* AQUILA B37 */
+ >;
+ };
+
+ /* Aquila UART_3, used as the Linux console */
+ pinctrl_main_uart8: main-uart8-default-pins {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x038, PIN_INPUT, 11) /* (AK35) MCASP0_ACLKX.UART8_RXD */ /* AQUILA D19 */
+ J784S4_IOPAD(0x03c, PIN_OUTPUT, 11) /* (AK38) MCASP0_AFSX.UART8_TXD */ /* AQUILA D20 */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+ /* Aquila QSPI_1 (4-bit) */
+ pinctrl_mcu_ospi0_4bit: mcu-ospi0-4bit-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ /* AQUILA B65 */
+ J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ /* AQUILA B68 */
+ J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ /* AQUILA B67 */
+ J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ /* AQUILA B61 */
+ J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ /* AQUILA B60 */
+ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ /* AQUILA B63 */
+ >;
+ };
+
+ /* Aquila QSPI_1 (8-bit) */
+ pinctrl_mcu_ospi0_8bit: mcu-ospi0-8bit-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ /* AQUILA B65 */
+ J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ /* AQUILA B68 */
+ J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ /* AQUILA B67 */
+ J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ /* AQUILA B61 */
+ J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ /* AQUILA B60 */
+ J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ /* AQUILA B70 */
+ J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ /* AQUILA B71 */
+ J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ /* AQUILA B72 */
+ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ /* AQUILA B73 */
+ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ /* AQUILA B63 */
+ >;
+ };
+
+ /* Aquila QSPI_1_CS1# */
+ pinctrl_mcu_ospi0_cs0: mcu-ospi0-cs0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ /* AQUILA B66 */
+ >;
+ };
+
+ /* Aquila QSPI_1_CS2# */
+ pinctrl_mcu_ospi0_cs1: mcu-ospi0-cs1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (A33) MCU_OSPI0_CSn1 */ /* AQUILA B62 */
+ >;
+ };
+
+ /* Aquila QSPI_1_SCK as GPIO */
+ pinctrl_wkup_gpio_16: wkup-gpio0-16-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (E32) MCU_OSPI0_CLK.WKUP_GPIO0_16 */ /* AQUILA B65 */
+ >;
+ };
+
+ /* Aquila GPIO_04 */
+ pinctrl_gpio_04: wkup-gpio0-17-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (D32) MCU_OSPI0_LBCLKO.WKUP_GPIO0_17 */ /* AQUILA C20 */
+ >;
+ };
+
+ /* Aquila QSPI_1_DQS as GPIO */
+ pinctrl_wkup_gpio_18: wkup-gpio0-18-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (C34) MCU_OSPI0_DQS.WKUP_GPIO0_18 */ /* AQUILA B63 */
+ >;
+ };
+
+ /* Aquila QSPI_1_IO0 as GPIO */
+ pinctrl_wkup_gpio_19: wkup-gpio0-19-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (B33) MCU_OSPI0_D0.WKUP_GPIO0_19 */ /* AQUILA B68 */
+ >;
+ };
+
+ /* Aquila QSPI_1_IO1 as GPIO */
+ pinctrl_wkup_gpio_20: wkup-gpio0-20-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (B32) MCU_OSPI0_D1.WKUP_GPIO0_20 */ /* AQUILA B67 */
+ >;
+ };
+
+ /* Aquila QSPI_1_IO2 as GPIO */
+ pinctrl_wkup_gpio_21: wkup-gpio0-21-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (C33) MCU_OSPI0_D2.WKUP_GPIO0_21 */ /* AQUILA B61 */
+ >;
+ };
+
+ /* Aquila QSPI_1_IO3 as GPIO */
+ pinctrl_wkup_gpio_22: wkup-gpio0-22-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 7) /* (C35) MCU_OSPI0_D3.WKUP_GPIO0_22 */ /* AQUILA B60 */
+ >;
+ };
+
+ /* Aquila QSPI_1_IO4 as GPIO */
+ pinctrl_wkup_gpio_23: wkup-gpio0-23-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 7) /* (D33) MCU_OSPI0_D4.WKUP_GPIO0_23 */ /* AQUILA B70 */
+ >;
+ };
+
+ /* Aquila QSPI_1_IO5 as GPIO */
+ pinctrl_wkup_gpio_24: wkup-gpio0-24-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (D34) MCU_OSPI0_D5.WKUP_GPIO0_24 */ /* AQUILA B71 */
+ >;
+ };
+
+ /* Aquila QSPI_1_IO6 as GPIO */
+ pinctrl_wkup_gpio_25: wkup-gpio0-25-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (E34) MCU_OSPI0_D6.WKUP_GPIO0_25 */ /* AQUILA B72 */
+ >;
+ };
+
+ /* Aquila QSPI_1_IO7 as GPIO */
+ pinctrl_wkup_gpio_26: wkup-gpio0-26-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (E33) MCU_OSPI0_D7.WKUP_GPIO0_26 */ /* AQUILA B73 */
+ >;
+ };
+
+ /* Aquila QSPI_1_CS#1 as GPIO */
+ pinctrl_wkup_gpio_27: wkup-gpio0-27-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 7) /* (A32) MCU_OSPI0_CSn0.WKUP_GPIO0_27 */ /* AQUILA B66 */
+ >;
+ };
+
+ /* Aquila QSPI_1_CS#2 as GPIO */
+ pinctrl_wkup_gpio_28: wkup-gpio0-28-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 7) /* (A33) MCU_OSPI0_CSn1.WKUP_GPIO0_28 */ /* AQUILA B62 */
+ >;
+ };
+};
+
+&wkup_pmx1 {
+ /* Aquila UART_4 (RXD) */
+ pinctrl_mcu_uart0_rx: mcu-uart0-rx-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 4) /* (D31) MCU_OSPI1_D1.MCU_UART0_RXD */ /* AQUILA D21 */
+ >;
+ };
+
+ /* Aquila GPIO_05 */
+ pinctrl_gpio_05: wkup-gpio0-29-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (B34) MCU_OSPI0_CSn2.WKUP_GPIO0_29 */ /* AQUILA C21 */
+ >;
+ };
+
+ /* Aquila GPIO_06 */
+ pinctrl_gpio_06: wkup-gpio0-30-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 7) /* (C32) MCU_OSPI0_CSn3.WKUP_GPIO0_30 */ /* AQUILA C22 */
+ >;
+ };
+
+ /* Aquila GPIO_07 */
+ pinctrl_gpio_07: wkup-gpio0-31-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 7) /* (F32) MCU_OSPI1_CLK.WKUP_GPIO0_31 */ /* AQUILA C23 */
+ >;
+ };
+
+ /* Aquila GPIO_13_CSI_2 */
+ pinctrl_gpio_13_csi_2: wkup-gpio0-32-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 7) /* (C31) MCU_OSPI1_LBCLKO.WKUP_GPIO0_32 */ /* AQUILA C1 */
+ >;
+ };
+
+ /* Aquila GPIO_14_CSI_2 */
+ pinctrl_gpio_14_csi_2: wkup-gpio0-33-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 7) /* (F31) MCU_OSPI1_DQS.WKUP_GPIO0_33 */ /* AQUILA C2 */
+ >;
+ };
+
+ /* RTC_IRQ# */
+ pinctrl_rtc_irq: wkup-gpio0-34-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 7) /* (E35) MCU_OSPI1_D0.WKUP_GPIO0_34 */
+ >;
+ };
+
+ /* Aquila CTRL_PWR_BTN_MICO# (PWR_BTN_INT#) */
+ pinctrl_pwr_btn_int: wkup-gpio0-36-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x01c, PIN_INPUT_PULLUP, 7) /* (G31) MCU_OSPI1_D2.WKUP_GPIO0_36 */ /* AQUILA B92 */
+ >;
+ };
+
+ /* Aquila GPIO_15_CSI_2 */
+ pinctrl_gpio_15_csi_2: wkup-gpio0-37-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 7) /* (F33) MCU_OSPI1_D3.WKUP_GPIO0_37 */ /* AQUILA C3 */
+ >;
+ };
+
+ /* Aquila GPIO_08 */
+ pinctrl_gpio_08: wkup-gpio0-38-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 7) /* (G32) MCU_OSPI1_CSn0.WKUP_GPIO0_38 */ /* AQUILA C24 */
+ >;
+ };
+
+ /* Aquila GPIO_16_CSI_2 */
+ pinctrl_gpio_16_csi_2: wkup-gpio0-39-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ /* AQUILA C4 */
+ >;
+ };
+};
+
+&wkup_pmx2 {
+ /* Aquila ADC_[1-4] */
+ pinctrl_mcu_adc0: mcu-adc0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (P36) MCU_ADC0_AIN0 */ /* AQUILA D1 */
+ J784S4_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (V36) MCU_ADC0_AIN1 */ /* AQUILA D2 */
+ J784S4_WKUP_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (T34) MCU_ADC0_AIN2 */ /* AQUILA D3 */
+ J784S4_WKUP_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (T36) MCU_ADC0_AIN3 */ /* AQUILA D4 */
+ >;
+ };
+
+ /* Aquila CTRL_MCLK_MOCI */
+ pinctrl_mcu_clkout0: mcu-clkout0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x084, PIN_OUTPUT, 6) /* (M38) WKUP_GPIO0_11.MCU_CLKOUT0 */ /* AQUILA A14 */
+ >;
+ };
+
+ /* Aquila I2C_1 */
+ pinctrl_mcu_i2c0: mcu-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (M35) MCU_I2C0_SCL */ /* AQUILA D8 */
+ J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (G34) MCU_I2C0_SDA */ /* AQUILA D7 */
+ >;
+ };
+
+ /* Aquila I2C_2 */
+ pinctrl_mcu_i2c1: mcu-i2c1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ /* AQUILA C17 */
+ J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ /* AQUILA C16 */
+ >;
+ };
+
+ /* Aquila CAN_2 */
+ pinctrl_mcu_mcan0: mcu-mcan0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ /* AQUILA B51 */
+ J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ /* AQUILA B50 */
+ >;
+ };
+
+ /* Aquila CAN_4 */
+ pinctrl_mcu_mcan1: mcu-mcan1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ /* AQUILA B56 */
+ J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ /* AQUILA B55 */
+ >;
+ };
+
+ /* On-module ETH_1 MDIO */
+ pinctrl_mcu_mdio: mcu-mdio-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
+ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
+ >;
+ };
+
+ /* On-module ETH_1 RGMII */
+ pinctrl_mcu_rgmii1: mcu-rgmii1-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
+ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
+ J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
+ J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
+ J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
+ J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
+ J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
+ J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
+ J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
+ J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
+ J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
+ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
+ >;
+ };
+
+ /* On-module SPI (TPM_SPI) */
+ pinctrl_mcu_spi0: mcu-spi0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (G38) MCU_SPI0_CLK */
+ J784S4_WKUP_IOPAD(0x044, PIN_OUTPUT, 0) /* (F37) MCU_SPI0_CS0 */
+ J784S4_WKUP_IOPAD(0x03c, PIN_INPUT, 0) /* (H36) MCU_SPI0_D0 */
+ J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (J38) MCU_SPI0_D1 */
+ >;
+ };
+
+ /* Aquila UART_4 (TX) */
+ pinctrl_mcu_uart0_tx: mcu-uart0-tx-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 2) /* (L33) WKUP_GPIO0_10.MCU_UART0_TXD */ /* AQUILA D22 */
+ >;
+ };
+
+ /* On-module Wi-Fi Power Enable */
+ pinctrl_en_3v3_wifi: wkup-gpio0-57-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */
+ >;
+ };
+
+ /* On-module TPM IRQ# */
+ pinctrl_tpm_irq: wkup-gpio0-81-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 7) /* (V34) MCU_ADC1_AIN2.WKUP_GPIO0_81 */
+ >;
+ };
+
+ /* On-module I2C - WKUP_I2C0 */
+ pinctrl_wkup_i2c0: wkup-i2c0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */
+ J784S4_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */
+ >;
+ };
+
+ /* Aquila UART_2 */
+ pinctrl_wkup_uart0: wkup-uart0-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ /* AQUILA B32 */
+ J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ /* AQUILA B34 */
+ J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ /* AQUILA B31 */
+ J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ /* AQUILA B33 */
+ >;
+ };
+};
+
+&wkup_pmx3 {
+ /* Aquila CTRL_WAKE1_MICO# */
+ pinctrl_ctrl_wake1_mico: wkup-gpio0-49-default-pins {
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x000, PIN_INPUT_PULLUP, 7) /* (M33) WKUP_GPIO0_49 */ /* AQUILA D6 */
+ >;
+ };
+};
+
+/* Aquila I2S_1_MCLK */
+&audio_refclk1 {
+ assigned-clock-rates = <24576000>;
+};
+
+/* On-module ETH_1 MDIO */
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_mdio>;
+ status = "disabled";
+
+ mcu_phy0: ethernet-phy at 0 {
+ reg = <0>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <79 IRQ_TYPE_EDGE_FALLING>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&dss {
+ assigned-clocks = <&k3_clks 218 2>,
+ <&k3_clks 218 5>;
+ assigned-clock-parents = <&k3_clks 218 3>,
+ <&k3_clks 218 7>;
+ status = "disabled";
+};
+
+&dss_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+};
+
+&main0_crit {
+ temperature = <105000>;
+};
+
+&main0_thermal {
+ trips {
+ main0_alert0: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ main0_alert1: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
+&main1_crit {
+ temperature = <105000>;
+};
+
+&main1_thermal {
+ trips {
+ main1_alert0: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ main1_alert1: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
+&main2_crit {
+ temperature = <105000>;
+};
+
+&main2_thermal {
+ trips {
+ main2_alert0: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ main2_alert1: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
+&main3_crit {
+ temperature = <105000>;
+};
+
+&main3_thermal {
+ trips {
+ main3_alert0: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ main3_alert1: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
+&main4_crit {
+ temperature = <105000>;
+};
+
+&main4_thermal {
+ trips {
+ main4_alert0: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ main4_alert1: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
+/* Aquila ETH_2 SGMII PHY */
+&main_cpsw0_port8 {
+ phy-mode = "sgmii";
+ phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_sgmii_link>;
+ phy-names = "mac", "serdes";
+ status = "disabled";
+};
+
+/* Aquila ETH_2_XGMII_MDIO */
+&main_cpsw0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_mdio1>;
+};
+
+/* Aquila PWM_1 */
+&main_ehrpwm0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_ehrpwm0_b>;
+ status = "disabled";
+};
+
+/* Aquila PWM_2 */
+&main_ehrpwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_ehrpwm1_a>;
+ status = "disabled";
+};
+
+/* Aquila PWM_4_DP */
+&main_ehrpwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_ehrpwm2_a>;
+ status = "disabled";
+};
+
+/* Aquila PWM_3_DSI */
+&main_ehrpwm5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_ehrpwm5_a>;
+ status = "disabled";
+};
+
+&main_gpio0 {
+ gpio-line-names =
+ "", /* 0 */
+ "AQUILA_B17",
+ "AQUILA_B18",
+ "AQUILA_B53",
+ "AQUILA_B54",
+ "AQUILA_B59",
+ "AQUILA_C18",
+ "AQUILA_C19",
+ "AQUILA_A13",
+ "AQUILA_A12",
+ "AQUILA_B75", /* 10 */
+ "AQUILA_B77",
+ "AQUILA_B42",
+ "AQUILA_B44",
+ "AQUILA_D19",
+ "AQUILA_D20",
+ "AQUILA_B58",
+ "AQUILA_D24",
+ "AQUILA_B45",
+ "AQUILA_C06",
+ "AQUILA_C05", /* 20 */
+ "AQUILA_B57",
+ "AQUILA_B90",
+ "AQUILA_B89",
+ "AQUILA_C26",
+ "AQUILA_C25",
+ "AQUILA_B22",
+ "AQUILA_B21",
+ "AQUILA_B74",
+ "AQUILA_D25",
+ "AQUILA_B24", /* 30 */
+ "AQUILA_B43",
+ "AQUILA_C38",
+ "AQUILA_B46",
+ "AQUILA_D23",
+ "AQUILA_B35",
+ "AQUILA_B37",
+ "AQUILA_B36",
+ "AQUILA_B38",
+ "AQUILA_D09",
+ "AQUILA_D12", /* 40 */
+ "AQUILA_C35",
+ "AQUILA_D10",
+ "AQUILA_D11",
+ "AQUILA_B81",
+ "AQUILA_B48",
+ "AQUILA_B49",
+ "AQUILA_A11",
+ "AQUILA_B19",
+ "AQUILA_B23",
+ "AQUILA_B20", /* 50 */
+ "AQUILA_D16",
+ "AQUILA_A06",
+ "AQUILA_D14",
+ "AQUILA_D15",
+ "AQUILA_D17",
+ "AQUILA_B41",
+ "AQUILA_B40",
+ "AQUILA_A01",
+ "",
+ "AQUILA_A08", /* 60 */
+ "AQUILA_A10",
+ "AQUILA_A02",
+ "AQUILA_A03",
+ "AQUILA_A05",
+ "AQUILA_A07";
+
+ status = "okay";
+};
+
+/* Aquila I2C_3_DSI1 */
+&main_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_i2c0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+};
+
+/* Aquila I2C_4_CSI1 */
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_i2c1>;
+ clock-frequency = <400000>;
+ status = "disabled";
+};
+
+/* Aquila I2C_5_CSI2 */
+&main_i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_i2c2>;
+ clock-frequency = <400000>;
+ status = "disabled";
+};
+
+/* Aquila I2C_6 */
+&main_i2c5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_i2c5>;
+ clock-frequency = <400000>;
+ status = "disabled";
+};
+
+/* Aquila CAN_1 */
+&main_mcan10 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_mcan10>;
+ status = "disabled";
+};
+
+/* Aquila CAN_3 */
+&main_mcan13 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_mcan13>;
+ status = "disabled";
+};
+
+/* On-module eMMC */
+&main_sdhci0 {
+ disable-wp;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ status = "okay";
+};
+
+/* Aquila SD_1 */
+&main_sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_mmc1>, <&pinctrl_sd1_cd_gpio>;
+ cd-gpios = <&main_gpio0 58 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ vmmc-supply = <®_sdhc1_vmmc>;
+ vqmmc-supply = <®_sdhc1_vqmmc>;
+ ti,driver-strength-ohm = <50>;
+ ti,fails-without-test-cd;
+ status = "disabled";
+};
+
+/* Aquila SPI_2 */
+&main_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_spi0>, <&pinctrl_main_spi0_cs0>;
+ status = "disabled";
+};
+
+/* Aquila SPI_1 */
+&main_spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_spi2>, <&pinctrl_main_spi2_cs0>;
+ status = "disabled";
+};
+
+/* Aquila UART_1 */
+&main_uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_uart4>;
+ status = "disabled";
+};
+
+/* Aquila UART_3, used as the Linux console */
+&main_uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_uart8>;
+ status = "disabled";
+};
+
+/* Aquila I2S_1 */
+&mcasp4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_mcasp4>;
+ op-mode = <0>; /* MCASP_I2S_MODE */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 1 2 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tdm-slots = <2>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+};
+
+&mcu_cpsw {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_rgmii1>;
+ status = "disabled";
+};
+
+/* On-module ETH_1 RGMII */
+&mcu_cpsw_port1 {
+ phy-handle = <&mcu_phy0>;
+ phy-mode = "rgmii-id";
+ status = "disabled";
+};
+
+/* Aquila I2C_1 */
+&mcu_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_i2c0>;
+ clock-frequency = <400000>;
+ status = "disabled";
+};
+
+/* Aquila I2C_2 */
+&mcu_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_i2c1>;
+ clock-frequency = <400000>;
+ status = "disabled";
+};
+
+/* Aquila CAN_2 */
+&mcu_mcan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_mcan0>;
+ status = "disabled";
+};
+
+/* Aquila CAN_4 */
+&mcu_mcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_mcan1>;
+ status = "disabled";
+};
+
+/* On-module SPI (TPM_SPI) */
+&mcu_spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_spi0>;
+ status = "okay";
+
+ tpm at 0 {
+ compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
+ reg = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm_irq>;
+ interrupt-parent = <&wkup_gpio0>;
+ interrupts = <81 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <33000000>;
+ };
+};
+
+/* Aquila UART_4 */
+&mcu_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_uart0_rx>, <&pinctrl_mcu_uart0_tx>;
+ status = "disabled";
+};
+
+&mhdp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_main_dp0_hpd>;
+ phy-names = "dpphy";
+ phys = <&serdes4_dp0_link>;
+ status = "disabled";
+};
+
+/* Aquila QSPI_1 */
+&ospi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_ospi0_8bit>, <&pinctrl_mcu_ospi0_cs0>;
+ status = "disabled";
+};
+
+/* Aquila PCIE_1 */
+&pcie0_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0_reset>;
+ clocks = <&k3_clks 332 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ num-lanes = <2>;
+ phy-names = "pcie-phy";
+ phys = <&serdes1_pcie0_2l_link>;
+ reset-gpios = <&main_gpio0 32 GPIO_ACTIVE_HIGH>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>;
+ status = "disabled";
+};
+
+/* Aquila PCIE_2 */
+&pcie1_rc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie1_reset>;
+ clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ num-lanes = <2>;
+ phy-names = "pcie-phy";
+ phys = <&serdes0_pcie1_2l_link>;
+ reset-gpios = <&main_gpio0 41 GPIO_ACTIVE_HIGH>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>;
+ status = "disabled";
+};
+
+/* On-module PCIe USB Bridge */
+&pcie2_rc {
+ clocks = <&k3_clks 334 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ num-lanes = <1>;
+ phy-names = "pcie-phy";
+ phys = <&serdes1_pcie2_1l_link>;
+ reset-gpios = <&som_gpio_expander 3 GPIO_ACTIVE_HIGH>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie1_proxy_ctrl 0x3>;
+ status = "okay";
+
+ pci at 0,0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ usb at 0 {
+ compatible = "pci104c,8241";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ ti,pwron-active-high;
+ };
+ };
+};
+
+/* PCIE for On-module Wi-Fi */
+&pcie3_rc {
+ clocks = <&k3_clks 335 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ num-lanes = <1>;
+ phy-names = "pcie-phy";
+ phys = <&serdes0_pcie3_1l_link>;
+ reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_HIGH>;
+ ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x3>;
+ status = "okay";
+};
+
+&serdes0 {
+ status = "okay";
+
+ /* Aquila PCIE_2 */
+ serdes0_pcie1_2l_link: phy at 0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
+ cdns,num-lanes = <2>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ };
+
+ /* On-module PCIe Wi-Fi */
+ serdes0_pcie3_1l_link: phy at 2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz0 3>;
+ cdns,num-lanes = <1>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ };
+
+ /* Aquila USB0 SS */
+ serdes0_usb0_ss_link: phy at 3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz0 4>;
+ cdns,num-lanes = <1>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ };
+};
+
+&serdes1 {
+ status = "okay";
+
+ /* Aquila PCIE_1 */
+ serdes1_pcie0_2l_link: phy at 0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
+ cdns,num-lanes = <2>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ };
+
+ /* On-module PCIe USB Bridge */
+ serdes1_pcie2_1l_link: phy at 2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz1 3>;
+ cdns,num-lanes = <1>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ };
+};
+
+&serdes2 {
+ status = "disabled";
+
+ /* Aquila ETH_2 xGMII */
+ serdes2_sgmii_link: phy at 3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz2 4>;
+ cdns,num-lanes = <1>;
+ cdns,phy-type = <PHY_TYPE_SGMII>;
+ };
+};
+
+&serdes4 {
+ status = "disabled";
+
+ /* Aquila DP_1 */
+ serdes4_dp0_link: phy at 0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
+ <&serdes_wiz4 3>, <&serdes_wiz4 4>;
+ cdns,max-bit-rate = <5400>;
+ cdns,num-lanes = <4>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ };
+};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+ status = "okay";
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, /* Aquila PCIE_2 L0 */
+ <J784S4_SERDES0_LANE1_PCIE1_LANE1>, /* Aquila PCIE_2 L1 */
+ <J784S4_SERDES0_LANE2_PCIE3_LANE0>, /* On-module PCIe Wi-Fi */
+ <J784S4_SERDES0_LANE3_USB>, /* Aquila USB0 SS */
+ <J784S4_SERDES1_LANE0_PCIE0_LANE0>, /* Aquila PCIE_1 L0 */
+ <J784S4_SERDES1_LANE1_PCIE0_LANE1>, /* Aquila PCIE_1 L1 */
+ <J784S4_SERDES1_LANE2_PCIE2_LANE0>, /* On-module PCIe USB Bridge */
+ <J784S4_SERDES1_LANE3_QSGMII_LANE2>, /* Aquila SGMII MSP_9 */
+ <J784S4_SERDES2_LANE0_QSGMII_LANE5>, /* Aquila SGMII MSP_6 */
+ <J784S4_SERDES2_LANE1_QSGMII_LANE6>, /* Aquila SGMII MSP_7 */
+ <J784S4_SERDES2_LANE2_QSGMII_LANE7>, /* Aquila SGMII MSP_8 */
+ <J784S4_SERDES2_LANE3_QSGMII_LANE8>, /* Aquila ETH_2 xGMII */
+ <J784S4_SERDES4_LANE0_EDP_LANE0>, /* Aquila DP L0 */
+ <J784S4_SERDES4_LANE1_EDP_LANE1>, /* Aquila DP L1 */
+ <J784S4_SERDES4_LANE2_EDP_LANE2>, /* Aquila DP L2 */
+ <J784S4_SERDES4_LANE3_EDP_LANE3>; /* Aquila DP L3 */
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&serdes_wiz1 {
+ status = "okay";
+};
+
+&serdes_wiz2 {
+ status = "disabled";
+};
+
+&serdes_wiz4 {
+ status = "disabled";
+};
+
+/* Aquila ADC_[1-4] */
+&tscadc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mcu_adc0>;
+ status = "disabled";
+
+ adc {
+ ti,adc-channels = <0 1 2 3>;
+ };
+};
+
+&usb0 {
+ phys = <&serdes0_usb0_ss_link>;
+ phy-names = "cdns3,usb3-phy";
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ usb-role-switch;
+ status = "disabled";
+};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "disabled";
+};
+
+&wkup_gpio0 {
+ gpio-line-names =
+ "", /* 0 */
+ "",
+ "",
+ "AQUILA_C53",
+ "AQUILA_B55",
+ "AQUILA_B56",
+ "AQUILA_B32",
+ "AQUILA_B34",
+ "AQUILA_C17",
+ "AQUILA_C16",
+ "AQUILA_D22", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AQUILA_B65",
+ "AQUILA_C20",
+ "AQUILA_B63",
+ "AQUILA_B68",
+ "AQUILA_B67", /* 20 */
+ "AQUILA_B61",
+ "AQUILA_B60",
+ "AQUILA_B70",
+ "AQUILA_B71",
+ "AQUILA_B72",
+ "AQUILC_B73",
+ "AQUILA_B66",
+ "AQUILA_B62",
+ "AQUILA_C21",
+ "AQUILA_C22", /* 30 */
+ "AQUILA_C23",
+ "AQUILA_C01",
+ "AQUILA_C02",
+ "",
+ "AQUILA_D21",
+ "",
+ "AQUILA_C03",
+ "AQUILA_C24",
+ "AQUILA_C04",
+ "AQUILA_B84", /* 40 */
+ "",
+ "AQUILA_B86",
+ "AQUILA_B87",
+ "",
+ "",
+ "AQUILA_B83",
+ "",
+ "",
+ "",
+ "", /* 50 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AQUILA_B31",
+ "AQUILA_B33",
+ "AQUILA_B50", /* 60 */
+ "AQUILA_B51",
+ "",
+ "",
+ "",
+ "AQUILA_D08",
+ "",
+ "",
+ "",
+ "",
+ "", /* 70 */
+ "AQUILA_D01",
+ "AQUILA_D02",
+ "AQUILA_D03",
+ "AQUILA_D04",
+ "AQUILA_D54",
+ "AQUILA_D55",
+ "AQUILA_C55",
+ "AQUILA_C56",
+ "",
+ "AQUILA_C36", /* 80 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "AQUILA_D07",
+ "";
+
+ status = "okay";
+};
+
+/* On-module I2C - WKUP_I2C0 */
+&wkup_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wkup_i2c0>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ som_gpio_expander: gpio at 21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names =
+ "USB_MUX_SEL",
+ "COLD_RESET_REQ",
+ "PWR_DOWN_REQ",
+ "PCIE_3_RESET#",
+ "PCIE_4_RESET#",
+ "WIFI_DISABLE",
+ "BT_DISABLE",
+ "SDIO_PWR_SEL_3.3V";
+ };
+
+ rtc_i2c: rtc at 32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ };
+
+ tps62873a: regulator at 40 {
+ compatible = "ti,tps62873";
+ reg = <0x40>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <600000>;
+ regulator-name = "+VDD_CPU_AVS";
+ };
+
+ tps62873b: regulator at 43 {
+ compatible = "ti,tps62873";
+ reg = <0x43>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <840000>;
+ regulator-min-microvolt = <760000>;
+ regulator-name = "+V0.8_VDD_CORE";
+ };
+
+ pmic_tps6594: pmic at 48 {
+ compatible = "ti,tps6594-q1";
+ reg = <0x48>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic_int>;
+ interrupt-parent = <&main_gpio0>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ buck12-supply = <®_vin>;
+ buck3-supply = <®_vin>;
+ buck4-supply = <®_vin>;
+ buck5-supply = <®_vin>;
+ ldo1-supply = <®_vin>;
+ ldo2-supply = <®_vin>;
+ ldo3-supply = <®_vin>;
+ ldo4-supply = <®_vin>;
+ system-power-controller;
+ ti,primary-pmic;
+
+ regulators {
+ reg_vdd_ddr: buck12 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-name = "+V1.1_VDD_DDR (PMIC BUCK12)";
+ };
+
+ reg_vdd_ram: buck3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <850000>;
+ regulator-min-microvolt = <850000>;
+ regulator-name = "+V0.85_VDD_RAM (PMIC BUCK3)";
+ };
+
+ reg_vdd_io: buck4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_VDD_IO (PMIC BUCK4)";
+ };
+
+ reg_3v3_vio: buck5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3_VIO (PMIC BUCK5)";
+ };
+
+ reg_vda_phy: ldo1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_VDA_PHY (PMIC LDO1)";
+ };
+
+ reg_2v5_eth: ldo2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microvolt = <2500000>;
+ regulator-name = "+V2.5_ETH (PMIC LDO2)";
+ };
+
+ reg_vda_dll: ldo3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <800000>;
+ regulator-min-microvolt = <800000>;
+ regulator-name = "+V0.8_VDA_DLL (PMIC LDO3)";
+ };
+
+ reg_vda_pll: ldo4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V0.8_VDA_PLL (PMIC LDO4)";
+ };
+ };
+ };
+
+ temperature-sensor at 4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ som_eeprom: eeprom at 50 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+&wkup0_crit {
+ temperature = <105000>;
+};
+
+&wkup0_thermal {
+ trips {
+ wkup0_alert0: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ wkup0_alert1: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
+&wkup1_crit {
+ temperature = <105000>;
+};
+
+&wkup1_thermal {
+ trips {
+ wkup1_alert0: trip-point0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ wkup1_alert1: trip-point1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+};
+
+&wkup_gpio_intr {
+ status = "okay";
+};
+
+/* Aquila UART_2 */
+&wkup_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wkup_uart0>;
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am69-r5-aquila-dev.dts b/arch/arm/dts/k3-am69-r5-aquila-dev.dts
new file mode 100644
index 000000000000..226431bb152d
--- /dev/null
+++ b/arch/arm/dts/k3-am69-r5-aquila-dev.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am69-aquila-dev.dts"
+#include "k3-am69-aquila-lpddr4-4266.dtsi"
+#include "k3-j784s4-ddr.dtsi"
+#include "k3-am69-aquila-dev-u-boot.dtsi"
+#include "k3-j784s4-r5.dtsi"
+
+&pmic_tps6594 {
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
+};
diff --git a/arch/arm/mach-k3/j784s4/Kconfig b/arch/arm/mach-k3/j784s4/Kconfig
index 84194f6efa8d..fff44dbf7c9a 100644
--- a/arch/arm/mach-k3/j784s4/Kconfig
+++ b/arch/arm/mach-k3/j784s4/Kconfig
@@ -9,6 +9,23 @@ choice
prompt "K3 J784S4 board"
optional
+config TARGET_AQUILA_AM69_A72
+ bool "Toradex Aquila AM69 running on A72"
+ select ARM64
+ select SYS_DISABLE_DCACHE_OPS
+ select BINMAN
+
+config TARGET_AQUILA_AM69_R5
+ bool "Toradex Aquila AM69 running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ select BINMAN
+ imply SYS_K3_SPL_ATF
+
config TARGET_J784S4_A72_EVM
bool "TI K3 based J784S4 EVM running on A72"
select ARM64
@@ -48,5 +65,6 @@ config TARGET_J742S2_R5_EVM
endchoice
source "board/ti/j784s4/Kconfig"
+source "board/toradex/aquila-am69/Kconfig"
endif
diff --git a/board/toradex/aquila-am69/Kconfig b/board/toradex/aquila-am69/Kconfig
new file mode 100644
index 000000000000..6afa97e2c828
--- /dev/null
+++ b/board/toradex/aquila-am69/Kconfig
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+
+if TARGET_AQUILA_AM69_A72
+
+config SYS_BOARD
+ default "aquila-am69"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "aquila-am69"
+
+config TDX_CFG_BLOCK
+ default y
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+ default y
+
+config TDX_CFG_BLOCK_DEV
+ default "0"
+
+config TDX_CFG_BLOCK_EXTRA
+ default y
+
+config TDX_CFG_BLOCK_OFFSET
+ default "-512"
+
+config TDX_CFG_BLOCK_PART
+ default "1"
+
+config TDX_HAVE_EEPROM_EXTRA
+ default y
+
+config TDX_HAVE_MMC
+ default y
+
+source "board/toradex/common/Kconfig"
+
+endif
+
+if TARGET_AQUILA_AM69_R5
+
+config SYS_BOARD
+ default "aquila-am69"
+
+config SYS_VENDOR
+ default "toradex"
+
+config SYS_CONFIG_NAME
+ default "aquila-am69"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/toradex/aquila-am69/MAINTAINERS b/board/toradex/aquila-am69/MAINTAINERS
new file mode 100644
index 000000000000..f629ba4a019e
--- /dev/null
+++ b/board/toradex/aquila-am69/MAINTAINERS
@@ -0,0 +1,13 @@
+AQUILA AM69
+M: Francesco Dolcini <francesco.dolcini at toradex.com>
+W: https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
+S: Maintained
+F: arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
+F: arch/arm/dts/k3-am69-aquila-dev.dts
+F: arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi
+F: arch/arm/dts/k3-am69-aquila.dtsi
+F: arch/arm/dts/k3-am69-r5-aquila-dev.dts
+F: board/toradex/aquila-am69
+F: configs/aquila-am69_a72_defconfig
+F: configs/aquila-am69_r5_defconfig
+F: include/configs/aquila-am69.h
diff --git a/board/toradex/aquila-am69/Makefile b/board/toradex/aquila-am69/Makefile
new file mode 100644
index 000000000000..aa71c4bbb210
--- /dev/null
+++ b/board/toradex/aquila-am69/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+
+obj-y += aquila-am69.o
+obj-y += ddrs_patch.o
+obj-y += aquila_ddrs_16GB.o
+obj-y += aquila_ddrs_8GB.o
diff --git a/board/toradex/aquila-am69/aquila-am69.c b/board/toradex/aquila-am69/aquila-am69.c
new file mode 100644
index 000000000000..98b9bfc5aa4b
--- /dev/null
+++ b/board/toradex/aquila-am69/aquila-am69.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Board specific initialization for Aquila AM69 SoM
+ *
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#include <asm/arch/k3-common-fdt.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <spl.h>
+
+#include "../common/tdx-common.h"
+#include "aquila_ddrs_16GB.h"
+#include "aquila_ddrs_8GB.h"
+#include "ddrs_patch.h"
+
+#define CTRL_MMR_CFG0_MCU_ADC1_CTRL 0x40F040B4
+#define CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL 0x40F08010
+#define MCU_CLKOUT0_CTRL_CLK_EN BIT(4)
+
+#define HW_CFG_MEM_SZ_32GB 0x00
+#define HW_CFG_MEM_SZ_16GB 0x01
+#define HW_CFG_MEM_SZ_8GB 0x02
+
+#define HW_CFG_MEM_SZ_MASK 0x03
+
+DECLARE_GLOBAL_DATA_PTR;
+static u8 hw_cfg;
+
+static u64 aquila_am69_memory_size(void)
+{
+ switch (hw_cfg & HW_CFG_MEM_SZ_MASK) {
+ case HW_CFG_MEM_SZ_32GB:
+ return SZ_32G;
+ case HW_CFG_MEM_SZ_16GB:
+ return SZ_16G;
+ case HW_CFG_MEM_SZ_8GB:
+ return SZ_8G;
+ default:
+ puts("Invalid memory size configuration\n");
+ return -EINVAL;
+ }
+}
+
+static void read_hw_cfg(void)
+{
+ struct gpio_desc gpio_hw_cfg;
+ char gpio_name[20];
+ int i;
+
+ printf("HW CFG: ");
+ for (i = 0; i < 5; i++) {
+ sprintf(gpio_name, "gpio at 42110000_%d", 82 + i);
+ if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) {
+ printf("Lookup named gpio error\n");
+ return;
+ }
+
+ if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) {
+ printf("gpio request error\n");
+ return;
+ }
+
+ if (dm_gpio_get_value(&gpio_hw_cfg) == 1)
+ hw_cfg |= BIT(i);
+
+ dm_gpio_free(NULL, &gpio_hw_cfg);
+ }
+ printf("0x%02x\n", hw_cfg);
+}
+
+static void update_ddr_timings(void)
+{
+ int ret = 0;
+ void *fdt = (void *)gd->fdt_blob;
+
+ switch (aquila_am69_memory_size()) {
+ case SZ_8G:
+ ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB,
+ MULTI_DDR_CFG_INTRLV_SIZE_8GB);
+ break;
+ case SZ_16G:
+ ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB,
+ MULTI_DDR_CFG_INTRLV_SIZE_16GB);
+ break;
+ }
+
+ if (ret)
+ printf("Applying DDR patch error: %d\n", ret);
+}
+
+static int aquila_am69_fdt_fixup_memory_size(u64 total_sz)
+{
+ void *blob = (void *)gd->fdt_blob;
+
+ u64 s[CONFIG_NR_DRAM_BANKS] = {
+ CFG_SYS_SDRAM_BASE,
+ CFG_SYS_SDRAM_BASE1
+ };
+
+ u64 e[CONFIG_NR_DRAM_BANKS] = {
+ SZ_2G,
+ total_sz - SZ_2G
+ };
+
+ return fdt_fixup_memory_banks(blob, s, e, CONFIG_NR_DRAM_BANKS);
+}
+
+void do_board_detect(void)
+{
+ /* MCU_ADC1 pins used as General Purpose Inputs */
+ writel(readl(CTRL_MMR_CFG0_MCU_ADC1_CTRL) | BIT(16),
+ CTRL_MMR_CFG0_MCU_ADC1_CTRL);
+
+ read_hw_cfg();
+
+ if (IS_ENABLED(CONFIG_K3_DDRSS))
+ update_ddr_timings();
+}
+
+int dram_init(void)
+{
+ s32 ret;
+
+ ret = fdtdec_setup_mem_size_base_lowest();
+ if (ret)
+ printf("Error setting up mem size and base. %d\n", ret);
+
+ return ret;
+}
+
+int dram_init_banksize(void)
+{
+ s32 ret;
+
+ ret = aquila_am69_fdt_fixup_memory_size(aquila_am69_memory_size());
+ if (ret)
+ printf("Error setting memory size. %d\n", ret);
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ printf("Error setting up memory banksize. %d\n", ret);
+
+ return ret;
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x100000000)
+ return 0x100000000;
+#endif
+
+ return gd->ram_top;
+}
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret;
+
+ ret = fdt_fixup_msmc_ram_k3(blob);
+ if (ret)
+ return ret;
+
+ return ft_common_board_setup(blob, bd);
+}
+#endif
+
+void spl_board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_ESM_K3)) {
+ const char * const esms[] = {"esm at 700000", "esm at 40800000", "esm at 42080000"};
+
+ for (int i = 0; i < ARRAY_SIZE(esms); ++i) {
+ ret = uclass_get_device_by_name(UCLASS_MISC, esms[i],
+ &dev);
+ if (ret) {
+ printf("MISC init for %s failed: %d\n", esms[i], ret);
+ break;
+ }
+ }
+ }
+
+ if (IS_ENABLED(CONFIG_ESM_PMIC) && ret == 0) {
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(pmic_esm),
+ &dev);
+ if (ret)
+ printf("ESM PMIC init failed: %d\n", ret);
+ }
+
+ if (IS_ENABLED(CONFIG_TARGET_AQUILA_AM69_R5))
+ writel(readl(CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL) |
+ MCU_CLKOUT0_CTRL_CLK_EN,
+ CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL);
+}
diff --git a/board/toradex/aquila-am69/aquila-am69.env b/board/toradex/aquila-am69/aquila-am69.env
new file mode 100644
index 000000000000..f8b7363dcf51
--- /dev/null
+++ b/board/toradex/aquila-am69/aquila-am69.env
@@ -0,0 +1,41 @@
+#define CFG_RAMDISK_ADDR_R 0x90300000
+#define CFG_SCRIPTADDR 0x90280000
+
+boot_script_dhcp=boot.scr
+boot_targets=mmc1 mmc0 dhcp
+console=ttyS2
+fdt_addr_r=0x90200000
+fdt_board=dev
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0x80200000
+kernel_comp_size=0x08000000
+ramdisk_addr_r=CFG_RAMDISK_ADDR_R
+scriptaddr=CFG_SCRIPTADDR
+
+dfu_alt_info_ram=
+ tispl.bin ram 0x80080000 0x200000;
+ u-boot.img ram 0x81000000 0x400000;
+ loadaddr ram CONFIG_SYS_LOAD_ADDR 0x80000;
+ scriptaddr ram CFG_SCRIPTADDR 0x80000;
+ ramdisk_addr_r ram CFG_RAMDISK_ADDR_R 0x8000000
+
+update_tiboot3=
+ askenv confirm Did you load tiboot3.bin (y/N)?;
+ if test $confirm = y; then
+ setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200;
+ mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt};
+ fi
+
+update_tispl=
+ askenv confirm Did you load tispl.bin (y/N)?;
+ if test $confirm = y; then
+ setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200;
+ mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt};
+ fi
+
+update_uboot=
+ askenv confirm Did you load u-boot.img (y/N)?;
+ if test $confirm = y; then
+ setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200;
+ mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt};
+ fi
diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB.c b/board/toradex/aquila-am69/aquila_ddrs_16GB.c
new file mode 100644
index 000000000000..009756abc95c
--- /dev/null
+++ b/board/toradex/aquila-am69/aquila_ddrs_16GB.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ * This contains a diff against the 32GB register settings created from the 16GB tool output.
+
+ * The 16GB dtsi file was generated with the following tool revisions:
+ * - SysConfig: Revision 1.23.1+4034
+ * - Jacinto7_DDRSS_RegConfigTool: Revision 0.11.0
+ * It was generated on Fri May 16 2025 17:28:31 GMT+0200 (Central European Summer Time)
+ */
+
+#include <asm/u-boot.h>
+#include <linux/kernel.h>
+#include "ddrs_patch.h"
+
+#define DDRSS_PLL_FHS_CNT 3
+
+#define DDRSS_CTL_267_DATA 0x01010101
+#define DDRSS_CTL_271_DATA 0xFFFFFFFF
+#define DDRSS_CTL_273_DATA 0x000003FF
+#define DDRSS_CTL_278_DATA 0x00010000
+#define DDRSS_CTL_287_DATA 0x00000100
+
+#define DDRSS_PI_14_DATA 0x08000005
+#define DDRSS_PI_29_DATA 0x05000000
+#define DDRSS_PI_45_DATA 0x00050500
+#define DDRSS_PI_55_DATA 0x05000000
+#define DDRSS_PI_67_DATA 0x00020205
+
+static struct ddr_reg_patch ctl_patch[] = {
+ { 267, DDRSS_CTL_267_DATA},
+ { 271, DDRSS_CTL_271_DATA},
+ { 273, DDRSS_CTL_273_DATA},
+ { 278, DDRSS_CTL_278_DATA},
+ { 287, DDRSS_CTL_287_DATA}
+};
+
+static struct ddr_reg_patch pi_patch[] = {
+ { 14, DDRSS_PI_14_DATA},
+ { 29, DDRSS_PI_29_DATA},
+ { 45, DDRSS_PI_45_DATA},
+ { 55, DDRSS_PI_55_DATA},
+ { 67, DDRSS_PI_67_DATA},
+};
+
+static struct ddrss_patch ddrss_ctrl_patch = {
+ .ddr_fhs_cnt = DDRSS_PLL_FHS_CNT,
+ .ctl_patch = ctl_patch,
+ .ctl_patch_num = ARRAY_SIZE(ctl_patch),
+ .pi_patch = pi_patch,
+ .pi_patch_num = ARRAY_SIZE(pi_patch),
+ .phy_patch = NULL,
+ .phy_patch_num = 0
+};
+
+struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4] = {
+ &ddrss_ctrl_patch,
+ &ddrss_ctrl_patch,
+ &ddrss_ctrl_patch,
+ &ddrss_ctrl_patch
+};
diff --git a/board/toradex/aquila-am69/aquila_ddrs_16GB.h b/board/toradex/aquila-am69/aquila_ddrs_16GB.h
new file mode 100644
index 000000000000..0740c0ef25cd
--- /dev/null
+++ b/board/toradex/aquila-am69/aquila_ddrs_16GB.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+#ifndef __AQUILA_DDRS_16GB_H
+#define __AQUILA_DDRS_16GB_H
+
+#define MULTI_DDR_CFG_INTRLV_SIZE_16GB 11
+extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4];
+
+#endif // __AQUILA_DDRS_16GB_H
diff --git a/board/toradex/aquila-am69/aquila_ddrs_8GB.c b/board/toradex/aquila-am69/aquila_ddrs_8GB.c
new file mode 100644
index 000000000000..3844b9eb5ba7
--- /dev/null
+++ b/board/toradex/aquila-am69/aquila_ddrs_8GB.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ * This contains a diff against the 32GB register settings created from the 8GB tool output.
+
+ * The 8GB dtsi file was generated with the following tool revisions:
+ * - SysConfig: Revision 1.23.1+4034
+ * - Jacinto7_DDRSS_RegConfigTool: Revision 0.11.0
+ * It was generated on Thu May 15 2025 10:35:37 GMT+0200 (Central European Summer Time)
+ */
+
+#include <asm/u-boot.h>
+#include <linux/kernel.h>
+#include "ddrs_patch.h"
+
+#define DDRSS_PLL_FHS_CNT 3
+
+#define DDRSS_CTL_60_DATA 0x00001008
+#define DDRSS_CTL_62_DATA 0x00000256
+#define DDRSS_CTL_64_DATA 0x00000256
+#define DDRSS_CTL_67_DATA 0x00040000
+#define DDRSS_CTL_68_DATA 0x00950005
+#define DDRSS_CTL_69_DATA 0x00950200
+#define DDRSS_CTL_79_DATA 0x00100010
+#define DDRSS_CTL_80_DATA 0x02660266
+#define DDRSS_CTL_81_DATA 0x02660266
+#define DDRSS_CTL_267_DATA 0x01010101
+#define DDRSS_CTL_268_DATA 0x01010000
+#define DDRSS_CTL_270_DATA 0x00000FFF
+#define DDRSS_CTL_271_DATA 0xFFFFFFFF
+#define DDRSS_CTL_272_DATA 0x01FF0000
+#define DDRSS_CTL_273_DATA 0x000001FF
+#define DDRSS_CTL_278_DATA 0x00010000
+#define DDRSS_CTL_287_DATA 0x00000100
+
+#define DDRSS_PI_14_DATA 0x08000005
+#define DDRSS_PI_29_DATA 0x05000000
+#define DDRSS_PI_45_DATA 0x00050500
+#define DDRSS_PI_55_DATA 0x05000000
+#define DDRSS_PI_67_DATA 0x00020205
+#define DDRSS_PI_73_DATA 0x00080100
+#define DDRSS_PI_169_DATA 0x00105012
+#define DDRSS_PI_171_DATA 0x00000256
+#define DDRSS_PI_173_DATA 0x00000256
+#define DDRSS_PI_235_DATA 0x02660010
+#define DDRSS_PI_236_DATA 0x03030266
+#define DDRSS_PI_241_DATA 0x00000010
+#define DDRSS_PI_246_DATA 0x00000266
+#define DDRSS_PI_251_DATA 0x01000266
+
+static struct ddr_reg_patch ctl_patch[] = {
+ { 60, DDRSS_CTL_60_DATA},
+ { 62, DDRSS_CTL_62_DATA},
+ { 64, DDRSS_CTL_64_DATA},
+ { 67, DDRSS_CTL_67_DATA},
+ { 68, DDRSS_CTL_68_DATA},
+ { 69, DDRSS_CTL_69_DATA},
+ { 79, DDRSS_CTL_79_DATA},
+ { 80, DDRSS_CTL_80_DATA},
+ { 81, DDRSS_CTL_81_DATA},
+ { 267, DDRSS_CTL_267_DATA},
+ { 268, DDRSS_CTL_268_DATA},
+ { 270, DDRSS_CTL_270_DATA},
+ { 271, DDRSS_CTL_271_DATA},
+ { 272, DDRSS_CTL_272_DATA},
+ { 273, DDRSS_CTL_273_DATA},
+ { 278, DDRSS_CTL_278_DATA},
+ { 287, DDRSS_CTL_287_DATA}
+};
+
+static struct ddr_reg_patch pi_patch[] = {
+ { 14, DDRSS_PI_14_DATA},
+ { 29, DDRSS_PI_29_DATA},
+ { 45, DDRSS_PI_45_DATA},
+ { 55, DDRSS_PI_55_DATA},
+ { 67, DDRSS_PI_67_DATA},
+ { 73, DDRSS_PI_73_DATA},
+ { 169, DDRSS_PI_169_DATA},
+ { 171, DDRSS_PI_171_DATA},
+ { 173, DDRSS_PI_173_DATA},
+ { 235, DDRSS_PI_235_DATA},
+ { 236, DDRSS_PI_236_DATA},
+ { 241, DDRSS_PI_241_DATA},
+ { 246, DDRSS_PI_246_DATA},
+ { 251, DDRSS_PI_251_DATA}
+};
+
+static struct ddrss_patch ddrss_ctrl_patch = {
+ .ddr_fhs_cnt = DDRSS_PLL_FHS_CNT,
+ .ctl_patch = ctl_patch,
+ .ctl_patch_num = ARRAY_SIZE(ctl_patch),
+ .pi_patch = pi_patch,
+ .pi_patch_num = ARRAY_SIZE(pi_patch),
+ .phy_patch = NULL,
+ .phy_patch_num = 0
+};
+
+struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4] = {
+ &ddrss_ctrl_patch,
+ &ddrss_ctrl_patch,
+ &ddrss_ctrl_patch,
+ &ddrss_ctrl_patch
+};
diff --git a/board/toradex/aquila-am69/aquila_ddrs_8GB.h b/board/toradex/aquila-am69/aquila_ddrs_8GB.h
new file mode 100644
index 000000000000..c82f236d55f5
--- /dev/null
+++ b/board/toradex/aquila-am69/aquila_ddrs_8GB.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+#ifndef __AQUILA_DDRS_8GB_H
+#define __AQUILA_DDRS_8GB_H
+
+#define MULTI_DDR_CFG_INTRLV_SIZE_8GB 9
+extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4];
+
+#endif // __AQUILA_DDRS_8GB_H
diff --git a/board/toradex/aquila-am69/board-cfg.yaml b/board/toradex/aquila-am69/board-cfg.yaml
new file mode 100644
index 000000000000..48ce2967cb50
--- /dev/null
+++ b/board/toradex/aquila-am69/board-cfg.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+# Board configuration for AM69
+#
+
+---
+
+board-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ control:
+ subhdr:
+ magic: 0xC1D3
+ size: 7
+ main_isolation_enable: 0x5A
+ main_isolation_hostid: 0x2
+ secproxy:
+ subhdr:
+ magic: 0x1207
+ size: 7
+ scaling_factor: 0x1
+ scaling_profile: 0x1
+ disable_main_nav_secure_proxy: 0
+ msmc:
+ subhdr:
+ magic: 0xA5C3
+ size: 5
+ msmc_cache_size: 0x8
+ debug_cfg:
+ subhdr:
+ magic: 0x020C
+ size: 8
+ trace_dst_enables: 0x00
+ trace_src_enables: 0x00
diff --git a/board/toradex/aquila-am69/ddrs_patch.c b/board/toradex/aquila-am69/ddrs_patch.c
new file mode 100644
index 000000000000..baac2637f001
--- /dev/null
+++ b/board/toradex/aquila-am69/ddrs_patch.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#include <fdt_support.h>
+#include <linux/errno.h>
+#include <stdint.h>
+
+#include "ddrs_patch.h"
+
+static int ftd_apply_ddrss_prop_patch(void *fdt, int mem_offset, const char *prop_name,
+ const struct ddr_reg_patch *patch_set, int patch_num)
+{
+ int ret;
+ int i;
+ u32 val;
+
+ for (i = 0; i < patch_num; i++, patch_set++) {
+ val = cpu_to_be32(patch_set->val);
+ ret = fdt_setprop_inplace_namelen_partial(fdt, mem_offset,
+ prop_name, strlen(prop_name),
+ patch_set->off * sizeof(u32),
+ &val, sizeof(u32));
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int fdt_apply_ddrss_patch(void *fdt, int msmc_offset, const char *ddrs_ctrl,
+ const struct ddrss_patch *ddrss_patch)
+{
+ int ret;
+ int mem_offset;
+
+ mem_offset = fdt_subnode_offset(fdt, msmc_offset, ddrs_ctrl);
+ if (mem_offset < 0)
+ return -ENODEV;
+
+ ret = fdt_setprop_inplace_u32(fdt, mem_offset, "ti,ddr-fhs-cnt", ddrss_patch->ddr_fhs_cnt);
+ if (ret)
+ return ret;
+
+ ret = ftd_apply_ddrss_prop_patch(fdt, mem_offset, "ti,ctl-data",
+ ddrss_patch->ctl_patch, ddrss_patch->ctl_patch_num);
+ if (ret)
+ return ret;
+
+ ret = ftd_apply_ddrss_prop_patch(fdt, mem_offset, "ti,pi-data",
+ ddrss_patch->pi_patch, ddrss_patch->pi_patch_num);
+ if (ret)
+ return ret;
+
+ ret = ftd_apply_ddrss_prop_patch(fdt, mem_offset, "ti,phy-data",
+ ddrss_patch->phy_patch, ddrss_patch->phy_patch_num);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+int aquila_am69_fdt_apply_ddr_patch(void *fdt, struct ddrss_patch *ddrss_patch[4], u32 intrlv_size)
+{
+ int ret;
+ int msmc_offset;
+
+ msmc_offset = fdt_path_offset(fdt, "/bus at 100000/bus at 30000000/msmc");
+ if (msmc_offset < 0)
+ return -ENODEV;
+
+ ret = fdt_setprop_inplace_u32(fdt, msmc_offset, "intrlv-size", intrlv_size);
+ if (ret)
+ return ret;
+
+ ret = fdt_apply_ddrss_patch(fdt, msmc_offset, "memorycontroller at 2990000", ddrss_patch[0]);
+ if (ret)
+ return ret;
+
+ ret = fdt_apply_ddrss_patch(fdt, msmc_offset, "memorycontroller at 29b0000", ddrss_patch[1]);
+ if (ret)
+ return ret;
+
+ ret = fdt_apply_ddrss_patch(fdt, msmc_offset, "memorycontroller at 29d0000", ddrss_patch[2]);
+ if (ret)
+ return ret;
+
+ ret = fdt_apply_ddrss_patch(fdt, msmc_offset, "memorycontroller at 29f0000", ddrss_patch[3]);
+ if (ret)
+ return ret;
+
+ return 0;
+}
diff --git a/board/toradex/aquila-am69/ddrs_patch.h b/board/toradex/aquila-am69/ddrs_patch.h
new file mode 100644
index 000000000000..2c79fd03a2a2
--- /dev/null
+++ b/board/toradex/aquila-am69/ddrs_patch.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#ifndef __AQUILA_AM69_DDRS_PATCH_H
+#define __AQUILA_AM69_DDRS_PATCH_H
+
+struct ddr_reg_patch {
+ u32 off;
+ u32 val;
+};
+
+struct ddrss_patch {
+ u32 ddr_fhs_cnt;
+ struct ddr_reg_patch *ctl_patch;
+ u32 ctl_patch_num;
+ struct ddr_reg_patch *pi_patch;
+ u32 pi_patch_num;
+ struct ddr_reg_patch *phy_patch;
+ u32 phy_patch_num;
+};
+
+/**
+ * aquila_am69_fdt_apply_ddr_patch - Apply DDRSS patches to the R5 U-Boot device tree
+ * @fdt: Pointer to the flattened device tree (FDT) blob in memory
+ * @ddrss_patch: Array of pointers to DDRSS patch structures (one per controller)
+ * @intrlv_size: Value to set for the "intrlv-size" property
+ *
+ * This function updates the MSMC node in the device tree by setting the
+ * "intrlv-size" property and applying DDRSS patches to each of the four
+ * memory controller nodes.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int aquila_am69_fdt_apply_ddr_patch(void *fdt, struct ddrss_patch *ddrss_patch[4], u32 intrlv_size);
+
+#endif // __AQUILA_AM69_DDRS_PATCH_H
diff --git a/board/toradex/aquila-am69/pm-cfg.yaml b/board/toradex/aquila-am69/pm-cfg.yaml
new file mode 100644
index 000000000000..8583da3d55ad
--- /dev/null
+++ b/board/toradex/aquila-am69/pm-cfg.yaml
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+# Power management configuration for AM69
+#
+
+---
+
+pm-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
diff --git a/board/toradex/aquila-am69/rm-cfg.yaml b/board/toradex/aquila-am69/rm-cfg.yaml
new file mode 100644
index 000000000000..02a753a0a9f1
--- /dev/null
+++ b/board/toradex/aquila-am69/rm-cfg.yaml
@@ -0,0 +1,3057 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J784S4
+#
+
+---
+
+rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - # 1
+ host_id: 3
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 2
+ host_id: 5
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 3
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 4
+ host_id: 13
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 5
+ host_id: 21
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 6
+ host_id: 23
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 7
+ host_id: 25
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 8
+ host_id: 27
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 9
+ host_id: 35
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 10
+ host_id: 37
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 11
+ host_id: 40
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 12
+ host_id: 42
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 13
+ host_id: 45
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 14
+ host_id: 47
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 15
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 16
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 17
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 18
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 19
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 20
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 21
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 22
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 23
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 24
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 25
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 26
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 27
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 28
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 29
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 30
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 31
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 32
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 3744
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 640
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 640
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 4
+ type: 640
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 4
+ type: 640
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 640
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 4
+ type: 640
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 4
+ type: 640
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 4
+ type: 640
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 12
+ type: 640
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 12
+ type: 640
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 704
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 11072
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 24
+ type: 11072
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 8
+ type: 11072
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 24
+ type: 11136
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 16
+ type: 11136
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 8
+ type: 11136
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 48
+ type: 11264
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 8
+ type: 11328
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 8
+ type: 11328
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 6
+ type: 11328
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 6
+ type: 11328
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 2
+ type: 11328
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 2
+ type: 11328
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 50176
+ num_resource: 96
+ type: 17986
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 17987
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 32
+ type: 17998
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 32
+ type: 17998
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 17999
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 17999
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 18017
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 18017
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 18018
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 18018
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 80
+ type: 18112
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 96
+ num_resource: 14
+ type: 18112
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 110
+ num_resource: 21
+ type: 18112
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 131
+ num_resource: 21
+ type: 18112
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 152
+ num_resource: 12
+ type: 18112
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 164
+ num_resource: 12
+ type: 18112
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 196
+ num_resource: 28
+ type: 18112
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 228
+ num_resource: 28
+ type: 18112
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 260
+ num_resource: 28
+ type: 18112
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 292
+ num_resource: 28
+ type: 18112
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 324
+ num_resource: 28
+ type: 18112
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 356
+ num_resource: 28
+ type: 18112
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 400
+ num_resource: 4
+ type: 18112
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 404
+ num_resource: 4
+ type: 18112
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 64
+ type: 19850
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 20480
+ num_resource: 1024
+ type: 19853
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 64
+ type: 19914
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 22528
+ num_resource: 1024
+ type: 19917
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 19968
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 19968
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 4
+ type: 19968
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 4
+ type: 19968
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 19968
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 4
+ type: 19968
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 12
+ type: 19968
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 4
+ type: 19968
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 4
+ type: 19968
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 4
+ type: 19968
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 48
+ num_resource: 4
+ type: 19968
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 4
+ type: 19968
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 4
+ type: 19968
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 60
+ num_resource: 4
+ type: 19968
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20160
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 423
+ num_resource: 10
+ type: 20161
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 433
+ num_resource: 20
+ type: 20161
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 453
+ num_resource: 16
+ type: 20161
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 469
+ num_resource: 13
+ type: 20161
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 482
+ num_resource: 128
+ type: 20161
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 610
+ num_resource: 46
+ type: 20161
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 656
+ num_resource: 10
+ type: 20161
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 666
+ num_resource: 20
+ type: 20161
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 686
+ num_resource: 64
+ type: 20161
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 750
+ num_resource: 10
+ type: 20161
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 760
+ num_resource: 4
+ type: 20161
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 764
+ num_resource: 4
+ type: 20161
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 878
+ num_resource: 128
+ type: 20161
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1006
+ num_resource: 10
+ type: 20161
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 345
+ num_resource: 6
+ type: 20162
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 351
+ num_resource: 0
+ type: 20162
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 351
+ num_resource: 1
+ type: 20162
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 352
+ num_resource: 1
+ type: 20162
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 353
+ num_resource: 1
+ type: 20162
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 354
+ num_resource: 1
+ type: 20162
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 355
+ num_resource: 4
+ type: 20162
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 359
+ num_resource: 1
+ type: 20162
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 360
+ num_resource: 1
+ type: 20162
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 361
+ num_resource: 1
+ type: 20162
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 362
+ num_resource: 3
+ type: 20162
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 365
+ num_resource: 1
+ type: 20162
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 366
+ num_resource: 1
+ type: 20162
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 367
+ num_resource: 1
+ type: 20162
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 368
+ num_resource: 25
+ type: 20162
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 393
+ num_resource: 1
+ type: 20162
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 394
+ num_resource: 2
+ type: 20162
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 396
+ num_resource: 2
+ type: 20162
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 398
+ num_resource: 2
+ type: 20162
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 400
+ num_resource: 2
+ type: 20162
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 402
+ num_resource: 12
+ type: 20162
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 414
+ num_resource: 1
+ type: 20162
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 415
+ num_resource: 2
+ type: 20162
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 417
+ num_resource: 2
+ type: 20162
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 419
+ num_resource: 2
+ type: 20162
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 421
+ num_resource: 2
+ type: 20162
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 6
+ type: 20163
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 0
+ type: 20163
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 20163
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20163
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20163
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 20163
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 4
+ type: 20163
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 1
+ type: 20163
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 20163
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 20163
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 3
+ type: 20163
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 1
+ type: 20163
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 1
+ type: 20163
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 1
+ type: 20163
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 25
+ type: 20163
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 1
+ type: 20163
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 2
+ type: 20163
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 55
+ num_resource: 2
+ type: 20163
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 2
+ type: 20163
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 59
+ num_resource: 2
+ type: 20163
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 61
+ num_resource: 12
+ type: 20163
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 4
+ type: 20163
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 77
+ num_resource: 2
+ type: 20163
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 79
+ num_resource: 2
+ type: 20163
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 81
+ num_resource: 2
+ type: 20163
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 2
+ type: 20163
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 85
+ num_resource: 8
+ type: 20164
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 93
+ num_resource: 8
+ type: 20164
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 101
+ num_resource: 6
+ type: 20164
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 107
+ num_resource: 4
+ type: 20164
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 111
+ num_resource: 2
+ type: 20164
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 113
+ num_resource: 2
+ type: 20164
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 0
+ type: 20164
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 2
+ type: 20164
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 117
+ num_resource: 96
+ type: 20164
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 213
+ num_resource: 96
+ type: 20164
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 309
+ num_resource: 32
+ type: 20164
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 343
+ num_resource: 1
+ type: 20165
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 344
+ num_resource: 1
+ type: 20165
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 341
+ num_resource: 1
+ type: 20166
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 342
+ num_resource: 1
+ type: 20166
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 20167
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 1
+ type: 20167
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20168
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1
+ num_resource: 1
+ type: 20168
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 5
+ type: 20170
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 20170
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 3
+ type: 20171
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 2
+ type: 20171
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 3
+ type: 20171
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 3
+ type: 20171
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20171
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20171
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 6
+ type: 20171
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 3
+ type: 20171
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 3
+ type: 20171
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 3
+ type: 20171
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 20171
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 1
+ type: 20171
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 1
+ type: 20171
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 20171
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 82
+ num_resource: 16
+ type: 20416
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 98
+ num_resource: 16
+ type: 20416
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 114
+ num_resource: 110
+ type: 20416
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20417
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 49152
+ num_resource: 1024
+ type: 20418
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20419
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 6
+ type: 20426
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 0
+ type: 20426
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 20426
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20426
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20426
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 20426
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 4
+ type: 20426
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 1
+ type: 20426
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 20426
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 20426
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 3
+ type: 20426
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 1
+ type: 20426
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 1
+ type: 20426
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 1
+ type: 20426
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 25
+ type: 20426
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 1
+ type: 20426
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 2
+ type: 20426
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 55
+ num_resource: 2
+ type: 20426
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 2
+ type: 20426
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 59
+ num_resource: 2
+ type: 20426
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 61
+ num_resource: 12
+ type: 20426
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 1
+ type: 20426
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 74
+ num_resource: 2
+ type: 20426
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 76
+ num_resource: 2
+ type: 20426
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 2
+ type: 20426
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 20426
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 20427
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 1
+ type: 20427
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20428
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1
+ num_resource: 1
+ type: 20428
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 6
+ type: 20429
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 0
+ type: 20429
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 20429
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20429
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20429
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 20429
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 4
+ type: 20429
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 1
+ type: 20429
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 20429
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 20429
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 3
+ type: 20429
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 1
+ type: 20429
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 1
+ type: 20429
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 1
+ type: 20429
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 25
+ type: 20429
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 1
+ type: 20429
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 2
+ type: 20429
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 55
+ num_resource: 2
+ type: 20429
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 2
+ type: 20429
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 59
+ num_resource: 2
+ type: 20429
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 61
+ num_resource: 12
+ type: 20429
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 4
+ type: 20429
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 77
+ num_resource: 2
+ type: 20429
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 79
+ num_resource: 2
+ type: 20429
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 81
+ num_resource: 2
+ type: 20429
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 2
+ type: 20429
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 85
+ num_resource: 8
+ type: 20430
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 93
+ num_resource: 8
+ type: 20430
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 101
+ num_resource: 6
+ type: 20430
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 107
+ num_resource: 4
+ type: 20430
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 111
+ num_resource: 2
+ type: 20430
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 113
+ num_resource: 2
+ type: 20430
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 0
+ type: 20430
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 2
+ type: 20430
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 117
+ num_resource: 96
+ type: 20430
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 213
+ num_resource: 96
+ type: 20430
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 309
+ num_resource: 32
+ type: 20430
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 20431
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 1
+ type: 20431
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20432
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1
+ num_resource: 1
+ type: 20432
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 56
+ type: 20554
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 112
+ num_resource: 24
+ type: 20554
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 136
+ num_resource: 12
+ type: 20554
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 148
+ num_resource: 12
+ type: 20554
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 160
+ num_resource: 10
+ type: 20554
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 170
+ num_resource: 10
+ type: 20554
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 180
+ num_resource: 28
+ type: 20554
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 208
+ num_resource: 8
+ type: 20554
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 216
+ num_resource: 12
+ type: 20554
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 228
+ num_resource: 8
+ type: 20554
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 236
+ num_resource: 10
+ type: 20554
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 246
+ num_resource: 10
+ type: 20554
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 1024
+ type: 20557
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1080
+ num_resource: 512
+ type: 20557
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 1592
+ num_resource: 256
+ type: 20557
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 1848
+ num_resource: 256
+ type: 20557
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 2104
+ num_resource: 256
+ type: 20557
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 2360
+ num_resource: 256
+ type: 20557
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 2616
+ num_resource: 512
+ type: 20557
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 3128
+ num_resource: 256
+ type: 20557
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 3384
+ num_resource: 256
+ type: 20557
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 3640
+ num_resource: 256
+ type: 20557
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 3896
+ num_resource: 256
+ type: 20557
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 4152
+ num_resource: 256
+ type: 20557
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 4408
+ num_resource: 32
+ type: 20557
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 4440
+ num_resource: 32
+ type: 20557
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 4472
+ num_resource: 136
+ type: 20557
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 1536
+ num_resource: 16
+ type: 20559
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2048
+ num_resource: 16
+ type: 20560
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2560
+ num_resource: 16
+ type: 20561
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3072
+ num_resource: 32
+ type: 20562
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3584
+ num_resource: 32
+ type: 20563
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 32
+ type: 20564
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 12
+ type: 20736
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 20
+ type: 20736
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 1
+ num_resource: 2
+ type: 20928
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 4
+ type: 20928
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 4
+ type: 20928
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 4
+ type: 20928
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 15
+ num_resource: 4
+ type: 20928
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 4
+ type: 20928
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 16
+ type: 20928
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 39
+ num_resource: 4
+ type: 20928
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 4
+ type: 20928
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 47
+ num_resource: 4
+ type: 20928
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 51
+ num_resource: 3
+ type: 20928
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 2
+ type: 20928
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 4
+ type: 20928
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 60
+ num_resource: 4
+ type: 20928
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20992
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 96
+ num_resource: 20
+ type: 20993
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 116
+ num_resource: 8
+ type: 20993
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 124
+ num_resource: 8
+ type: 20993
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 132
+ num_resource: 8
+ type: 20993
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 140
+ num_resource: 8
+ type: 20993
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 148
+ num_resource: 8
+ type: 20993
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 156
+ num_resource: 16
+ type: 20993
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 172
+ num_resource: 8
+ type: 20993
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 180
+ num_resource: 8
+ type: 20993
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 188
+ num_resource: 8
+ type: 20993
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 196
+ num_resource: 8
+ type: 20993
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 204
+ num_resource: 4
+ type: 20993
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 208
+ num_resource: 32
+ type: 20993
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 240
+ num_resource: 12
+ type: 20993
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 50
+ num_resource: 3
+ type: 20994
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 0
+ type: 20994
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 1
+ type: 20994
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 1
+ type: 20994
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 55
+ num_resource: 1
+ type: 20994
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 1
+ type: 20994
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 1
+ type: 20994
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 58
+ num_resource: 1
+ type: 20994
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 59
+ num_resource: 1
+ type: 20994
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 60
+ num_resource: 1
+ type: 20994
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 61
+ num_resource: 1
+ type: 20994
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 62
+ num_resource: 1
+ type: 20994
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 63
+ num_resource: 2
+ type: 20994
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 65
+ num_resource: 0
+ type: 20994
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 65
+ num_resource: 8
+ type: 20994
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 4
+ type: 20994
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 77
+ num_resource: 1
+ type: 20994
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 1
+ type: 20994
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 79
+ num_resource: 1
+ type: 20994
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 1
+ type: 20994
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 81
+ num_resource: 2
+ type: 20994
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 1
+ type: 20994
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 84
+ num_resource: 1
+ type: 20994
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 85
+ num_resource: 1
+ type: 20994
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 86
+ num_resource: 1
+ type: 20994
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 87
+ num_resource: 1
+ type: 20994
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 88
+ num_resource: 3
+ type: 20994
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 91
+ num_resource: 2
+ type: 20994
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 3
+ type: 20995
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 0
+ type: 20995
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 20995
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 6
+ num_resource: 1
+ type: 20995
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 1
+ type: 20995
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 20995
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 20995
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 20995
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20995
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20995
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 20995
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 20995
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 15
+ num_resource: 2
+ type: 20995
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 0
+ type: 20995
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 8
+ type: 20995
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 4
+ type: 20995
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 1
+ type: 20995
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 1
+ type: 20995
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 20995
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 1
+ type: 20995
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 20995
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 20995
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 20995
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 20995
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 20995
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 20995
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 3
+ type: 20995
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 2
+ type: 20995
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 45
+ num_resource: 1
+ type: 20995
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 48
+ num_resource: 0
+ type: 20997
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 48
+ num_resource: 2
+ type: 20997
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 20999
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 20999
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 5
+ type: 21002
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 21002
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 3
+ type: 21003
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 2
+ type: 21003
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 2
+ type: 21003
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 2
+ type: 21003
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 9
+ num_resource: 2
+ type: 21003
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 2
+ type: 21003
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 21003
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 2
+ type: 21003
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 2
+ type: 21003
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 2
+ type: 21003
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 2
+ type: 21003
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 21003
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 3
+ type: 21003
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 3
+ type: 21003
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 48
+ num_resource: 8
+ type: 21056
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 4
+ type: 21056
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 60
+ num_resource: 8
+ type: 21056
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 68
+ num_resource: 4
+ type: 21056
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 72
+ num_resource: 4
+ type: 21056
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 76
+ num_resource: 4
+ type: 21056
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 21056
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 82
+ num_resource: 2
+ type: 21056
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 84
+ num_resource: 8
+ type: 21056
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 92
+ num_resource: 4
+ type: 21056
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 21057
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 56320
+ num_resource: 256
+ type: 21058
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 21059
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 3
+ type: 21066
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 0
+ type: 21066
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 21066
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 6
+ num_resource: 1
+ type: 21066
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 1
+ type: 21066
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 21066
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 21066
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 21066
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 21066
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 21066
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 21066
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 21066
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 15
+ num_resource: 2
+ type: 21066
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 0
+ type: 21066
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 8
+ type: 21066
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 4
+ type: 21066
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 1
+ type: 21066
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 1
+ type: 21066
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 21066
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 1
+ type: 21066
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 21066
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 21066
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 21066
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 21066
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 21066
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 21066
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 3
+ type: 21066
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 2
+ type: 21066
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 21067
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 21067
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 3
+ type: 21069
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 0
+ type: 21069
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 21069
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 6
+ num_resource: 1
+ type: 21069
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 1
+ type: 21069
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 21069
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 21069
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 21069
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 21069
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 21069
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 21069
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 21069
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 15
+ num_resource: 2
+ type: 21069
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 0
+ type: 21069
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 8
+ type: 21069
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 4
+ type: 21069
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 1
+ type: 21069
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 1
+ type: 21069
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 21069
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 1
+ type: 21069
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 21069
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 21069
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 21069
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 21069
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 21069
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 21069
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 3
+ type: 21069
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 2
+ type: 21069
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 45
+ num_resource: 1
+ type: 21069
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 21071
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 21071
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 32
+ type: 21194
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 64
+ type: 21194
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 4
+ type: 21194
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 122
+ num_resource: 134
+ type: 21194
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 16406
+ num_resource: 128
+ type: 21197
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16534
+ num_resource: 256
+ type: 21197
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 16790
+ num_resource: 64
+ type: 21197
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 16854
+ num_resource: 1066
+ type: 21197
+ host_id: 128
+ reserved: 0
diff --git a/board/toradex/aquila-am69/sec-cfg.yaml b/board/toradex/aquila-am69/sec-cfg.yaml
new file mode 100644
index 000000000000..e6cb99783cf5
--- /dev/null
+++ b/board/toradex/aquila-am69/sec-cfg.yaml
@@ -0,0 +1,380 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+# Security management configuration for AM69
+#
+
+---
+
+sec-cfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ processor_acl_list:
+ subhdr:
+ magic: 0xF1EA
+ size: 164
+ proc_acl_entries:
+ - # 1
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 2
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 3
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 4
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 5
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 6
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 7
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 8
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 9
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 10
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 11
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 12
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 13
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 14
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 15
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 16
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 17
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 18
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 19
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 20
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 21
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 22
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 23
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 24
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 25
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 26
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 27
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 28
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 29
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 30
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 31
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ - # 32
+ processor_id: 0
+ proc_access_master: 0
+ proc_access_secondary: [0, 0, 0]
+ host_hierarchy:
+ subhdr:
+ magic: 0x8D27
+ size: 68
+ host_hierarchy_entries:
+ - # 1
+ host_id: 0
+ supervisor_host_id: 0
+ - # 2
+ host_id: 0
+ supervisor_host_id: 0
+ - # 3
+ host_id: 0
+ supervisor_host_id: 0
+ - # 4
+ host_id: 0
+ supervisor_host_id: 0
+ - # 5
+ host_id: 0
+ supervisor_host_id: 0
+ - # 6
+ host_id: 0
+ supervisor_host_id: 0
+ - # 7
+ host_id: 0
+ supervisor_host_id: 0
+ - # 8
+ host_id: 0
+ supervisor_host_id: 0
+ - # 9
+ host_id: 0
+ supervisor_host_id: 0
+ - # 10
+ host_id: 0
+ supervisor_host_id: 0
+ - # 11
+ host_id: 0
+ supervisor_host_id: 0
+ - # 12
+ host_id: 0
+ supervisor_host_id: 0
+ - # 13
+ host_id: 0
+ supervisor_host_id: 0
+ - # 14
+ host_id: 0
+ supervisor_host_id: 0
+ - # 15
+ host_id: 0
+ supervisor_host_id: 0
+ - # 16
+ host_id: 0
+ supervisor_host_id: 0
+ - # 17
+ host_id: 0
+ supervisor_host_id: 0
+ - # 18
+ host_id: 0
+ supervisor_host_id: 0
+ - # 19
+ host_id: 0
+ supervisor_host_id: 0
+ - # 20
+ host_id: 0
+ supervisor_host_id: 0
+ - # 21
+ host_id: 0
+ supervisor_host_id: 0
+ - # 22
+ host_id: 0
+ supervisor_host_id: 0
+ - # 23
+ host_id: 0
+ supervisor_host_id: 0
+ - # 24
+ host_id: 0
+ supervisor_host_id: 0
+ - # 25
+ host_id: 0
+ supervisor_host_id: 0
+ - # 26
+ host_id: 0
+ supervisor_host_id: 0
+ - # 27
+ host_id: 0
+ supervisor_host_id: 0
+ - # 28
+ host_id: 0
+ supervisor_host_id: 0
+ - # 29
+ host_id: 0
+ supervisor_host_id: 0
+ - # 30
+ host_id: 0
+ supervisor_host_id: 0
+ - # 31
+ host_id: 0
+ supervisor_host_id: 0
+ - # 32
+ host_id: 0
+ supervisor_host_id: 0
+ otp_config:
+ subhdr:
+ magic: 0x4081
+ size: 69
+ otp_entry:
+ - # 1
+ host_id: 0
+ host_perms: 0
+ - # 2
+ host_id: 0
+ host_perms: 0
+ - # 3
+ host_id: 0
+ host_perms: 0
+ - # 4
+ host_id: 0
+ host_perms: 0
+ - # 5
+ host_id: 0
+ host_perms: 0
+ - # 6
+ host_id: 0
+ host_perms: 0
+ - # 7
+ host_id: 0
+ host_perms: 0
+ - # 8
+ host_id: 0
+ host_perms: 0
+ - # 9
+ host_id: 0
+ host_perms: 0
+ - # 10
+ host_id: 0
+ host_perms: 0
+ - # 11
+ host_id: 0
+ host_perms: 0
+ - # 12
+ host_id: 0
+ host_perms: 0
+ - # 13
+ host_id: 0
+ host_perms: 0
+ - # 14
+ host_id: 0
+ host_perms: 0
+ - # 15
+ host_id: 0
+ host_perms: 0
+ - # 16
+ host_id: 0
+ host_perms: 0
+ - # 17
+ host_id: 0
+ host_perms: 0
+ - # 18
+ host_id: 0
+ host_perms: 0
+ - # 19
+ host_id: 0
+ host_perms: 0
+ - # 20
+ host_id: 0
+ host_perms: 0
+ - # 21
+ host_id: 0
+ host_perms: 0
+ - # 22
+ host_id: 0
+ host_perms: 0
+ - # 23
+ host_id: 0
+ host_perms: 0
+ - # 24
+ host_id: 0
+ host_perms: 0
+ - # 25
+ host_id: 0
+ host_perms: 0
+ - # 26
+ host_id: 0
+ host_perms: 0
+ - # 27
+ host_id: 0
+ host_perms: 0
+ - # 28
+ host_id: 0
+ host_perms: 0
+ - # 29
+ host_id: 0
+ host_perms: 0
+ - # 30
+ host_id: 0
+ host_perms: 0
+ - # 31
+ host_id: 0
+ host_perms: 0
+ - # 32
+ host_id: 0
+ host_perms: 0
+ write_host_id: 0
+ dkek_config:
+ subhdr:
+ magic: 0x5170
+ size: 12
+ allowed_hosts: [128, 0, 0, 0]
+ allow_dkek_export_tisci: 0x5A
+ rsvd: [0, 0, 0]
+ sa2ul_cfg:
+ subhdr:
+ magic: 0x23BE
+ size: 0
+ auth_resource_owner: 0
+ enable_saul_psil_global_config_writes: 0
+ rsvd: [0, 0]
+ sec_dbg_config:
+ subhdr:
+ magic: 0x42AF
+ size: 16
+ allow_jtag_unlock: 0x0
+ allow_wildcard_unlock: 0x0
+ allowed_debug_level_rsvd: 0
+ rsvd: 0
+ min_cert_rev: 0x0
+ jtag_unlock_hosts: [0, 0, 0, 0]
+ sec_handover_cfg:
+ subhdr:
+ magic: 0x608F
+ size: 10
+ handover_msg_sender: 0
+ handover_to_host_id: 0
+ rsvd: [0, 0, 0, 0]
diff --git a/board/toradex/aquila-am69/tifs-rm-cfg.yaml b/board/toradex/aquila-am69/tifs-rm-cfg.yaml
new file mode 100644
index 000000000000..2889baacf82e
--- /dev/null
+++ b/board/toradex/aquila-am69/tifs-rm-cfg.yaml
@@ -0,0 +1,2655 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Resource management configuration for J784S4
+#
+
+---
+
+tifs-rm-cfg:
+ rm_boardcfg:
+ rev:
+ boardcfg_abi_maj: 0x0
+ boardcfg_abi_min: 0x1
+ host_cfg:
+ subhdr:
+ magic: 0x4C41
+ size: 356
+ host_cfg_entries:
+ - # 1
+ host_id: 3
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 2
+ host_id: 5
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 3
+ host_id: 12
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 4
+ host_id: 13
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 5
+ host_id: 21
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 6
+ host_id: 23
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 7
+ host_id: 25
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 8
+ host_id: 27
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 9
+ host_id: 35
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 10
+ host_id: 37
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 11
+ host_id: 40
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 12
+ host_id: 42
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 13
+ host_id: 45
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 14
+ host_id: 47
+ allowed_atype: 0x2A
+ allowed_qos: 0xAAAA
+ allowed_orderid: 0xAAAAAAAA
+ allowed_priority: 0xAAAA
+ allowed_sched_priority: 0xAA
+ - # 15
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 16
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 17
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 18
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 19
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 20
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 21
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 22
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 23
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 24
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 25
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 26
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 27
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 28
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 29
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 30
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 31
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ - # 32
+ host_id: 0
+ allowed_atype: 0
+ allowed_qos: 0
+ allowed_orderid: 0
+ allowed_priority: 0
+ allowed_sched_priority: 0
+ resasg:
+ subhdr:
+ magic: 0x7B25
+ size: 8
+ resasg_entries_size: 3208
+ reserved: 0
+ resasg_entries:
+ -
+ start_resource: 16
+ num_resource: 32
+ type: 17998
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 32
+ type: 17998
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 17999
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 17999
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 18017
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 32
+ type: 18017
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 18018
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 16
+ type: 18018
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 64
+ type: 19850
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 64
+ type: 19914
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 4
+ type: 19968
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 4
+ type: 19968
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 4
+ type: 19968
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 4
+ type: 19968
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 4
+ type: 19968
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 4
+ type: 19968
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 12
+ type: 19968
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 4
+ type: 19968
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 4
+ type: 19968
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 44
+ num_resource: 4
+ type: 19968
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 48
+ num_resource: 4
+ type: 19968
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 4
+ type: 19968
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 4
+ type: 19968
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 60
+ num_resource: 4
+ type: 19968
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20160
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 423
+ num_resource: 10
+ type: 20161
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 433
+ num_resource: 20
+ type: 20161
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 453
+ num_resource: 16
+ type: 20161
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 469
+ num_resource: 13
+ type: 20161
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 482
+ num_resource: 128
+ type: 20161
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 610
+ num_resource: 46
+ type: 20161
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 656
+ num_resource: 10
+ type: 20161
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 666
+ num_resource: 20
+ type: 20161
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 686
+ num_resource: 64
+ type: 20161
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 750
+ num_resource: 10
+ type: 20161
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 760
+ num_resource: 4
+ type: 20161
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 764
+ num_resource: 4
+ type: 20161
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 878
+ num_resource: 128
+ type: 20161
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1006
+ num_resource: 10
+ type: 20161
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 345
+ num_resource: 6
+ type: 20162
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 351
+ num_resource: 0
+ type: 20162
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 351
+ num_resource: 1
+ type: 20162
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 352
+ num_resource: 1
+ type: 20162
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 353
+ num_resource: 1
+ type: 20162
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 354
+ num_resource: 1
+ type: 20162
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 355
+ num_resource: 4
+ type: 20162
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 359
+ num_resource: 1
+ type: 20162
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 360
+ num_resource: 1
+ type: 20162
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 361
+ num_resource: 1
+ type: 20162
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 362
+ num_resource: 3
+ type: 20162
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 365
+ num_resource: 1
+ type: 20162
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 366
+ num_resource: 1
+ type: 20162
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 367
+ num_resource: 1
+ type: 20162
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 368
+ num_resource: 25
+ type: 20162
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 393
+ num_resource: 1
+ type: 20162
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 394
+ num_resource: 2
+ type: 20162
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 396
+ num_resource: 2
+ type: 20162
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 398
+ num_resource: 2
+ type: 20162
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 400
+ num_resource: 2
+ type: 20162
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 402
+ num_resource: 12
+ type: 20162
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 414
+ num_resource: 1
+ type: 20162
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 415
+ num_resource: 2
+ type: 20162
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 417
+ num_resource: 2
+ type: 20162
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 419
+ num_resource: 2
+ type: 20162
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 421
+ num_resource: 2
+ type: 20162
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 6
+ type: 20163
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 0
+ type: 20163
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 20163
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20163
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20163
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 20163
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 4
+ type: 20163
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 1
+ type: 20163
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 20163
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 20163
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 3
+ type: 20163
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 1
+ type: 20163
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 1
+ type: 20163
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 1
+ type: 20163
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 25
+ type: 20163
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 1
+ type: 20163
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 2
+ type: 20163
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 55
+ num_resource: 2
+ type: 20163
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 2
+ type: 20163
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 59
+ num_resource: 2
+ type: 20163
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 61
+ num_resource: 12
+ type: 20163
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 4
+ type: 20163
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 77
+ num_resource: 2
+ type: 20163
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 79
+ num_resource: 2
+ type: 20163
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 81
+ num_resource: 2
+ type: 20163
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 2
+ type: 20163
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 85
+ num_resource: 8
+ type: 20164
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 93
+ num_resource: 8
+ type: 20164
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 101
+ num_resource: 6
+ type: 20164
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 107
+ num_resource: 4
+ type: 20164
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 111
+ num_resource: 2
+ type: 20164
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 113
+ num_resource: 2
+ type: 20164
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 0
+ type: 20164
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 2
+ type: 20164
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 117
+ num_resource: 96
+ type: 20164
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 213
+ num_resource: 96
+ type: 20164
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 309
+ num_resource: 32
+ type: 20164
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 343
+ num_resource: 1
+ type: 20165
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 344
+ num_resource: 1
+ type: 20165
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 341
+ num_resource: 1
+ type: 20166
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 342
+ num_resource: 1
+ type: 20166
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 20167
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 1
+ type: 20167
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20168
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1
+ num_resource: 1
+ type: 20168
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 5
+ type: 20170
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 20170
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 3
+ type: 20171
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 2
+ type: 20171
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 3
+ type: 20171
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 3
+ type: 20171
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20171
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20171
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 6
+ type: 20171
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 3
+ type: 20171
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 3
+ type: 20171
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 3
+ type: 20171
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 28
+ num_resource: 1
+ type: 20171
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 1
+ type: 20171
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 1
+ type: 20171
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 20171
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 82
+ num_resource: 16
+ type: 20416
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 98
+ num_resource: 16
+ type: 20416
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 114
+ num_resource: 110
+ type: 20416
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20417
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 6
+ type: 20426
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 0
+ type: 20426
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 20426
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20426
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20426
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 20426
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 4
+ type: 20426
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 1
+ type: 20426
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 20426
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 20426
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 3
+ type: 20426
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 1
+ type: 20426
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 1
+ type: 20426
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 1
+ type: 20426
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 25
+ type: 20426
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 1
+ type: 20426
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 2
+ type: 20426
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 55
+ num_resource: 2
+ type: 20426
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 2
+ type: 20426
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 59
+ num_resource: 2
+ type: 20426
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 61
+ num_resource: 12
+ type: 20426
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 1
+ type: 20426
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 74
+ num_resource: 2
+ type: 20426
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 76
+ num_resource: 2
+ type: 20426
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 2
+ type: 20426
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 20426
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 20427
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 1
+ type: 20427
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20428
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1
+ num_resource: 1
+ type: 20428
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 4
+ num_resource: 6
+ type: 20429
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 0
+ type: 20429
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 20429
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20429
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20429
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 20429
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 4
+ type: 20429
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 1
+ type: 20429
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 1
+ type: 20429
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 1
+ type: 20429
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 21
+ num_resource: 3
+ type: 20429
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 1
+ type: 20429
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 1
+ type: 20429
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 1
+ type: 20429
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 27
+ num_resource: 25
+ type: 20429
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 52
+ num_resource: 1
+ type: 20429
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 2
+ type: 20429
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 55
+ num_resource: 2
+ type: 20429
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 2
+ type: 20429
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 59
+ num_resource: 2
+ type: 20429
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 61
+ num_resource: 12
+ type: 20429
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 4
+ type: 20429
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 77
+ num_resource: 2
+ type: 20429
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 79
+ num_resource: 2
+ type: 20429
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 81
+ num_resource: 2
+ type: 20429
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 2
+ type: 20429
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 85
+ num_resource: 8
+ type: 20430
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 93
+ num_resource: 8
+ type: 20430
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 101
+ num_resource: 6
+ type: 20430
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 107
+ num_resource: 4
+ type: 20430
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 111
+ num_resource: 2
+ type: 20430
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 113
+ num_resource: 2
+ type: 20430
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 0
+ type: 20430
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 115
+ num_resource: 2
+ type: 20430
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 117
+ num_resource: 96
+ type: 20430
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 213
+ num_resource: 96
+ type: 20430
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 309
+ num_resource: 32
+ type: 20430
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 1
+ type: 20431
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 1
+ type: 20431
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20432
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 1
+ num_resource: 1
+ type: 20432
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 56
+ type: 20554
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 112
+ num_resource: 24
+ type: 20554
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 136
+ num_resource: 12
+ type: 20554
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 148
+ num_resource: 12
+ type: 20554
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 160
+ num_resource: 10
+ type: 20554
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 170
+ num_resource: 10
+ type: 20554
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 180
+ num_resource: 28
+ type: 20554
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 208
+ num_resource: 8
+ type: 20554
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 216
+ num_resource: 12
+ type: 20554
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 228
+ num_resource: 8
+ type: 20554
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 236
+ num_resource: 10
+ type: 20554
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 246
+ num_resource: 10
+ type: 20554
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 1536
+ num_resource: 16
+ type: 20559
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2048
+ num_resource: 16
+ type: 20560
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2560
+ num_resource: 16
+ type: 20561
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3072
+ num_resource: 32
+ type: 20562
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 3584
+ num_resource: 32
+ type: 20563
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 4096
+ num_resource: 32
+ type: 20564
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 1
+ num_resource: 2
+ type: 20928
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 4
+ type: 20928
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 4
+ type: 20928
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 4
+ type: 20928
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 15
+ num_resource: 4
+ type: 20928
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 19
+ num_resource: 4
+ type: 20928
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 23
+ num_resource: 16
+ type: 20928
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 39
+ num_resource: 4
+ type: 20928
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 4
+ type: 20928
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 47
+ num_resource: 4
+ type: 20928
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 51
+ num_resource: 3
+ type: 20928
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 2
+ type: 20928
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 4
+ type: 20928
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 60
+ num_resource: 4
+ type: 20928
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 20992
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 96
+ num_resource: 20
+ type: 20993
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 116
+ num_resource: 8
+ type: 20993
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 124
+ num_resource: 8
+ type: 20993
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 132
+ num_resource: 8
+ type: 20993
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 140
+ num_resource: 8
+ type: 20993
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 148
+ num_resource: 8
+ type: 20993
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 156
+ num_resource: 16
+ type: 20993
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 172
+ num_resource: 8
+ type: 20993
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 180
+ num_resource: 8
+ type: 20993
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 188
+ num_resource: 8
+ type: 20993
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 196
+ num_resource: 8
+ type: 20993
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 204
+ num_resource: 4
+ type: 20993
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 208
+ num_resource: 32
+ type: 20993
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 240
+ num_resource: 12
+ type: 20993
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 50
+ num_resource: 3
+ type: 20994
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 0
+ type: 20994
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 53
+ num_resource: 1
+ type: 20994
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 1
+ type: 20994
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 55
+ num_resource: 1
+ type: 20994
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 1
+ type: 20994
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 57
+ num_resource: 1
+ type: 20994
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 58
+ num_resource: 1
+ type: 20994
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 59
+ num_resource: 1
+ type: 20994
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 60
+ num_resource: 1
+ type: 20994
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 61
+ num_resource: 1
+ type: 20994
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 62
+ num_resource: 1
+ type: 20994
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 63
+ num_resource: 2
+ type: 20994
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 65
+ num_resource: 0
+ type: 20994
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 65
+ num_resource: 8
+ type: 20994
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 73
+ num_resource: 4
+ type: 20994
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 77
+ num_resource: 1
+ type: 20994
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 78
+ num_resource: 1
+ type: 20994
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 79
+ num_resource: 1
+ type: 20994
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 1
+ type: 20994
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 81
+ num_resource: 2
+ type: 20994
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 83
+ num_resource: 1
+ type: 20994
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 84
+ num_resource: 1
+ type: 20994
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 85
+ num_resource: 1
+ type: 20994
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 86
+ num_resource: 1
+ type: 20994
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 87
+ num_resource: 1
+ type: 20994
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 88
+ num_resource: 3
+ type: 20994
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 91
+ num_resource: 2
+ type: 20994
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 3
+ type: 20995
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 0
+ type: 20995
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 20995
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 6
+ num_resource: 1
+ type: 20995
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 1
+ type: 20995
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 20995
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 20995
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 20995
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 20995
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 20995
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 20995
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 20995
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 15
+ num_resource: 2
+ type: 20995
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 0
+ type: 20995
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 8
+ type: 20995
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 4
+ type: 20995
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 1
+ type: 20995
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 1
+ type: 20995
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 20995
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 1
+ type: 20995
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 20995
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 20995
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 20995
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 20995
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 20995
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 20995
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 3
+ type: 20995
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 2
+ type: 20995
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 45
+ num_resource: 1
+ type: 20995
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 48
+ num_resource: 0
+ type: 20997
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 48
+ num_resource: 2
+ type: 20997
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 20999
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 20999
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 5
+ type: 21002
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 21002
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 3
+ type: 21003
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 3
+ num_resource: 2
+ type: 21003
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 2
+ type: 21003
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 2
+ type: 21003
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 9
+ num_resource: 2
+ type: 21003
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 2
+ type: 21003
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 3
+ type: 21003
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 16
+ num_resource: 2
+ type: 21003
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 18
+ num_resource: 2
+ type: 21003
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 20
+ num_resource: 2
+ type: 21003
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 2
+ type: 21003
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 24
+ num_resource: 2
+ type: 21003
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 26
+ num_resource: 3
+ type: 21003
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 3
+ type: 21003
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 48
+ num_resource: 8
+ type: 21056
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 56
+ num_resource: 4
+ type: 21056
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 60
+ num_resource: 8
+ type: 21056
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 68
+ num_resource: 4
+ type: 21056
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 72
+ num_resource: 4
+ type: 21056
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 76
+ num_resource: 4
+ type: 21056
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 80
+ num_resource: 2
+ type: 21056
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 82
+ num_resource: 2
+ type: 21056
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 84
+ num_resource: 8
+ type: 21056
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 92
+ num_resource: 4
+ type: 21056
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 1
+ type: 21057
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 3
+ type: 21066
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 0
+ type: 21066
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 21066
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 6
+ num_resource: 1
+ type: 21066
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 1
+ type: 21066
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 21066
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 21066
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 21066
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 21066
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 21066
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 21066
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 21066
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 15
+ num_resource: 2
+ type: 21066
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 0
+ type: 21066
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 8
+ type: 21066
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 4
+ type: 21066
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 1
+ type: 21066
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 1
+ type: 21066
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 21066
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 1
+ type: 21066
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 21066
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 21066
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 21066
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 21066
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 21066
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 21066
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 3
+ type: 21066
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 2
+ type: 21066
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 21067
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 21067
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 2
+ num_resource: 3
+ type: 21069
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 0
+ type: 21069
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 5
+ num_resource: 1
+ type: 21069
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 6
+ num_resource: 1
+ type: 21069
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 7
+ num_resource: 1
+ type: 21069
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 8
+ num_resource: 1
+ type: 21069
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 9
+ num_resource: 1
+ type: 21069
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 10
+ num_resource: 1
+ type: 21069
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 11
+ num_resource: 1
+ type: 21069
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 12
+ num_resource: 1
+ type: 21069
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 13
+ num_resource: 1
+ type: 21069
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 14
+ num_resource: 1
+ type: 21069
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 15
+ num_resource: 2
+ type: 21069
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 0
+ type: 21069
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 17
+ num_resource: 8
+ type: 21069
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 25
+ num_resource: 4
+ type: 21069
+ host_id: 13
+ reserved: 0
+ -
+ start_resource: 29
+ num_resource: 1
+ type: 21069
+ host_id: 21
+ reserved: 0
+ -
+ start_resource: 30
+ num_resource: 1
+ type: 21069
+ host_id: 23
+ reserved: 0
+ -
+ start_resource: 31
+ num_resource: 1
+ type: 21069
+ host_id: 25
+ reserved: 0
+ -
+ start_resource: 32
+ num_resource: 1
+ type: 21069
+ host_id: 27
+ reserved: 0
+ -
+ start_resource: 33
+ num_resource: 2
+ type: 21069
+ host_id: 35
+ reserved: 0
+ -
+ start_resource: 35
+ num_resource: 1
+ type: 21069
+ host_id: 37
+ reserved: 0
+ -
+ start_resource: 36
+ num_resource: 1
+ type: 21069
+ host_id: 40
+ reserved: 0
+ -
+ start_resource: 37
+ num_resource: 1
+ type: 21069
+ host_id: 42
+ reserved: 0
+ -
+ start_resource: 38
+ num_resource: 1
+ type: 21069
+ host_id: 45
+ reserved: 0
+ -
+ start_resource: 39
+ num_resource: 1
+ type: 21069
+ host_id: 47
+ reserved: 0
+ -
+ start_resource: 40
+ num_resource: 3
+ type: 21069
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 43
+ num_resource: 2
+ type: 21069
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 45
+ num_resource: 1
+ type: 21069
+ host_id: 128
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 0
+ type: 21071
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 0
+ num_resource: 2
+ type: 21071
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 22
+ num_resource: 32
+ type: 21194
+ host_id: 12
+ reserved: 0
+ -
+ start_resource: 54
+ num_resource: 64
+ type: 21194
+ host_id: 3
+ reserved: 0
+ -
+ start_resource: 118
+ num_resource: 4
+ type: 21194
+ host_id: 5
+ reserved: 0
+ -
+ start_resource: 122
+ num_resource: 134
+ type: 21194
+ host_id: 128
+ reserved: 0
diff --git a/configs/aquila-am69_a72_defconfig b/configs/aquila-am69_a72_defconfig
new file mode 100644
index 000000000000..fb694c6bd64e
--- /dev/null
+++ b/configs/aquila-am69_a72_defconfig
@@ -0,0 +1,179 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_AQUILA_AM69_A72=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am69-aquila-dev"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a00000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_LOAD_ADDR=0x88200000
+CONFIG_SPL_SIZE_LIMIT=0x80000
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_BOOTCOMMAND="bootflow scan -b"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am69-aquila-${fdt_board}.dtb"
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_BOARD_INIT is not set
+CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SYS_PROMPT="Aquila AM69 # "
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUX_MMIO=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PHY_CADENCE_TORRENT=y
+CONFIG_PHY_J721E_WIZ=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_USB_GADGET_OS_DESCRIPTORS=y
+CONFIG_SPL_DFU=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_HEXDUMP=y
+# CONFIG_OPTEE_LIB is not set
diff --git a/configs/aquila-am69_r5_defconfig b/configs/aquila-am69_r5_defconfig
new file mode 100644
index 000000000000..9360704e369e
--- /dev/null
+++ b/configs/aquila-am69_r5_defconfig
@@ -0,0 +1,134 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
+CONFIG_TARGET_AQUILA_AM69_R5=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am69-r5-aquila-dev"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x41c76000
+CONFIG_SPL_BSS_MAX_SIZE=0xa000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SPL_SIZE_LIMIT=0x100000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_LOG=y
+CONFIG_LOG_MAX_LEVEL=4
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_BOARD_INIT is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_ESM_K3=y
+CONFIG_K3_AVS0=y
+CONFIG_ESM_PMIC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65941=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_TPS6287X=y
+CONFIG_DM_REGULATOR_TPS65941=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/doc/board/toradex/aquila-am69.rst b/doc/board/toradex/aquila-am69.rst
new file mode 100644
index 000000000000..6a346e9f4d0f
--- /dev/null
+++ b/doc/board/toradex/aquila-am69.rst
@@ -0,0 +1,221 @@
+.. SPDX-License-Identifier: GPL-2.0-only
+.. sectionauthor:: Emanuele Ghidoli <emanuele.ghidoli at toradex.com>
+
+Aquila AM69 Module
+==================
+
+Quick Start
+-----------
+
+- Setup environment variables
+- Get binary-only TI Linux firmware
+- Build the ARM trusted firmware binary
+- Build the OPTEE binary
+- Build U-Boot for the R5
+- Build U-Boot for the A72
+- Flash to eMMC
+- Boot
+
+Setup environment
+-----------------
+
+Suggested current toolchains are ARM 11.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads):
+
+- https://developer.arm.com/-/media/Files/downloads/gnu/11.3.rel1/binrel/arm-gnu-toolchain-11.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz
+- https://developer.arm.com/-/media/Files/downloads/gnu/11.3.rel1/binrel/arm-gnu-toolchain-11.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz
+
+.. code-block:: console
+
+ $ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf-
+ $ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu-
+
+Get the TI Linux Firmware
+-------------------------
+
+.. code-block:: console
+
+ $ echo "Downloading TI Linux Firmware..."
+ $ git clone -b ti-linux-firmware https://git.ti.com/git/processor-firmware/ti-linux-firmware.git
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: console
+
+ $ echo "Downloading and building TF-A..."
+ $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ $ cd trusted-firmware-a
+
+Then build ATF (TF-A):
+
+.. code-block:: console
+
+ $ export CROSS_COMPILE="$CROSS_COMPILE_64"
+ $ make PLAT=k3 TARGET_BOARD=j784s4 SPD=opteed K3_USART=0x8
+
+Get and Build OPTEE
+-------------------
+
+.. code-block:: console
+
+ $ echo "Downloading and building OPTEE..."
+ $ git clone https://github.com/OP-TEE/optee_os.git
+ $ cd optee_os
+
+Then build OPTEE:
+
+.. code-block:: console
+
+ $ export CROSS_COMPILE="$CROSS_COMPILE_32"
+ $ export CROSS_COMPILE64="$CROSS_COMPILE_64"
+ $ export CFG_CONSOLE_UART=0x8
+ $ make PLATFORM=k3-j784s4 CFG_ARM64_core=y
+
+Build U-Boot for R5
+-------------------
+
+.. code-block:: console
+
+ $ export CROSS_COMPILE="$CROSS_COMPILE_32"
+ $ export BINMAN_INDIRS=<path/to/ti-linux-firmware>
+ $ make O=/tmp/aquila-r5 aquila-am69_r5_config
+ $ make O=/tmp/aquila-r5
+
+Build U-Boot for A72
+--------------------
+
+.. code-block:: console
+
+ $ export CROSS_COMPILE=$CROSS_COMPILE_64
+ $ export BL31=<path/to/atf>/build/k3/j784s4/release/bl31.bin
+ $ export TEE=<path/to/optee>/out/arm-plat-k3/core/tee-pager_v2.bin
+ $ export BINMAN_INDIRS="<path/to/ti-linux-firmware> /tmp/aquila-r5"
+ $ make O=/tmp/aquila-a72 aquila-am69_a72_config
+ $ make O=/tmp/aquila-a72
+
+Flash to eMMC
+-------------
+
+.. code-block:: console
+
+ => mmc dev 0 1
+ => fatload mmc 1 ${loadaddr} tiboot3.bin
+ => mmc write ${loadaddr} 0x0 0x400
+ => fatload mmc 1 ${loadaddr} tispl.bin
+ => mmc write ${loadaddr} 0x400 0x1000
+ => fatload mmc 1 ${loadaddr} u-boot.img
+ => mmc write ${loadaddr} 0x1400 0xc00
+
+As a convenience, instead of having to remember all those addresses and sizes,
+one may also use the update U-Boot wrappers:
+
+.. code-block:: console
+
+ => tftpboot ${loadaddr} tiboot3.bin
+ => run update_tiboot3
+
+ => tftpboot ${loadaddr} tispl.bin
+ => run update_tispl
+
+ => tftpboot ${loadaddr} u-boot.img
+ => run update_uboot
+
+Boot
+----
+
+Output:
+
+.. code-block:: console
+
+U-Boot SPL 2026.01-rc1-00200-g39abfe677ff5-dirty (Nov 03 2025 - 18:09:30 +0100)
+SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.8--v11.01.08 (Fancy Rat)')
+HW CFG: 0x00
+Initialized 4 DRAM controllers
+SPL initial stack usage: 13552 bytes
+Trying to boot from MMC1
+Authentication passed
+Authentication passed
+Authentication passed
+Loading Environment from nowhere... OK
+init_env from device 17 not supported!
+Authentication passed
+Authentication passed
+Starting ATF on ARM64 core...
+
+NOTICE: BL31: v2.13.0(release):v2.13.0-1063-g7a0a320df
+NOTICE: BL31: Built : 13:30:07, Oct 28 2025
+I/TC:
+I/TC: OP-TEE version: 4.8.0 (gcc version 11.3.1 20220712 (Arm GNU Toolchain 11.3.Rel1)) #1 Tue Oct 28 12:32:30 UTC 2025 aarch64
+I/TC: WARNING: This OP-TEE configuration might be insecure!
+I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
+I/TC: Primary CPU initializing
+I/TC: GIC redistributor base address not provided
+I/TC: Assuming default GIC group status and modifier
+I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.8--v11.01.08 (Fancy Rat)')
+I/TC: Activated SA2UL device
+I/TC: Enabled firewalls for SA2UL TRNG device
+I/TC: EIP76D TRNG initialized
+I/TC: SA2UL Drivers initialized
+I/TC: HUK Initialized
+I/TC: Disabling output console
+
+U-Boot SPL 2026.01-rc1-00200-g39abfe677ff5-dirty (Nov 03 2025 - 18:11:30 +0100)
+Unable to shutdown MCU R5 core 1, -22
+SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.8--v11.01.08 (Fancy Rat)')
+DM ABI: 3.0 (firmware ver 0x000b 'PSDK.11.01.00.04--v11.01.08a' patch_ver: 8)
+HW CFG: 0x00
+Trying to boot from MMC1
+Authentication passed
+Authentication passed
+
+
+U-Boot 2026.01-rc1-00200-g39abfe677ff5-dirty (Nov 03 2025 - 18:11:30 +0100)
+
+SoC: J784S4 SR1.0 HS-FS
+DRAM: 2 GiB (total 32 GiB)
+optee optee: OP-TEE: revision 4.8 (86660925433a8d4d)
+Core: 191 devices, 35 uclasses, devicetree: separate
+MMC: mmc at 4f80000: 0, mmc at 4fb0000: 1
+Loading Environment from MMC... Reading from MMC(0)... OK
+MISSING TORADEX CARRIER CONFIG BLOCKS
+In: serial at 2880000
+Out: serial at 2880000
+Err: serial at 2880000
+Model: Toradex 0088 Aquila AM69 Octa 32GB WB IT V1.1A
+Serial#: 12593784
+Net: am65_cpsw_nuss ethernet at 46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1
+
+Warning: ethernet at 46000000port@1 MAC addresses don't match:
+Address in ROM is c0:d6:0a:de:0e:e6
+Address in environment is 00:14:2d:c0:2a:78
+eth0: ethernet at 46000000port@1 [PRIME]
+Hit any key to stop autoboot: 0
+MMC: no card present
+Cannot persist EFI variables without system partition
+** Booting bootflow '<NULL>' with efi_mgr
+Loading Boot0000 'mmc 0' failed
+EFI boot manager: Cannot load any image
+Boot failed (err=-14)
+MMC: no card present
+MMC: no card present
+MMC: no card present
+MMC: no card present
+** Booting bootflow 'mmc at 4f80000.bootdev.part_1' with script
+Loading DeviceTree: k3-am69-aquila-dev.dtb
+142461 bytes read in 2 ms (67.9 MiB/s)
+87 bytes read in 1 ms (85 KiB/s)
+Working FDT set to 90200000
+Applying Overlay: aquila-am69_spi1_spidev_overlay.dtbo
+560 bytes read in 1 ms (546.9 KiB/s)
+Applying Overlay: aquila-am69_spi2_spidev_overlay.dtbo
+560 bytes read in 1 ms (546.9 KiB/s)
+7937825 bytes read in 28 ms (270.4 MiB/s)
+Bootargs: root=PARTUUID=1d80c51f-02 ro rootwait console=tty1 console=ttyS2,115200
+ Uncompressing Kernel Image to 0
+## Flattened Device Tree blob at 90200000
+ Booting using the fdt blob at 0x90200000
+Working FDT set to 90200000
+ Loading Device Tree to 00000000fce5c000, end 00000000fcea1fff ... OK
+Working FDT set to fce5c000
+
+Starting kernel ...
diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst
index b6d49cc187e2..27f059542e6a 100644
--- a/doc/board/toradex/index.rst
+++ b/doc/board/toradex/index.rst
@@ -7,6 +7,7 @@ Toradex
:maxdepth: 2
apalis-imx8
+ aquila-am69
colibri_imx7
colibri-imx8x
smarc-imx8mp
diff --git a/include/configs/aquila-am69.h b/include/configs/aquila-am69.h
new file mode 100644
index 000000000000..36553d4295b7
--- /dev/null
+++ b/include/configs/aquila-am69.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Configuration header file for Aquila AM69 SoM
+ *
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#ifndef __CONFIG_AQUILA_AM69_H
+#define __CONFIG_AQUILA_AM69_H
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE1 0x880000000
+
+#endif /* __CONFIG_AQUILA_AM69_H */
--
2.47.3
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