[PATCH 0/4] Add PCIe Endpoint controller support for TI J784S4 SoC

[Tom Rini]

On Thu, 23 Oct 2025 17:16:00 +0530, Hrushikesh Salunke wrote:

> This series enables PCIe Endpoint mode on TI's J784S4 SoC. The J784S4
> SoC features two Cadence PCIe controller instances (PCIe0 and PCIe1)
> that can operate in endpoint mode. This series adds support for
> configuring these controllers with up to 4 lanes.
> 
> Key changes include:
> - Adding a stabilization delay after power domain reset to prevent
>   timing-related initialization issues
> - SERDES mux configuration support for proper lane routing, which is
>   essential for SoCs where SERDES lanes are shared between multiple
>   controllers (PCIe, USB, etc.) with different configurations across
>   boot phases
> - J784S4 SoC endpoint configuration with 4-lane support
> - Disabling unconfigured endpoint functions to prevent enumeration
>   issues on the Root Complex side
> 
> [...]

Applied to u-boot/master, thanks!

[1/4] pci_endpoint: pci_cdns_ti_ep: Add delay after power domain reset
      commit: 352214e8b2fadae4af7b7d9c849af24a7350ab2b
[2/4] pci_endpoint: pci_cdns_ti_ep: Add SERDES mux configuration support
      commit: f0c7d4b4c637a3ae74f71d4a4b565e8ba999d744
[3/4] pci_endpoint: pci_cdns_ti_ep: Enable PCIe Endpoint mode in J784S4 SoC
      commit: 8692f48baad3b94357dc6fd114ebed8c633637a6
[4/4] configs: j784s4_evm_a72_defconfig: Enable configs for PCI Endpoint mode
      commit: 6176174ab24443d271bb507f001551f86bf53cca
-- 
Tom