[PATCH 3/5] phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage

[Tom Rini]

On Mon, Nov 10, 2025 at 03:11:42PM +0530, Hrushikesh Salunke wrote:

> Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES
> wrapper driver in SPL stage. This is required for PCIe boot support
> where SERDES configuration must be done early in the boot sequence
> before loading bootloader image over PCIe.
> 
> Signed-off-by: Hrushikesh Salunke <h-salunke at ti.com>
> ---
>  drivers/phy/ti/Kconfig | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig
> index 111085f235d..bc52a4992fb 100644
> --- a/drivers/phy/ti/Kconfig
> +++ b/drivers/phy/ti/Kconfig
> @@ -7,3 +7,13 @@ config PHY_J721E_WIZ
>  	  signals to the SERDES (Sierra/Torrent). This driver configures
>  	  three clock selects (pll0, pll1, dig) and resets for each of the
>  	  lanes.
> +
> +config SPL_PHY_J721E_WIZ
> +	tristate "TI J721E WIZ (SERDES Wrapper) support"

Same comment as the last patch.

-- 
Tom
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