[PATCH v2 1/2] mtd: rawnand: atmel: set pmecc data setup time

[Eugen Hristev]

On 11/11/25 11:47, Alexander Dahl wrote:
> Hei hei,
> 
> Am Fri, Nov 07, 2025 at 04:02:23PM +0100 schrieb Zixun LI:
>> Setup the pmecc data setup time as 3 clock cycles for 133MHz as
>> recommended by the datasheet.
>>
>> Backported from Linux: f55f552a7c7e0a1 ("mtd: rawnand: atmel: set pmecc
>> data setup time")
>>
>> Fixes: a490e1b7c017c ("nand: atmel: Add pmecc driver")
>>
>> Signed-off-by: Zixun LI <admin at hifiphile.com>
>> ---
>>  drivers/mtd/nand/raw/atmel/pmecc.c | 6 ++++++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c
>> index e500a0fe3f8671ff08195c94c3383696a7731eb3..7c4e9bd5f9967b119239adf2b39e683ea62b71fd 100644
>> --- a/drivers/mtd/nand/raw/atmel/pmecc.c
>> +++ b/drivers/mtd/nand/raw/atmel/pmecc.c
>> @@ -142,6 +142,7 @@ struct atmel_pmecc_caps {
>>  	int nstrengths;
>>  	int el_offset;
>>  	bool correct_erased_chunks;
>> +	bool clk_ctrl;
>>  };
>>  
>>  struct atmel_pmecc_user_conf_cache {
>> @@ -840,6 +841,10 @@ atmel_pmecc_create(struct udevice *dev,
>>  
>>  	pmecc->regs.timing = 0;
>>  
>> +	/* pmecc data setup time */
>> +	if (caps->clk_ctrl)
>> +		writel(PMECC_CLK_133MHZ, pmecc->regs.base + ATMEL_PMECC_CLK);
>> +
>>  	/* Disable all interrupts before registering the PMECC handler. */
>>  	writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR);
>>  	atmel_pmecc_reset(pmecc);
>> @@ -884,6 +889,7 @@ static struct atmel_pmecc_caps at91sam9g45_caps = {
>>  	.strengths = atmel_pmecc_strengths,
>>  	.nstrengths = 5,
>>  	.el_offset = 0x8c,
>> +	.clk_ctrl = true,
>>  };
>>  
>>  static struct atmel_pmecc_caps sama5d4_caps = {
> 
> Tested this with sam9x60 d5m SiP and Spansion® SLC NAND Flash
> S34ML02G1 on a custom board:
> 
> Tested-by: Alexander Dahl <ada at thorsis.com>

Reviewed-by: Eugen Hristev <eugen.hristev at linaro.org>

> 
> Greets
> Alex
>