[PATCH v2 0/5] arm: k3: j784s4: Add PCIe boot support

[Hrushikesh Salunke]

On 12/11/25 11:08, Kumar, Udit wrote:
> 
> On 11/11/2025 11:46 AM, Hrushikesh Salunke wrote:
>> This series adds PCIe endpoint boot support for the TI J784S4 SoC.
>>
>> PCIe boot allows the device to boot as a PCIe endpoint, where the
>> bootloader images are loaded by a PCIe host through Device Firmware
>> Upgrade (DFU) over PCIe.
>>
>> The J784S4 SoC uses PCIe1 instance with SERDES0 for endpoint boot.
>> To enable this functionality, the SERDES and PCIe peripherals must be
>> configured early in the R5 SPL stage before the bootloader images can
>> be transferred from the host.
>>
>> This series:
>> 1. Adds the required clock and device data for SERDES0 and PCIe1
>> 2. Enables Cadence Torrent PHY driver at SPL stage
>> 3. Enables J721E WIZ SERDES wrapper driver at SPL stage
>> 4. Enables PCIe boot configs for R5 and A72 stage
> 
> I assume you might have changed device tree to PCIEe EP,
> 
> I suggest , adding this in J784s4 board doc. (If any changes are done to 
> test this feature and not part of this series)
> 
> 

Yes it needs to be changed to PCIe EP. I am planning on
adding all the PCIe boot details to board doc.

Regards,
Hrushikesh.


>>
>> This feature has been tested on J784S4 EVM. Following are the logs
>> corresponding to this feature.
>>
>> https://gist.github.com/hrushikesh221/cf48b512eb4cd90c1612ad2e531b8ffe
>>
>> Program used to copy bootloaders from PCIe Root-Complex to Endpoint:
>>
>> https://gist.github.com/hrushikesh221/94e6042dbd717c74b74a5c9fc8ec5b6c
>>
>> This series is based on commit :
>> 6b27b688694 Merge branch 'master' of https://source.denx.de/u-boot/ 
>> custodians/u-boot-sh
>>
>> Changes in v2:
>> - Fixed SPDX license identifier to use "GPL-2.0-or-later" instead of 
>> "GPL-2.0+"
>>    in clk-data.c and dev-data.c
>> - Changed SPL_PHY_CADENCE_TORRENT config type from "tristate" to "bool"
>> - Changed SPL_PHY_J721E_WIZ config type from "tristate" to "bool"
>>
>> Hrushikesh Salunke (5):
>>    arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe boot
>>    phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage
>>    phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage
>>    configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot
>>    configs: j784s4_evm_a72_defconfig: Enable configs for PCIe boot
>>
>>   arch/arm/mach-k3/r5/j784s4/clk-data.c | 209 +++++++++++++++++++++++++-
>>   arch/arm/mach-k3/r5/j784s4/dev-data.c |  43 +++---
>>   configs/j784s4_evm_a72_defconfig      |   7 +
>>   configs/j784s4_evm_r5_defconfig       |  13 ++
>>   drivers/phy/cadence/Kconfig           |   7 +
>>   drivers/phy/ti/Kconfig                |  10 ++
>>   6 files changed, 262 insertions(+), 27 deletions(-)
>>