[PATCH v1] sync socfpga common u-boot dts

[Sune Brian]

> > > > Do TIENFONG still handles patches on SoCFPGA? Seems like there are
> > > > no action or response on all SoCFPGA related patches?
> > >
> > > Yes, he's Tien Fong is still active, it's just that most subsystems are
> > > fairly slow moving.
> >
> > For patches that really affect normal boot should push back
> > to mainstream. Those patches really fixes the boot and w/o it
> > system completely stall.
> > For those that are more less critical can be handle in slower pace.
>
> If there's not a PR with them by rc4 or so, please do call out
> individual patches that need to be picked up, that's typically how I
> handle critical patches that haven't been grabbed yet. Thanks!

There is one critical patch that breaks the boot completely.
"[v4] Altera SoCFpga Boot Stall Fix"
20251020133455.1870-1-briansune at gmail.com

The other patch that is less critical but SDRAM involves
communication will stall.
"FPGA2SDRAM setup fix"
20251020133554.1901-1-briansune at gmail.com

Other than that are all non-critical.
The original issue is Altera just consider the new
SoCFPGA series and accidentally remove the
if-else case for old GEN5.

Brian