[PATCH v4] Altera SoCFpga Boot Stall Fix

[Sune Brian]

>  U_BOOT_CMD(bridge, 3, 1, do_bridge,
>     "SoCFPGA HPS FPGA bridge control",
> -   "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n"
> -   "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n"
> +   "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges\n"
> +   "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges\n"
> +   "Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10\n"
> +   "For example:\n"
> +   "1) To enable and disable all bridges (command without mask):\n"
> +   " a) bridge enable\n"
> +   " b) bridge disable\n"
> +   "2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask):\n"
> +   " a) bridge enable 0x3\n"
> +   " b) bridge disable 0x3\n"
>     ""
>  );

With all do respect. If you have no clue what this is intended.
Read back old 2013- 2019 UBOOT style. These command
and operation is what backward bridge control via boot.scr
or boot env variable.

I am not here to argue, but the patch that touching this file
breaks all Cyclone V SoCFPGA and possible Arria V / 10
SD boot.

Meanwhile, if bridge control method is removed then all
H2F F2H control will be dead. So unless there are very
strong reason or better control method that can support
both old and new bridge control method otherwise no reason
to do so.

Brian