[PATCH 2/5] arm: include: imx7: rename PWM registers to match driver name

[Thomas Bonnefille]

The imx pwm driver uses PWMn_BASE_ADDR as the address of the different
PWM controllers, as the current names used for the PWM addresses aren't
used anywhere, this commit renames the macro to match what has been done
for i.MX6 and i.MX5.

It also adds some basic bit descriptions, macros and structure to give
to the pwm-imx driver based on what has already been done for the other
i.MX models.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille at bootlin.com>
---
 arch/arm/include/asm/arch-mx7/imx-regs.h | 25 +++++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 849c5482241..d1cc176d6dc 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -127,10 +127,10 @@
 #define ECSPI4_BASE_ADDR                (AIPS2_OFF_BASE_ADDR+0x30000)
 #define FTM1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x40000)
 #define FTM2_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x50000)
-#define PWM1_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x60000)
-#define PWM2_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x70000)
-#define PWM3_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x80000)
-#define PWM4_IPS_BASE_ADDR              (AIPS2_OFF_BASE_ADDR+0x90000)
+#define PWM1_BASE_ADDR                  (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define PWM2_BASE_ADDR                  (AIPS2_OFF_BASE_ADDR + 0x70000)
+#define PWM3_BASE_ADDR                  (AIPS2_OFF_BASE_ADDR + 0x80000)
+#define PWM4_BASE_ADDR                  (AIPS2_OFF_BASE_ADDR + 0x90000)
 #define SYSCNT_RD_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR+0xA0000)
 #define SYSCNT_CMP_IPS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR+0xB0000)
 #define SYSCNT_CTRL_IPS_BASE_ADDR       (AIPS2_OFF_BASE_ADDR+0xC0000)
@@ -970,6 +970,23 @@ struct aipstz_regs {
 	u32	opacr4;
 };
 
+#define PWMCR_PRESCALER(x)	((((x) - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN       BIT(24)
+#define PWMCR_WAITEN       BIT(23)
+#define PWMCR_DBGEN        BIT(22)
+#define PWMCR_CLKSRC_IPG_HIGH  (BIT(17) | BIT(16))
+#define PWMCR_CLKSRC_IPG   BIT(16)
+#define PWMCR_EN           BIT(0)
+
+struct pwm_regs {
+	u32	cr;
+	u32	sr;
+	u32	ir;
+	u32	sar;
+	u32	pr;
+	u32	cnr;
+};
+
 struct wdog_regs {
 	u16	wcr;	/* Control */
 	u16	wsr;	/* Service */

-- 
2.52.0