[PATCH] common: spl: Enable Instruction cache after relocation in board_init_r

[Ernest Van Hoecke]

On Tue, Mar 25, 2025 at 11:04:20AM +0530, Prasanth Mantena wrote:
> On 09:13, Tom Rini wrote:
> > On Mon, Mar 17, 2025 at 12:15:07PM +0530, Prasanth Babu Mantena wrote:
> > 
> > > ICACHE is enabled in board_init_f which executes only before relocation.
> > > Instruction cache invalidation is needed after relocation as well in the
> > > common spl, which is taken care in the u-boot init_sequence, but missing
> > > for the spl. So, enable it at the start of board_init_r for spl, which
> > > invalidates icache needed after instruction relocation.
> > > 
> > > Fixes: 52a86e69e20 ("arm: k3: Enable instruction cache for main domain SPL")
> > > Signed-off-by: Prasanth Babu Mantena <p-mantena at ti.com>
> > > ---
> > >  arch/arm/mach-k3/common.c | 1 +
> > >  common/spl/spl.c          | 1 +
> > >  2 files changed, 2 insertions(+)
> > 
> > What's missing from spl_enable_cache() in K3 already? And looking more
> > at this, since Rockchip does this slightly differently I wonder if we
> > need to think harder about making some of these hook points generic.
> 
> spl_enable_cache is getting called in the board_init_f and the
> enable_cache here is getting called in the board_init_r, which is
> basically doing the cache invalidate after the relocation. If this is
> the case, I doubt, if we have to enable this directly in board_init_r
> only, instead doing it in board_init_f.

Hi all,

We have seen intermittent boot failures on the AM69, fixed by applying
this patch. How can we fix this up to get it upstream? Thanks for your
efforts here.

Kind regards,
Ernest