[PATCH v4] SDRAM Calibration Failed fix for GEN5 SoCFPGA

[Sune Brian]

> Thanks for sharing your findings. However, based on the behavior you
> described, I’m not fully convinced that enabling cyclic/watchdog is
> actually fixing the SDRAM calibration issue itself. From the SPL side,
> there is no clear timeout or calibration control path that would
> logically be corrected by turning on the cyclic framework, so the
> improvement may simply be due to timing shifts rather than a real fix.

BTW T.F. I want to point out a very important setup.
By default the Altera trunk had turned on

  │ │       [*] Enable U-Boot watchdog reset
                   │ │
  │ │       [*] Automatically start watchdog timer
                   │ │
  │ │       (10000) Watchdog timeout in msec
                   │ │
  │ │       [ ] Enable Watchdog Timer support for IMX and LSCH2 of NXP
                   │ │
  │ │       [ ] i.MX7ULP watchdog
                   │ │
  │ │       -*- Designware watchdog timer support
                   │ │
  │ │       [*] Enable driver model for watchdog timer drivers

So maybe you can also reverse investigate on your side via real board.
Removing all CYCLIC WDT drivers and all dst watchdog "okay" do
not introduce sdram calibration issue?

Lets cross check.

Thanks,
Brian