[PATCH] spi: cadence-qspi: Remove cdns,is-dma property handling
Michal Simek
michal.simek at amd.com
Wed Oct 1 08:21:34 CEST 2025
On 9/25/25 09:49, Michal Simek wrote:
> Remove cdns,is-dma DT property handling. Property is not the part of DT
> binding and it is also hardcoded to value 1 in all DTs that's why remove it
> because none is also testing value 0.
> If there is any use case when this configuration should be supported this
> patch can be reverted.
>
> Signed-off-by: Michal Simek <michal.simek at amd.com>
> ---
>
> arch/arm/dts/versal-mini-ospi.dtsi | 1 -
> arch/arm/dts/versal-net-mini-ospi.dtsi | 1 -
> drivers/spi/cadence_qspi.c | 8 +-------
> drivers/spi/cadence_qspi.h | 5 -----
> drivers/spi/cadence_qspi_apb.c | 22 ----------------------
> 5 files changed, 1 insertion(+), 36 deletions(-)
>
> diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
> index eec2a08e7c70..6991f6a51db0 100644
> --- a/arch/arm/dts/versal-mini-ospi.dtsi
> +++ b/arch/arm/dts/versal-mini-ospi.dtsi
> @@ -38,7 +38,6 @@
> num-cs = <1>;
> cdns,fifo-depth = <256>;
> cdns,fifo-width = <4>;
> - cdns,is-dma = <1>;
> cdns,trigger-address = <0xc0000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> diff --git a/arch/arm/dts/versal-net-mini-ospi.dtsi b/arch/arm/dts/versal-net-mini-ospi.dtsi
> index 1c94b352dc97..d2d5ec8e5cbf 100644
> --- a/arch/arm/dts/versal-net-mini-ospi.dtsi
> +++ b/arch/arm/dts/versal-net-mini-ospi.dtsi
> @@ -52,7 +52,6 @@
> num-cs = <1>;
> cdns,fifo-depth = <256>;
> cdns,fifo-width = <4>;
> - cdns,is-dma = <1>;
> cdns,is-stig-pgm = <1>;
> cdns,trigger-address = <0xc0000000>;
> #address-cells = <1>;
> diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
> index 599596f9f087..849bd930edf0 100644
> --- a/drivers/spi/cadence_qspi.c
> +++ b/drivers/spi/cadence_qspi.c
> @@ -210,7 +210,6 @@ static int cadence_spi_probe(struct udevice *bus)
>
> priv->regbase = plat->regbase;
> priv->ahbbase = plat->ahbbase;
> - priv->is_dma = plat->is_dma;
> priv->is_decoded_cs = plat->is_decoded_cs;
> priv->fifo_depth = plat->fifo_depth;
> priv->fifo_width = plat->fifo_width;
> @@ -348,10 +347,7 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
> case CQSPI_READ:
> err = cadence_qspi_apb_read_setup(priv, op);
> if (!err) {
> - if (priv->is_dma)
> - err = cadence_qspi_apb_dma_read(priv, op);
> - else
> - err = cadence_qspi_apb_read_execute(priv, op);
> + err = cadence_qspi_apb_dma_read(priv, op);
> }
> break;
> case CQSPI_WRITE:
> @@ -412,8 +408,6 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
> if (plat->ahbsize >= SZ_8M)
> priv->use_dac_mode = true;
>
> - plat->is_dma = dev_read_bool(bus, "cdns,is-dma");
> -
> /* All other parameters are embedded in the child node */
> subnode = cadence_qspi_get_subnode(bus);
> if (!ofnode_valid(subnode)) {
> diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
> index 879e7f8dbfb8..10c4ad14cc05 100644
> --- a/drivers/spi/cadence_qspi.h
> +++ b/drivers/spi/cadence_qspi.h
> @@ -223,8 +223,6 @@ struct cadence_spi_plat {
> u32 tchsh_ns;
> u32 tslch_ns;
> u32 quirks;
> -
> - bool is_dma;
> };
>
> struct cadence_spi_priv {
> @@ -261,7 +259,6 @@ struct cadence_spi_priv {
> bool ddr_init;
> bool is_decoded_cs;
> bool use_dac_mode;
> - bool is_dma;
>
> /* Transaction protocol parameters. */
> u8 inst_width;
> @@ -292,8 +289,6 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
>
> int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv,
> const struct spi_mem_op *op);
> -int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv,
> - const struct spi_mem_op *op);
> int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv,
> const struct spi_mem_op *op);
> int cadence_qspi_apb_write_execute(struct cadence_spi_priv *priv,
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index 4696c09f754b..243e29ae1c4f 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -764,28 +764,6 @@ failrd:
> return ret;
> }
>
> -int cadence_qspi_apb_read_execute(struct cadence_spi_priv *priv,
> - const struct spi_mem_op *op)
> -{
> - u64 from = op->addr.val;
> - void *buf = op->data.buf.in;
> - size_t len = op->data.nbytes;
> -
> - cadence_qspi_apb_enable_linear_mode(true);
> -
> - if (priv->use_dac_mode && (from + len < priv->ahbsize)) {
> - if (len < 256 ||
> - dma_memcpy(buf, priv->ahbbase + from, len) < 0) {
> - memcpy_fromio(buf, priv->ahbbase + from, len);
> - }
> - if (!cadence_qspi_wait_idle(priv->regbase))
> - return -EIO;
> - return 0;
> - }
> -
> - return cadence_qspi_apb_indirect_read_execute(priv, len, buf);
> -}
> -
> /* Opcode + Address (3/4 bytes) */
> int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv,
> const struct spi_mem_op *op)
Applied.
M
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