[PATCH v2] cmd: ti: Add DDRSS Inline ECC Error Injection command
    Kumar, Udit 
    u-kumar1 at ti.com
       
    Thu Oct  9 06:12:19 CEST 2025
    
    
  
On 10/8/2025 5:04 PM, Neha Malcom Francis wrote:
> From: Georgi Vlaev <g-vlaev at ti.com>
>
> Introduce a new version of the Keystone-II "ddr" command for testing the
> inline ECC support in the DDRSS bridge available on K3 devices. The ECC
> hardware support in K3's DDRSS and the test method differ substantially
> from what we support in the K2 variant of the command. This K3 DDRSS
> command currently supports only single controller testing.
>
> The ECC error injection procedure follows these steps:
> 1) Flush and disable the data cache.
> 2) Disable the protected ECC Rx range.
> 3) Flip a bit in the address.
> 4) Restore the range to original.
> 5) Read the modified value (corrected).
> 6) Re-enable the data cache.
Reviewed-by: Udit Kumar <u-kumar1 at ti.com>
> This will cause the 1-bit ECC error count to increase while the read
> will return the corrected value.
>
> The K3 version of the command extends the syntax for the "ecc_err"
> argument by also introducing an argument for range which specifies which
> range (0, 1, 2) the address is located in.
>
> Multi-bit ECC errors are uncorrectable and will lead to a synchronous
> abort.
>
> Signed-off-by: Georgi Vlaev <g-vlaev at ti.com>
> Signed-off-by: Santhosh Kumar K <s-k6 at ti.com>
> [n-francis at ti.com: Add J7 and multiple-region support, simplify logic]
> Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
> ---
> Changes since v1:
> https://lore.kernel.org/all/20251001082045.3547143-1-n-francis@ti.com/
> - instead of terming it as a test, push it as a tool to inject ECC to
>    possibly create an ECC error; as this depends on the user's
>    configuration
> - cmd/ti/ddrss.c --> cmd/ti/ddr4.c, and maintain same command name as K2
>    i.e. "ddr" (Udit)
> - add description for multi-bit error behavior (Udit)
> - s/x/range (Udit)
> - add check for range, ecc_err no check needed (can be any value,
>    synchronous abort / ECC error count / no ECC error are the three
>    possible behaviors depending on the user's configuration) (Udit)
>
> Test logs on J784S4-EVM (after modifying for single controller with ECC enabled)
> https://gist.github.com/nehamalcom/6ed3e835a55530d84a358bacf9095d2e
>
>   cmd/ti/Kconfig  |   8 ++
>   cmd/ti/Makefile |   1 +
>   cmd/ti/ddr4.c   | 251 ++++++++++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 260 insertions(+)
>   create mode 100644 cmd/ti/ddr4.c
>
> diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
> index 9442c9993c1..43fe9ef2f08 100644
> --- a/cmd/ti/Kconfig
> +++ b/cmd/ti/Kconfig
> @@ -8,6 +8,14 @@ config CMD_DDR3
>   	   supports memory verification, memory comapre and ecc
> [..]
    
    
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