[PATCH 00/24] Introduce Allwinner H6/H616 NAND controller support
Richard Genoud
richard.genoud at bootlin.com
Thu Oct 16 16:27:23 CEST 2025
Hi everyone,
This patch series introduce H6/H616 NAND controller support (but not yet
the DMA/MDMA part).
All the work was done on a H616 board with a Kioxia TC58NVG1S3HTA00 NAND
chip.
ECC is supported, as well as scrambling.
Support for booting from NAND is not part of this series, but it's almost
ready. (It needs quite some modifications in sunxi-spl-image-builder.c
and sunxi_toc0.c)
H6 SoC has not been tested, but it shares all registers with H616, plus
some registers dedicated to Embedded Crypto Engine that H616 lacks.
This IP has quite some register fields modified from the A10/A23, but in
the end, it works more or less the same.
Main differences with A10/A23 are:
- The need for 2 more clocks (for ECC and MBUS)
- The use of a new USER_DATA_LEN register
- More ECC strengths (44, 52, 68, 72, 76 and 80 bits / 1KB)
- MDMA based on chained buffers
- some registers layouts have changed (mainly due do the stronger ECC)
Patches 1 and 2 are small fixes
Patches 3-6 harmonize the registers definitions between U-Boot and SPL,
and ultimately merge those definitions in an include file, without
functional change.
Patches 7-19 are paving the way to the introduction of H6/H616 NAND
controller by adding per SoC capabilities for both drivers. They are
small for an easier review, without functional change.
Patches 20-21 are adding missing NAND related clocks definitions for
H6/H616
Patch 22 adds the support for H6/H616 NAND controller in U-Boot.
Patch 23 adds the support for H6/H616 NAND controller in SPL.
Patch 24 fixes warnings in sunxi_nand_spl.c
A similar series for this NAND controller support in Linux has been sent
and being reviewed.
Richard Genoud (24):
mtd: rawnand: sunxi: cosmetic: remove needless comment
mtd: rawnand: sunxi_spl: fix pointer from integer without a cast
mtd: rawnand: sunxi_spl: cosmetic: harmonize register defines with non
spl file
mtd: rawnand: sunxi_spl: cosmetic: use definitions from
linux/mtd/rawnand.h
mtd: rawnand: sunxi_spl: cosmetic: replace AHB_DIV_1 by
CCM_NAND_CTRL_M/N
mtd: rawnand: sunxi: cosmetic: merge register definitions for
sunxi_nand{,_spl}.c
mtd: rawnand: sunxi: cosmetic: add per SoC capabilities
mtd: rawnand: sunxi: cosmetic: move ECC_ERR_CNT register offset in SoC
caps
mtd: rawnand: sunxi: cosmetic: move USER_DATA register offset in SoC
caps
mtd: rawnand: sunxi: cosmetic: move ECC_PAT_FOUND register in SoC caps
mtd: rawnand: sunxi: cosmetic: add has_ecc_block_512 capability
mtd: rawnand: sunxi: cosmetic: move NFC_ECC_MODE offset in SoC caps
mtd: rawnand: sunxi: cosmetic: introduce reg_pat_id in sunxi_nfc_caps
mtd: rawnand: sunxi_spl: cosmetic: add per SoC capabilities
mtd: rawnand: sunxi: cosmetic: move NFC_RANDOM_EN register offset in
SoC caps
mtd: rawnand: sunxi: cosmetic: introduce reg_spare_area in
sunxi_nfc_caps
mtd: rawnand: sunxi_spl: use NFC_ECC_ERR_MSK and NFC_ECC_PAT_FOUND
mtd: rawnand: sunxi_spl: increase max_oobsize for 2KiB pages
mtd: rawnand: sunxi_spl: cosmetic: use NFC_ECC_MODE and
NFC_RANDOM_SEED macros
sunxi: clock: H6: add NAND controller clock registers
clk: sunxi: Add MBUS Master Clock Gating Register
mtd: rawnand: sunxi: add support for H6/H616 nand controller
mtd: rawnand: sunxi_spl: add support for H6/H616 nand controller
mtd: rawnand: sunxi_spl: Fix cast to pointer from integer warnings
.../include/asm/arch-sunxi/clock_sun50i_h6.h | 24 ++
board/sunxi/board.c | 17 +-
drivers/clk/sunxi/clk_h6.c | 2 +
drivers/clk/sunxi/clk_h616.c | 2 +
drivers/mtd/nand/raw/Kconfig | 3 +-
drivers/mtd/nand/raw/sunxi_nand.c | 301 ++++++++---------
drivers/mtd/nand/raw/sunxi_nand.h | 229 +++++++++++++
drivers/mtd/nand/raw/sunxi_nand_spl.c | 305 +++++++++++-------
8 files changed, 616 insertions(+), 267 deletions(-)
create mode 100644 drivers/mtd/nand/raw/sunxi_nand.h
base-commit: 2ba64e303b2706e5c42a6bf982326d632342ca66
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