[PATCH 1/1] riscv: consider CONFIG_RISCV_ISA_ZAAMO in SPL too

[Heinrich Schuchardt]

Commit a681cfecb434 ("riscv: Add a Zalrsc-only alternative for
synchronization in start.S") changed the hart synchronization in start.S.
It uses CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO) to determine which method to
use. If the macro evaluates to true the old behavior is maintained.

The macro evaluates to false for SPL builds which was unintended. Use
IS_ENABLED(CONFIG_RISCV_ISA_ZAAMO) instead.

This fixes a boot failure on StarFive JH7110 based boards.

Fixes: a681cfecb434 ("riscv: Add a Zalrsc-only alternative for synchronization in start.S")
Reported-by: Emil Renner Berthing <emil.renner.berthing at canonical.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt at canonical.com>
---
 arch/riscv/cpu/start.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 6324ff585d4..87b3ff0f93f 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -151,7 +151,7 @@ call_harts_early_init:
 	 */
 	la	t0, hart_lottery
 	li	t1, 1
-#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
+#if IS_ENABLED(CONFIG_RISCV_ISA_ZAAMO)
 	amoswap.w s2, t1, 0(t0)
 	bnez	s2, wait_for_gd_init
 #else
@@ -184,7 +184,7 @@ call_harts_early_init:
 #if !CONFIG_IS_ENABLED(XIP)
 #ifdef CONFIG_AVAILABLE_HARTS
 	la	t0, available_harts_lock
-#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
+#if IS_ENABLED(CONFIG_RISCV_ISA_ZAAMO)
 	amoswap.w.rl zero, zero, 0(t0)
 #else
 	fence	rw, w
@@ -203,7 +203,7 @@ wait_for_gd_init:
 	la	t0, available_harts_lock
 	li	t1, 1
 1:
-#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
+#if IS_ENABLED(CONFIG_RISCV_ISA_ZAAMO)
 	amoswap.w.aq t1, t1, 0(t0)
 #else
 	lr.w.aq	t1, 0(t0)
@@ -219,7 +219,7 @@ wait_for_gd_init:
 	or	t2, t2, t1
 	SREG	t2, GD_AVAILABLE_HARTS(gp)
 
-#if CONFIG_IS_ENABLED(RISCV_ISA_ZAAMO)
+#if IS_ENABLED(CONFIG_RISCV_ISA_ZAAMO)
 	amoswap.w.rl zero, zero, 0(t0)
 #else
 	fence	rw, w
-- 
2.51.0