[PATCH 05/24] mtd: rawnand: sunxi_spl: cosmetic: replace AHB_DIV_1 by CCM_NAND_CTRL_M/N

[Andre Przywara]

Hi,

On 16/10/2025 15:27, Richard Genoud wrote:
> CCM_NAND_CTRL_M/N is defined in clock headers, and it's more readable
> 
> Signed-off-by: Richard Genoud <richard.genoud at bootlin.com>
> ---
>   drivers/mtd/nand/raw/sunxi_nand_spl.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c
> index 306c1c0d0989..9f80a8010d7b 100644
> --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c
> +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c
> @@ -531,5 +531,6 @@ void nand_deselect(void)
>   #else
>   	clrbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
>   #endif
> -	clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
> +	clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE |
> +		     CCM_NAND_CTRL_N(0) | CCM_NAND_CTRL_M(1));

The change looks alright, but can you please use the opportunity to 
change the CCM access to the new scheme, away from using a struct, and 
towards using #define'd offsets? You have that conditionally in a later 
patch, so please rather move the legacy users over here.
No need to change *every* clock user for the older SoCs, or to remove 
the NAND clocks from the struct, just define the NAND related offsets in 
clock_sun4i.h and clock_sun6i.h, then use the H6/H616 way here for all.

Thanks!
Andre


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