[PATCH v3] armv8: implement workaround for broken CNTFRQ_EL0 value

Kaustabh Chakraborty kauschluss at disroot.org
Wed Oct 22 23:02:57 CEST 2025


In devices where the U-Boot is used as a secondary bootloader, we rely
on the device's primary bootloader to implement CNTFRQ_EL0. However,
this reliance may lead to a non-functional timer in broken firmware.

For instance, some versions of Samsung's S-Boot don't implement it. It's
also not possible to set it in the U-Boot, because it's booted in a lower
exception level. CNTFRQ_EL0 is reported to be 0.

Use gd->arch.timer_rate_hz to override the queried value if set. This
setting needs to be done in the board file, preferrably in timer_init().
This feature is present only when the CONFIG_ARMV8_CNTFRQ_BROKEN is
enabled.

Signed-off-by: Kaustabh Chakraborty <kauschluss at disroot.org>
---
Changes in v3:
- Added back config option for use with timer_rate_hz (Tom Rini)
- Link to v2: https://lore.kernel.org/r/20251017-armv8-broken-cntfrq-v2-1-1e043cbb657e@disroot.org

Changes in v2:
- Switched to using gd->arch.timer_rate_hz instead of a new config
  option (Ahmad Fatoum)
- Link to v1: https://lore.kernel.org/r/20251014-armv8-broken-cntfrq-v1-1-b63f9c69ffcb@disroot.org
---
 arch/arm/cpu/armv8/Kconfig         | 8 ++++++++
 arch/arm/cpu/armv8/generic_timer.c | 4 ++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 199335cd6040d30a355a7fd5448a449fa7f550fb..dfc4ce851c3a6e406423412b469164b2e6f7d5f8 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -4,6 +4,14 @@ config CMO_BY_VA_ONLY
 	bool "Force cache maintenance to be exclusively by VA"
 	depends on !SYS_DISABLE_DCACHE_OPS
 
+config ARMV8_CNTFRQ_BROKEN
+	bool "Fix broken ARMv8 generic timer"
+	depends on SYS_ARCH_TIMER
+	help
+	  Say Y here if U-Boot depends on a prior stage bootloader, which
+	  does not set the CNTFRQ_EL0 frequency, and its not possible to
+	  set it from U-Boot either.
+
 config ARMV8_SPL_EXCEPTION_VECTORS
 	bool "Install crash dump exception vectors"
 	depends on SPL
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index 1de7ec596fc7cbbc3e78a241f163bc0a4fcad6b6..744ab3b91e59703ad83e19459e60a42643eb2e61 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -19,6 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 unsigned long notrace get_tbclk(void)
 {
 	unsigned long cntfrq;
+
+	if (IS_ENABLED(CONFIG_ARMV8_CNTFRQ_BROKEN) && gd->arch.timer_rate_hz)
+		return gd->arch.timer_rate_hz;
+
 	asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq));
 	return cntfrq;
 }

---
base-commit: 582a04763aa80738c1c8ac60c47d1a5159a42833
change-id: 20251023-armv8-broken-cntfrq-537307c01d56

Best regards,
-- 
Kaustabh Chakraborty <kauschluss at disroot.org>



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