[PATCH 4/4] rockchip: spl_common: fix TIMER_FMODE constant

[Quentin Schulz]

From: Quentin Schulz <quentin.schulz at cherry.de>

The free running mode is 0 at bit offset 1. User mode is 1 at bit offset
1. Currently, free running mode is 1 at offset 0, which is already the
case thanks to TIME_EN.

So, this essentially does not change the actual value written to the
register as it is TIME_EN | TIMER_FMODE which currently is 0x1 | BIT(0)
= 0b1, and will become 0x1 | (0 << 1) = 0b1.

I checked PX30, RK3128, RK3188, RK3228, RK3288, RK3308, RK3328, RK3368
RK3506, RK3562 and RK3568 TRMs.

Signed-off-by: Quentin Schulz <quentin.schulz at cherry.de>
---
 arch/arm/mach-rockchip/spl_common.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/spl_common.c b/arch/arm/mach-rockchip/spl_common.c
index b29f33448ab..208cd22fcad 100644
--- a/arch/arm/mach-rockchip/spl_common.c
+++ b/arch/arm/mach-rockchip/spl_common.c
@@ -10,8 +10,8 @@
 #define TIMER_LOAD_COUNT_H	0x04
 #define TIMER_CONTROL_REG	0x10
 #define TIMER_EN	0x1
-#define	TIMER_FMODE	BIT(0)
-#define	TIMER_RMODE	BIT(1)
+#define	TIMER_FMODE	(0 << 1)
+#define	TIMER_RMODE	(1 << 1)
 
 __weak void rockchip_stimer_init(void)
 {

-- 
2.51.0