[PATCH 2/6] arm: dts: k3-j721s2: ddr: Update to v0.12.0 of DDR config tool

[Neha Malcom Francis]

Hi Udit

On 31/10/25 15:00, Kumar, Udit wrote:
> 
> On 10/31/2025 11:04 AM, Neha Malcom Francis wrote:
>> Update the DDR configuration for J721S2 according to the SysConfig
>> DDR Configuration tool v0.12.0. Log of changes between 0.9.1 to 0.12.0
>> is [0].
>>
>> [0]
>> https://dev.ti.com/tirex/content/TDA4x_DRA8x_AM67x-AM69x_DDR_Config_0.12.00.0000/docs/RevisionHistory.html
>>
>> Signed-off-by: Neha Malcom Francis <n-francis at ti.com>
>> ---
>>   arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 591 ++++++++++---------
>>   1 file changed, 307 insertions(+), 284 deletions(-)
>>
>> diff --git a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
>> b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
>> index c91576bf093..ecd42b1cf4d 100644
>> --- a/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
>> +++ b/arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
>> @@ -1,11 +1,23 @@
>>   // SPDX-License-Identifier: GPL-2.0+
>>   /*
>> - * Copyright (C) 2021 Texas Instruments Incorporated -
>> https://www.ti.com/
>> - * This file was generated by the Jacinto7_DDRSS_RegConfigTool,
>> Revision: 0.7.0
>> - * This file was generated on 10/14/2021
>> - */
>> + * Copyright (C) 2023 Texas Instruments Incorporated -
>> http://www.ti.com/
>> + * This file was generated with the following tool revisions:
>> + *     - SysConfig: Revision 1.25.0+4268
>> + *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.12.0
>> + * This file was generated on Thu Oct 30 2025 14:46:29 GMT+0530
>> (India Standard Time)
>> + *
>> + * Multi DDR Configuration (table based on register configuration
>> tool inputs):
>> + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
>> + * | DDRSS | PHYSICAL SIZE | SOFTWARE ACCESSIBLE SIZE |
>> + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
>> + * |   0   |      8 GB     |           8 GB           |
>> + * |~~~~~~~|~~~~~~~~~~~~~~~|~~~~~~~~~~~~~~~~~~~~~~~~~~|
>> + * |   1   |      8 GB     |           8 GB           |
>> + * |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|
>> +*/
>>   -#define DDRSS_PLL_FHS_CNT 10
>> +#define DDRSS_PLL_FHS_CNT 5
>> +#define DDRSS1_PLL_FHS_CNT 5
>>   #define DDRSS_PLL_FREQUENCY_0 27500000
>>   #define DDRSS_PLL_FREQUENCY_1 1066500000
>>   #define DDRSS_PLL_FREQUENCY_2 1066500000
>> @@ -16,6 +28,15 @@
>>   #define MULTI_DDR_CFG_HYBRID_SELECT 0
>>   #define MULTI_DDR_CFG_EMIFS_ACTIVE 3
>>   [..] #define DDRSS1_PHY_1420_DATA 0x3F0DFF11
>>   #define DDRSS1_PHY_1421_DATA 0x01FF00F0
>>   #define DDRSS1_PHY_1422_DATA 0x20040006
>> +
>> +
> 
> <blank line > also in patch 3/6

As mentioned in the cover letter, I did not want to hand edit this
configuration file so haven't made any modifications. I will work on
getting the tool to output data compliant to checkpatch rules.

Is that okay?

> 
> 

-- 
Thanking You
Neha Malcom Francis