[PATCH v1] arm64: imx8ulp: Split SRAM0 mapping to isolate the SCMI shared memory as non-cacheable

[Marek Vasut]

On 10/31/25 8:49 AM, alice.guo at oss.nxp.com wrote:
> From: Alice Guo <alice.guo at nxp.com>
> 
> This patch splits the 2MB SRAM0 mapping into three regions:
> - 0x22000000~0x2201f000: cacheable normal memory
> - 0x2201f000~0x22020000: non-cacheable device memory
> - 0x22020000~0x22200000: cacheable normal memory
> 
> The change ensures the SCMI shared memory is non-cacheable, which
> avoids cache-related issues after removing
> mmu_set_region_dcache_behaviour() from scmi_dt_get_smt_buffer().
> 
> Signed-off-by: Alice Guo <alice.guo at nxp.com>
> ---
>   arch/arm/mach-imx/imx8ulp/soc.c | 16 +++++++++++++++-
>   1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
> index 04c6f064130..6cb6b0e7429 100644
> --- a/arch/arm/mach-imx/imx8ulp/soc.c
> +++ b/arch/arm/mach-imx/imx8ulp/soc.c
> @@ -384,7 +384,21 @@ static struct mm_region imx8ulp_arm64_mem_map[] = {
>   		/* SRAM0 (align with 2M) */
>   		.virt = 0x22000000UL,
>   		.phys = 0x22000000UL,
> -		.size = 0x200000UL,
> +		.size = 0x1f000UL,
> +		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> +			 PTE_BLOCK_OUTER_SHARE |
> +			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
> +	}, {

Please add a comment that this is used for mailboxes and must be 
non-cacheable here.

> +		.virt = 0x2201f000UL,
> +		.phys = 0x2201f000UL,
> +		.size = 0x1000UL,
> +		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +			 PTE_BLOCK_NON_SHARE |
> +			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
> +	}, {
Reviewed-by: Marek Vasut <marek.vasut at mailbox.org>

Thanks !