[PATCH v3 1/6] imx9: Add support for saving DDR training data to NVM
Simona Toaca (OSS)
simona.toaca at oss.nxp.com
Thu Apr 2 11:40:43 CEST 2026
From: Simona Toaca <simona.toaca at nxp.com>
DDR training data can be saved to NVM and be available
to OEI at boot time, which will trigger QuickBoot flow.
U-Boot only checks for data integrity (CRC32), while
OEI is in charge of authentication when it tries to
load the data from NVM.
On iMX95 A0/A1, 'authentication' is done via another
CRC32. On the other boards, authentication is done by
using ELE to check the MAC stored in the ddrphy_qb_state
structure.
Supported platforms: iMX94, iMX95, iMX952 (using OEI)
Supported storage types: eMMC, SD, SPI flash.
Signed-off-by: Viorel Suman <viorel.suman at nxp.com>
Signed-off-by: Ye Li <ye.li at nxp.com>
Signed-off-by: Simona Toaca <simona.toaca at nxp.com>
---
arch/arm/include/asm/arch-imx9/ddr.h | 48 +++-
arch/arm/include/asm/mach-imx/qb.h | 15 ++
arch/arm/mach-imx/imx9/Makefile | 6 +-
arch/arm/mach-imx/imx9/qb.c | 379 +++++++++++++++++++++++++++
arch/arm/mach-imx/imx9/scmi/soc.c | 7 +
drivers/ddr/imx/imx9/Kconfig | 7 +
6 files changed, 459 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/include/asm/mach-imx/qb.h
create mode 100644 arch/arm/mach-imx/imx9/qb.c
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
index a8e3f7354c7..290e3e4e06e 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2022 NXP
+ * Copyright 2022-2026 NXP
*/
#ifndef __ASM_ARCH_IMX8M_DDR_H
@@ -100,6 +100,52 @@ struct dram_timing_info {
extern struct dram_timing_info dram_timing;
+/* Quick Boot related */
+#define DDRPHY_QB_CSR_SIZE 5168
+#define DDRPHY_QB_ACSM_SIZE (4 * 1024)
+#define DDRPHY_QB_MSB_SIZE 0x200
+#define DDRPHY_QB_PSTATES 0
+#define DDRPHY_QB_PST_SIZE (DDRPHY_QB_PSTATES * 4 * 1024)
+
+/**
+ * This structure needs to be aligned with the one in OEI.
+ */
+struct ddrphy_qb_state {
+ u32 crc; /* Used for ensuring integrity in DRAM */
+#define MAC_LENGTH 8 /* 256 bits, 32-bit aligned */
+ u32 mac[MAC_LENGTH]; /* For 95A0/1 use mac[0] to keep CRC32 value */
+ u8 trained_vrefca_a0;
+ u8 trained_vrefca_a1;
+ u8 trained_vrefca_b0;
+ u8 trained_vrefca_b1;
+ u8 trained_vrefdq_a0;
+ u8 trained_vrefdq_a1;
+ u8 trained_vrefdq_b0;
+ u8 trained_vrefdq_b1;
+ u8 trained_vrefdqu_a0;
+ u8 trained_vrefdqu_a1;
+ u8 trained_vrefdqu_b0;
+ u8 trained_vrefdqu_b1;
+ u8 trained_dramdfe_a0;
+ u8 trained_dramdfe_a1;
+ u8 trained_dramdfe_b0;
+ u8 trained_dramdfe_b1;
+ u8 trained_dramdca_a0;
+ u8 trained_dramdca_a1;
+ u8 trained_dramdca_b0;
+ u8 trained_dramdca_b1;
+ u16 qb_pll_upll_prog0;
+ u16 qb_pll_upll_prog1;
+ u16 qb_pll_upll_prog2;
+ u16 qb_pll_upll_prog3;
+ u16 qb_pll_ctrl1;
+ u16 qb_pll_ctrl4;
+ u16 qb_pll_ctrl5;
+ u16 csr[DDRPHY_QB_CSR_SIZE];
+ u16 acsm[DDRPHY_QB_ACSM_SIZE];
+ u16 pst[DDRPHY_QB_PST_SIZE];
+};
+
void ddr_load_train_firmware(enum fw_type type);
int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);
diff --git a/arch/arm/include/asm/mach-imx/qb.h b/arch/arm/include/asm/mach-imx/qb.h
new file mode 100644
index 00000000000..aeec26718cb
--- /dev/null
+++ b/arch/arm/include/asm/mach-imx/qb.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2026 NXP
+ */
+
+#ifndef __IMX_QB_H__
+#define __IMX_QB_H__
+
+#include <stdbool.h>
+
+bool qb_check(void);
+int qb(int qb_dev, bool save);
+void spl_qb_save(void);
+
+#endif
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 53cc97c6b47..d2e44f0d5f9 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright 2022 NXP
+# Copyright 2022,2026 NXP
obj-y += lowlevel_init.o
@@ -12,4 +12,6 @@ endif
ifneq ($(CONFIG_SPL_BUILD),y)
obj-y += imx_bootaux.o
-endif
\ No newline at end of file
+endif
+
+obj-y += qb.o
diff --git a/arch/arm/mach-imx/imx9/qb.c b/arch/arm/mach-imx/imx9/qb.c
new file mode 100644
index 00000000000..220545192d4
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/qb.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * Copyright 2024-2026 NXP
+ */
+#include <dm/device-internal.h>
+#include <dm/uclass.h>
+#include <errno.h>
+#include <imx_container.h>
+#include <linux/bitfield.h>
+#include <mmc.h>
+#include <spi_flash.h>
+#include <spl.h>
+#include <stdlib.h>
+#include <u-boot/crc.h>
+
+#include <asm/arch/ddr.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/sys_proto.h>
+
+#define QB_STATE_LOAD_SIZE SZ_64K
+
+#define MMC_DEV 0
+#define QSPI_DEV 1
+
+#define IMG_FLAGS_IMG_TYPE_MASK 0xF
+#define IMG_FLAGS_IMG_TYPE(x) FIELD_GET(IMG_FLAGS_IMG_TYPE_MASK, (x))
+
+#define IMG_TYPE_DDR_TDATA_DUMMY 0xD /* dummy DDR training data image */
+
+bool qb_check(void)
+{
+ struct ddrphy_qb_state *qb_state;
+ u32 size, crc;
+
+ /**
+ * Ensure CRC is not empty, the reason is that
+ * the data is invalidated after first save run
+ * or after it is overwritten.
+ */
+ qb_state = (struct ddrphy_qb_state *)CONFIG_QB_SAVED_STATE_BASE;
+ size = sizeof(struct ddrphy_qb_state) - sizeof(qb_state->crc);
+ crc = crc32(0, (u8 *)qb_state->mac, size);
+
+ if (!qb_state->crc || crc != qb_state->crc)
+ return false;
+
+ return true;
+}
+
+static unsigned long qb_get_boot_device_offset(void *dev, int dev_type)
+{
+ unsigned long offset = 0;
+ struct mmc *mmc;
+
+ switch (dev_type) {
+ case MMC_DEV:
+ mmc = dev;
+
+ if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
+ offset = CONTAINER_HDR_MMCSD_OFFSET;
+ } else {
+ u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+
+ if (part == EMMC_BOOT_PART_BOOT1 || part == EMMC_BOOT_PART_BOOT2)
+ offset = CONTAINER_HDR_EMMC_OFFSET;
+ else
+ offset = CONTAINER_HDR_MMCSD_OFFSET;
+ }
+ break;
+ case QSPI_DEV:
+ offset = CONTAINER_HDR_QSPI_OFFSET;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return offset;
+}
+
+static int qb_parse_container(void *addr, u32 *qb_data_off)
+{
+ struct container_hdr *phdr;
+ struct boot_img_t *img_entry;
+ int i = 0;
+ u32 img_type, img_end;
+
+ phdr = addr;
+ if (phdr->tag != 0x87 || (phdr->version != 0x0 && phdr->version != 0x2))
+ return -EINVAL;
+
+ img_entry = addr + sizeof(struct container_hdr);
+ for (i = 0; i < phdr->num_images; i++) {
+ img_type = IMG_FLAGS_IMG_TYPE(img_entry->hab_flags);
+ if (img_type == IMG_TYPE_DDR_TDATA_DUMMY && img_entry->size == 0) {
+ /* Image entry pointing to DDR Training Data */
+ *qb_data_off = img_entry->offset;
+ return 0;
+ }
+
+ img_end = img_entry->offset + img_entry->size;
+ if (i + 1 < phdr->num_images) {
+ img_entry++;
+ if (img_end + QB_STATE_LOAD_SIZE == img_entry->offset) {
+ /* hole detected */
+ *qb_data_off = img_end;
+ return 0;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int get_dev_qbdata_offset(void *dev, int dev_type, unsigned long offset,
+ u32 *qbdata_offset)
+{
+ int ret = -EOPNOTSUPP;
+ u16 ctnr_hdr_align = CONTAINER_HDR_ALIGNMENT;
+ void *buf = kmalloc(ctnr_hdr_align, GFP_KERNEL);
+
+ if (!buf) {
+ printf("kmalloc buffer failed\n");
+ return -ENOMEM;
+ }
+
+ switch (dev_type) {
+ case MMC_DEV:
+ unsigned long count = 0;
+ struct mmc *mmc = dev;
+
+ if (!(CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(MMC_WRITE)))
+ goto get_dev_qbdata_offset_exit;
+
+ count = blk_dread(mmc_get_blk_desc(mmc),
+ offset / mmc->read_bl_len,
+ ctnr_hdr_align / mmc->read_bl_len,
+ buf);
+ if (count == 0) {
+ printf("Read container image from MMC/SD failed\n");
+ ret = -EIO;
+ goto get_dev_qbdata_offset_exit;
+ }
+ break;
+ case QSPI_DEV:
+ if (!CONFIG_IS_ENABLED(SPI))
+ goto get_dev_qbdata_offset_exit;
+
+ ret = spi_flash_read(dev, offset,
+ ctnr_hdr_align, buf);
+ if (ret) {
+ printf("Read container header from QSPI failed\n");
+ ret = -EIO;
+ goto get_dev_qbdata_offset_exit;
+ }
+ break;
+ default:
+ printf("Support for device %d not enabled\n", dev_type);
+ goto get_dev_qbdata_offset_exit;
+ }
+
+ ret = qb_parse_container(buf, qbdata_offset);
+
+get_dev_qbdata_offset_exit:
+ free(buf);
+
+ return ret;
+}
+
+static int get_qbdata_offset(void *dev, int dev_type, u32 *qbdata_offset)
+{
+ u32 offset = qb_get_boot_device_offset(dev, dev_type);
+ u16 ctnr_hdr_align = CONTAINER_HDR_ALIGNMENT;
+ u32 cont_offset;
+ int ret, i;
+
+ for (i = 0; i < 3; i++) {
+ cont_offset = offset + i * ctnr_hdr_align;
+ ret = get_dev_qbdata_offset(dev, dev_type, cont_offset, qbdata_offset);
+ if (ret == 0) {
+ (*qbdata_offset) += cont_offset;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int qb_mmc_get_device_index(u32 dev)
+{
+ switch (dev) {
+ case BOOT_DEVICE_MMC1:
+ return 0;
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC2_2:
+ return 1;
+ }
+
+ return -ENODEV;
+}
+
+static int qb_mmc_find_device(struct mmc **mmcp, int mmc_dev)
+{
+ int ret;
+
+ ret = mmc_init_device(mmc_dev);
+ if (ret)
+ return ret;
+
+ *mmcp = find_mmc_device(mmc_dev);
+
+ return *mmcp ? 0 : -ENODEV;
+}
+
+static int qb_mmc(int dev, bool save)
+{
+ struct mmc *mmc;
+ int ret = 0, mmc_dev;
+ bool has_hw_part;
+ u8 orig_part, part;
+ u32 offset;
+ void *buf;
+
+ if (!(CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(MMC_WRITE))) {
+ printf("Please enable MMC and MMC_WRITE.\n");
+ return -EOPNOTSUPP;
+ }
+
+ mmc_dev = qb_mmc_get_device_index(dev);
+ if (mmc_dev < 0)
+ return mmc_dev;
+
+ ret = qb_mmc_find_device(&mmc, mmc_dev);
+ if (ret) {
+ printf("MMC %d not found.\n", mmc_dev);
+ return ret;
+ }
+
+ ret = mmc_init(mmc);
+ if (ret)
+ return ret;
+
+ has_hw_part = !IS_SD(mmc) && mmc->part_config != MMCPART_NOAVAILABLE;
+
+ if (has_hw_part) {
+ orig_part = mmc_get_blk_desc(mmc)->hwpart;
+ part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+
+ /* Select the partition */
+ ret = mmc_switch_part(mmc, part);
+ if (ret)
+ return ret;
+ }
+
+ ret = get_qbdata_offset(mmc, MMC_DEV, &offset);
+ if (ret)
+ return ret;
+
+ if (save) {
+ /* QB data is stored in DDR -> can use it as buf */
+ buf = (void *)CONFIG_QB_SAVED_STATE_BASE;
+ ret = blk_dwrite(mmc_get_blk_desc(mmc),
+ offset / mmc->write_bl_len,
+ QB_STATE_LOAD_SIZE / mmc->write_bl_len,
+ (const void *)buf);
+ } else {
+ /* erase */
+ ret = blk_derase(mmc_get_blk_desc(mmc),
+ offset / mmc->write_bl_len,
+ QB_STATE_LOAD_SIZE / mmc->write_bl_len);
+ }
+
+ if (!ret)
+ return -EIO;
+
+ if (!has_hw_part)
+ return 0;
+
+ /* Return to original partition */
+ return mmc_switch_part(mmc, orig_part);
+}
+
+static int qb_spi_find_device(struct spi_flash **dev)
+{
+ int ret;
+ struct udevice *udev;
+
+ ret = uclass_first_device_err(UCLASS_SPI_FLASH, &udev);
+
+ if (ret)
+ return ret;
+
+ *dev = dev_get_uclass_priv(udev);
+
+ return *dev ? 0 : -ENODEV;
+}
+
+static int qb_spi(int dev, bool save)
+{
+ int ret = 0;
+ u32 offset;
+ void *buf;
+ struct spi_flash *flash;
+
+ if (!CONFIG_IS_ENABLED(SPI)) {
+ printf("Please enable SPI.\n");
+ return -EOPNOTSUPP;
+ }
+
+ ret = qb_spi_find_device(&flash);
+ if (ret) {
+ printf("SPI flash not found.\n");
+ return -ENODEV;
+ }
+
+ ret = get_qbdata_offset(flash, QSPI_DEV, &offset);
+ if (ret)
+ return ret;
+
+ ret = spi_flash_erase(flash, offset,
+ QB_STATE_LOAD_SIZE);
+
+ if (ret)
+ return ret;
+
+ if (!save)
+ return 0;
+
+ /* QB data is stored in DDR -> can use it as buf */
+ buf = (void *)CONFIG_QB_SAVED_STATE_BASE;
+ ret = spi_flash_write(flash, offset,
+ QB_STATE_LOAD_SIZE, buf);
+
+ return ret;
+}
+
+int qb(int qb_dev, bool save)
+{
+ int ret = -EINVAL;
+
+ if (save && !qb_check())
+ return ret;
+
+ switch (qb_dev) {
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+ case BOOT_DEVICE_MMC2_2:
+ ret = qb_mmc(qb_dev, save);
+ break;
+ case BOOT_DEVICE_SPI:
+ ret = qb_spi(qb_dev, save);
+ break;
+ default:
+ printf("Unsupported quickboot device\n");
+ break;
+ }
+
+ if (ret)
+ return ret;
+
+ if (!save)
+ return 0;
+
+ /**
+ * invalidate qb_state mem so that at next boot
+ * the check function will fail and save won't happen
+ */
+ memset((void *)CONFIG_QB_SAVED_STATE_BASE, 0, sizeof(struct ddrphy_qb_state));
+
+ return 0;
+}
+
+void spl_qb_save(void)
+{
+ int dev = spl_boot_device();
+
+ /* Save QB data on current boot device */
+ if (qb(dev, true))
+ printf("QB save failed\n");
+}
diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c
index fbee435786c..86570e763d7 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -310,6 +310,13 @@ static struct mm_region imx9_mem_map[] = {
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* QB data */
+ .virt = CONFIG_QB_SAVED_STATE_BASE,
+ .phys = CONFIG_QB_SAVED_STATE_BASE,
+ .size = 0x200000UL, /* 2M */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
}, {
/* empty entry to split table entry 5 if needed when TEEs are used */
0,
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
index 0a45340ffb6..de1f59bfaf5 100644
--- a/drivers/ddr/imx/imx9/Kconfig
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -29,4 +29,11 @@ config SAVED_DRAM_TIMING_BASE
info into memory for low power use.
default 0x2051C000
+config QB_SAVED_STATE_BASE
+ hex "Define the base address for saved QuickBoot state"
+ default 0x8fe00000
+ help
+ Once DRAM is trained, the resulted training info is
+ saved into memory in order to be reachable from U-Boot.
+
endmenu
--
2.43.0
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