[PATCH v1 3/3] imx952_evk: Enable ENETC0
alice.guo at oss.nxp.com
alice.guo at oss.nxp.com
Fri Apr 3 11:41:28 CEST 2026
From: Alice Guo <alice.guo at nxp.com>
Enable ENETC0 functionality on the i.MX952 EVK board.
Signed-off-by: Alice Guo <alice.guo at nxp.com>
---
arch/arm/dts/imx952-evk-u-boot.dtsi | 94 +++++++++++++++++++++++++++++++++
arch/arm/dts/imx952-u-boot.dtsi | 100 ++++++++++++++++++++++++++++++++++++
configs/imx952_evk_defconfig | 3 ++
3 files changed, 197 insertions(+)
diff --git a/arch/arm/dts/imx952-evk-u-boot.dtsi b/arch/arm/dts/imx952-evk-u-boot.dtsi
index b872c3a7273..2a1770e694a 100644
--- a/arch/arm/dts/imx952-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx952-evk-u-boot.dtsi
@@ -5,6 +5,100 @@
#include "imx952-u-boot.dtsi"
+&enetc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enetc0>;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&lpi2c6 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c6>;
+ status = "okay";
+
+ pcal6416: gpio at 21 {
+ compatible = "nxp,pcal6416";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x21>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcal6416>;
+ vcc-supply = <®_3p3v>;
+ };
+};
+
+&netc_blk_ctrl {
+ status = "okay";
+};
+
+&netc_bus0 {
+ status = "okay";
+};
+
+&netc_emdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emdio>;
+ status = "okay";
+
+ ethphy0: ethernet-phy at 1 {
+ reg = <1>;
+ reset-gpios = <&pcal6416 13 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <80000>;
+ realtek,clkout-disable;
+ };
+};
+
+&netc_timer {
+ status = "okay";
+};
+
&wdog3 {
status = "disabled";
};
+
+&scmi_iomuxc {
+ pinctrl_lpi2c6: lpi2c6grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e
+ IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6416: pcal6416grp {
+ fsl,pins = <
+ IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e
+ >;
+ };
+
+ pinctrl_emdio: emdiogrp{
+ fsl,pins = <
+ IMX952_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e
+ IMX952_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e
+ >;
+ };
+
+ pinctrl_enetc0: enetc0grp {
+ fsl,pins = <
+ IMX952_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e
+ IMX952_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e
+ IMX952_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e
+ IMX952_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e
+ IMX952_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x50e
+ IMX952_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
+ IMX952_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x50e
+ IMX952_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
+ IMX952_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x50e
+ IMX952_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x50e
+ IMX952_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x50e
+ IMX952_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x50e
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi
index e977014992e..179e287dbf2 100644
--- a/arch/arm/dts/imx952-u-boot.dtsi
+++ b/arch/arm/dts/imx952-u-boot.dtsi
@@ -223,6 +223,106 @@
&{/soc} {
bootph-all;
+
+ netc_blk_ctrl: netc-blk-ctrl at 4cd20000 {
+ compatible = "nxp,imx952-netc-blk-ctrl";
+ reg = <0x0 0x4cd20000 0x0 0x10000>,
+ <0x0 0x4cd30000 0x0 0x10000>,
+ <0x0 0x4c81000c 0x0 0x1c>;
+ reg-names = "ierb", "prb", "netcmix";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ power-domains = <&scmi_devpd IMX952_PD_NETC>;
+ assigned-clocks = <&scmi_clk IMX952_CLK_ENET>,
+ <&scmi_clk IMX952_CLK_ENETREF>;
+ assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD2>,
+ <&scmi_clk IMX952_CLK_SYSPLL1_PFD0>;
+ assigned-clock-rates = <666666666>, <250000000>;
+ clocks = <&scmi_clk IMX952_CLK_CGC_NETC>;
+ clock-names = "ipg";
+
+ netc_bus0: pcie at 4ca00000 {
+ compatible = "pci-host-ecam-generic";
+ reg = <0x0 0x4ca00000 0x0 0x100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x0 0x0>;
+ msi-map = <0x000 &its 0x60 0x1>, //ENETC0 PF
+ <0x001 &its 0x62 0x1>, //NETC Timer
+ <0x002 &its 0x63 0x1>, //EMDIO
+ <0x040 &its 0x64 0x1>; //ENETC0 VF
+ /* ENETC0 BAR0 - non-prefetchable memory */
+ ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0x40000
+ /* Timer and EMDIO BAR0/2 and ENETC0 VF BAR0 - non-prefetchable memory */
+ 0x82000000 0x0 0x4cc80000 0x0 0x4cc80000 0x0 0x70000
+ /* ENETC0 VF BAR2 - non-prefetchable memory */
+ 0x82000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000>;
+
+ enetc0: ethernet at 0,0 {
+ compatible = "pci1131,e101";
+ reg = <0x00000 0 0 0 0>;
+ clocks = <&scmi_clk IMX952_CLK_ENETREF>;
+ clock-names = "ref";
+ status = "disabled";
+ };
+
+ netc_timer: ethernet at 0,1 {
+ compatible = "pci1131,ee02";
+ reg = <0x00100 0 0 0 0>;
+ status = "disabled";
+ };
+
+ netc_emdio: mdio at 0,2 {
+ compatible = "pci1131,ee00";
+ reg = <0x00200 0 0 0 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rcec at 1,0 {
+ compatible = "pci1131,e001";
+ reg = <0x00800 0 0 0 0>;
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ netc_bus1: pcie at 4cb00000 {
+ compatible = "pci-host-ecam-generic";
+ reg = <0x0 0x4cb00000 0x0 0x100000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x1 0x1>;
+ msi-map = <0x100 &its 0x61 0x1>, //ENETC1 PF
+ <0x140 &its 0x65 0x1>; //ENETC1 VF
+ /* ENETC1 BAR0 - non-prefetchable memory */
+ ranges = <0x82000000 0x0 0x4cc40000 0x0 0x4cc40000 0x0 0x40000
+ /* ENETC1: VF BAR0 - non-prefetchable memory */
+ 0x82000000 0x0 0x4ccf0000 0x0 0x4ccf0000 0x0 0x10000
+ /* ENETC1: VF BAR2 - non-prefetchable memory */
+ 0x82000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>;
+ power-domains = <&scmi_devpd IMX952_PD_NETC>;
+
+ enetc1: ethernet at 0,0 {
+ compatible = "pci1131,e101";
+ reg = <0x10000 0 0 0 0>;
+ clocks = <&scmi_clk IMX952_CLK_ENETREF>;
+ clock-names = "ref";
+ status = "disabled";
+ };
+
+ rcec at 1,0 {
+ compatible = "pci1131,e001";
+ reg = <0x10800 0 0 0 0>;
+ interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+ };
};
&sram0 {
diff --git a/configs/imx952_evk_defconfig b/configs/imx952_evk_defconfig
index a700aea67a1..c03f3dec89d 100644
--- a/configs/imx952_evk_defconfig
+++ b/configs/imx952_evk_defconfig
@@ -40,6 +40,7 @@ CONFIG_DEFAULT_FDT_FILE="freescale/imx952-evk.dtb"
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
CONFIG_BOARD_LATE_INIT=y
+CONFIG_PCI_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x30000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_LOAD_IMX_CONTAINER=y
@@ -111,6 +112,8 @@ CONFIG_DM_PCA953X=y
CONFIG_ADP5585_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
CONFIG_IMX_MU_MBOX=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
--
2.43.0
More information about the U-Boot
mailing list