[PATCH 2/3] net: zynq_gem: set 128-bit AXI bus width for 10GBE

[Pranav Tilak]

Set 128-bit AXI bus width in network config for 10GBE. The default 64-bit
setting causes DMA data corruption.

Signed-off-by: Pranav Tilak <pranav.vinaytilak at amd.com>
---
 drivers/net/zynq_gem.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index c06d114af68..e9210d42438 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -69,10 +69,13 @@
 #define ZYNQ_GEM_NWCFG_SGMII_ENBL	0x08000000 /* SGMII Enable */
 #define ZYNQ_GEM_NWCFG_PCS_SEL		0x00000800 /* PCS select */
 
+#define ZYNQ_GEM_DBUS_WIDTH_MASK	(3 << 21) /* bits 22:21 */
 #ifdef CONFIG_ARM64
 # define ZYNQ_GEM_DBUS_WIDTH	(1 << 21) /* 64 bit bus */
+# define ZYNQ_GEM_DBUS_WIDTH_128	(2 << 21) /* 128 bit bus */
 #else
 # define ZYNQ_GEM_DBUS_WIDTH	(0 << 21) /* 32 bit bus */
+# define ZYNQ_GEM_DBUS_WIDTH_128	(0 << 21) /* 32 bit bus */
 #endif
 
 #define ZYNQ_GEM_NWCFG_INIT		(ZYNQ_GEM_DBUS_WIDTH | \
@@ -533,6 +536,8 @@ static int zynq_gem_init(struct udevice *dev)
 	nwconfig = ZYNQ_GEM_NWCFG_INIT;
 
 	if (device_is_compatible(dev, "amd,versal2-10gbe")) {
+		nwconfig &= ~ZYNQ_GEM_DBUS_WIDTH_MASK;
+		nwconfig |= ZYNQ_GEM_DBUS_WIDTH_128;
 		if (priv->interface == PHY_INTERFACE_MODE_10GBASER) {
 			ctrl = readl(&regs->nwcfg);
 			ctrl |= PCSSEL;
-- 
2.43.0