[PATCH] arm: socfpga: Remove confusing timer related words from watchdog reset

[Chee, Tien Fong]

> From: Maniyam, Dinesh <dinesh.maniyam at altera.com>
> Sent: Wednesday, February 25, 2026 1:19 PM
> To: u-boot at lists.denx.de <u-boot at lists.denx.de>
> Cc: Marek Vasut <marex at denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt at gmail.com>; Tom Rini <trini at konsulko.com>; Chee, Tien
> Fong <tien.fong.chee at altera.com>; Hea, Kok Kiang <kok.kiang.hea at altera.com>;
> Maniyam, Dinesh <dinesh.maniyam at altera.com>; Ng, Boon Khai
> <boon.khai.ng at altera.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi at altera.com>; Tien Fong Chee <tien.fong.chee at intel.com>
> Subject: [PATCH] arm: socfpga: Remove confusing timer related words from
> watchdog reset
> From: Dinesh Maniyam <dinesh.maniyam at altera.com>
> It's confusing to have timer related words along with watchdog reset
> dessert function, because the function is only release watchdog from
> reset, so it has not related to any timer setting.
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> Signed-off-by: Dinesh Maniyam <dinesh.maniyam at altera.com>
> ---
>  arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +-
>  arch/arm/mach-socfpga/reset_manager_arria10.c              | 4 ++--
>  arch/arm/mach-socfpga/spl_a10.c                            | 4 ++--
>  3 files changed, 5 insertions(+), 5 deletions(-)
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> index 26faa628a05..9aacf3e2c62 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> @@ -12,7 +12,7 @@
>  void socfpga_watchdog_disable(void);
>  void socfpga_reset_deassert_noc_ddr_scheduler(void);
>  int socfpga_reset_deassert_bridges_handoff(void);
> -void socfpga_reset_deassert_osc1wd0(void);
> +void socfpga_reset_deassert_wd0(void);
>  int socfpga_bridges_reset(void);
>  #define RSTMGR_A10_STATUS       0x00
> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> b/arch/arm/mach-socfpga/reset_manager_arria10.c
> index da335f4292c..54ab7b13439 100644
> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> @@ -108,8 +108,8 @@ int socfpga_reset_deassert_bridges_handoff(void)
>                                   mask_noc, false, 1000, false);
>  }
> -/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
> -void socfpga_reset_deassert_osc1wd0(void)
> +/* Release Watchdog 0 from reset through reset manager */
> +void socfpga_reset_deassert_wd0(void)
>  {
>          clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
>                       ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
> index c20376f7f8e..320e090e57b 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -266,8 +266,8 @@ void board_init_f(ulong dummy)
>          cm_basic_init(gd->fdt_blob);
>  #ifdef CONFIG_HW_WATCHDOG
> -       /* release osc1 watchdog timer 0 from reset */
> -       socfpga_reset_deassert_osc1wd0();
> +       /* release watchdog 0 from reset */
> +       socfpga_reset_deassert_wd0();
>          /* reconfigure and enable the watchdog */
>          hw_watchdog_init();
> --
> 2.43.7

Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>

Best regards,
Tien Fong