[PATCH] arm: socfpga: Add NAND register address and data register

[Chee, Tien Fong]

On 4/3/2026 11:37 am, dinesh.maniyam at altera.com wrote:
> From: Dinesh Maniyam<dinesh.maniyam at altera.com>
>
> These are required by denali_spl.c for Arria10. Pre-set nand base and
> data address will be used for spl nand read and write.
>
> Signed-off-by: Tien Fong Chee<tien.fong.chee at intel.com>
> Signed-off-by: Dinesh Maniyam<dinesh.maniyam at altera.com>
> ---
>   arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> index b947cc07291..120cbfa23a5 100644
> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> @@ -12,6 +12,8 @@
>   #define SOCFPGA_SDMMC_ADDRESS			0xff808000
>   #define SOCFPGA_QSPIREGS_ADDRESS		0xff809000
>   #define SOCFPGA_QSPIDATA_ADDRESS		0xffa00000
> +#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
> +#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
>   #define SOCFPGA_UART1_ADDRESS			0xffc02100
>   #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xffcfa000
>   #define SOCFPGA_FPGAMGRDATA_ADDRESS		0xffcfe400

Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com> Best regards, 
Tien Fong