[PATCH v1] drivers: cadence_qspi_apb: Add 1us delays in polling loops

[Tom Rini]

On Thu, Mar 12, 2026 at 07:44:19PM +0800, Boon Khai Ng wrote:

> Add 1us delays in busy-wait polling loops to reduce CPU usage, minimize
> bus traffic, and prevent watchdog timeout during QSPI operations.
> 
> Three tight polling loops continuously check hardware status without
> any delay, consuming excessive CPU cycles and potentially triggering
> watchdog timeout on long operations. Adding small delays allows the
> hardware time to respond and reduces unnecessary register reads.
> 
> The udelay() function includes WATCHDOG_RESET()/schedule() calls that
> service the watchdog, preventing system reset during extended QSPI
> transfers.
> 
> Signed-off-by: Boon Khai Ng <boon.khai.ng at altera.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 3 +++
>  1 file changed, 3 insertions(+)

So, this is fine, BUT it pushes socfpga_vining_fpga over the size limit.
And I see SoCFPGA isn't enabling LTO at all. Can you please get that
tested on at least some SoCFPGA platforms and then enable it for all?
Then we can continue down this path, thanks!

-- 
Tom
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