[PATCH] arm: arria10: Add correct mask bits for RTRIM and PU_DRV_STRG

[Chee, Tien Fong]

On 4/3/2026 12:12 pm, dinesh.maniyam at altera.com wrote:

> From: Dinesh Maniyam<dinesh.maniyam at altera.com>
>
> The current mask bits of RTRIM and PU_DRV_STRG are mismatched with the
> configuration register of arria10. The correct register for RTRIM and
> PU_DRV_STRG should be 0x7 and 0x1f respectively.
>
> Signed-off-by: Dinesh Maniyam<dinesh.maniyam at altera.com>
> ---
>   arch/arm/mach-socfpga/qts-filter-a10.sh | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh b/arch/arm/mach-socfpga/qts-filter-a10.sh
> index ab16522add5..510947d5632 100755
> --- a/arch/arm/mach-socfpga/qts-filter-a10.sh
> +++ b/arch/arm/mach-socfpga/qts-filter-a10.sh
> @@ -106,11 +106,11 @@ EOF
>   	echo
>   	echo "/* Macro for Config IO bit mapping */"
>   	echo -n "#define CONFIG_IO_MACRO(NAME) "
> -	echo "(((NAME ## _RTRIM & 0xff) << 19) | \\"
> +	echo "(((NAME ## _RTRIM & 0x7) << 19) | \\"
>   	echo "	((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\"
>   	echo "	((NAME ## _WK_PU_EN & 0x1) << 16) | \\"
>   	echo "	((NAME ## _PU_SLW_RT & 0x1) << 13) | \\"
> -	echo "	((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\"
> +	echo "	((NAME ## _PU_DRV_STRG & 0x1f) << 8) | \\"
>   	echo "	((NAME ## _PD_SLW_RT & 0x1) << 5) | \\"
>   	echo "	(NAME ## _PD_DRV_STRG & 0x1f))"
>   

Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com> Best regards, 
Tien Fong