[PATCH] drivers: watchdog: Enhance watchdog support in SPL for N5X

[Maniyam, Dinesh]

Hi Tien Fong,

On 15/4/2026 5:51 pm, Chee, Tien Fong wrote:
>
> Hi Dinesh,
>
>
> On 4/3/2026 12:08 pm, dinesh.maniyam at altera.com wrote:
>> From: Dinesh Maniyam<dinesh.maniyam at altera.com>
>
>
> commit subject scope mismatch, expect arm: socfpga: spl_n5x: ...
>
>
>> Enable watchdog before initializing other component (example: DDR).
>> Thus, watchdog need to be fully executed in onchip ram.
>
>
> The commit message does not fully describe the actual change which 
> switches from the
>
> legacy CONFIG_HW_WATCHDOG path (hw_watchdog_init()) to
>
> DM watchdog init (initr_watchdog() with CONFIG_IS_ENABLED(WDT)).
>
> Please update the message to clearly state that behavior change and 
> rationale
>
> Wording/grammar Minor wording clean-up would help readability, e.g.:
> “before initializing other components”
> “Watchdog needs to be enabled after the clock driver because it 
> retrieves the watchdog clock frequency.”
>
>
>> Signed-off-by: Dinesh Maniyam<dinesh.maniyam at altera.com>
>> ---
>>   arch/arm/mach-socfpga/spl_n5x.c | 17 ++++++++++-------
>>   1 file changed, 10 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c
>> index 81283ef7162..22c20f89b4b 100644
>> --- a/arch/arm/mach-socfpga/spl_n5x.c
>> +++ b/arch/arm/mach-socfpga/spl_n5x.c
>> @@ -9,6 +9,7 @@
>>   #include <asm/arch/mailbox_s10.h>
>>   #include <asm/arch/misc.h>
>>   #include <asm/arch/reset_manager.h>
>> +#include <asm/arch/smmu_s10.h>
>
>
>  doesn’t appear used by the patch itself
>
>
>>   #include <asm/arch/system_manager.h>
>>   #include <asm/global_data.h>
>>   #include <asm/io.h>
>> @@ -19,6 +20,7 @@
>>   #include <init.h>
>>   #include <spl.h>
>>   #include <watchdog.h>
>> +#include <wdt.h>
>>   
>>   DECLARE_GLOBAL_DATA_PTR;
>>   
>> @@ -37,13 +39,6 @@ void board_init_f(ulong dummy)
>>   	writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
>>   	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
>>   
>> -#ifdef CONFIG_HW_WATCHDOG
>> -	/* Enable watchdog before initializing the HW */
>> -	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
>> -	socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
>> -	hw_watchdog_init();
>> -#endif
>> -
>>   	/* ensure all processors are not released prior Linux boot */
>>   	writeq(0, CPU_RELEASE_ADDR);
>>   
>> @@ -69,6 +64,14 @@ void board_init_f(ulong dummy)
>>   		hang();
>>   	}
>>   
>> +	/*
>> +	 * Enable watchdog as early as possible before initializing other
>> +	 * component. Watchdog need to be enabled after clock driver because
>> +	 * it will retrieve the clock frequency from clock driver.
>> +	 */
>> +	if (CONFIG_IS_ENABLED(WDT))
>> +		initr_watchdog();
>> +
>>   	print_reset_info();
>>   	cm_print_clock_quick_summary();
>>   
>
> Best regards,
>
> Tien Fong
>

Thanks for the review.

I’ll update the subject to |arm: socfpga: spl_n5x:| and revise the 
commit message to clearly
describe the switch from legacy |CONFIG_HW_WATCHDOG| to DM watchdog 
(|initr_watchdog()|),
including the ordering rationale (after clock init, before DDR, 
SPL/on-chip RAM only).

I’ll also remove the unused |smmu_s10.h| include and do minor wording 
cleanups.

Will resend an updated patch.

Best regards,
Dinesh