[PATCH 0/8] spi: atcspi200: Modernize driver and add spi-mem + data merge support

[Leo Yu-Chi Liang]

This series modernizes the Andes ATCSPI200 SPI controller driver and
adds two new features: spi-mem framework support (including dual/quad
modes) and an optional 4-byte data merge mode for higher throughput on
aligned transfers.

Patches 1-4 are cleanups and fixes with no intended functional change
to existing behavior:

  1. Replace volatile struct register access with readl()/writel() +
     offset defines, convert bit macros to BIT()/GENMASK()/FIELD_PREP(),
     modernize DT parsing (dev_read_u32_default, dev_remap_addr),
     rename struct nds_spi_slave to atcspi200_priv, and fix coding
     style throughout.
  2. Improve clock configuration: add sensible fallbacks for clock
     source and max frequency, honor spi-max-frequency from DT, use a
     round-up divider that picks the closest frequency not exceeding
     the target, and stop clobbering clock settings on every stop().
  3. Replace manual busy-wait counters with wait_for_bit_le32() and
     get_timer() based timeouts so the driver benefits from watchdog
     handling and time-based (rather than iteration-based) limits.
  4. Remove a duplicate atcspi200_hw_stop() call after the transfer
     loop and simplify the CHUNK_SIZE=1 transfer logic that had
     accumulated dead variables. Also includes a Fixes: tag for the
     duplicate-stop issue.

Patches 5-6 add new functionality:

  5. Wire up spi_controller_mem_ops so the driver can service the
     spi-mem framework with proper cmd/addr/dummy/data phase handling
     and single/dual/quad bus widths. A shared atcspi200_pio_transfer()
     helper is used by both the spi-mem and legacy xfer paths.
  6. Add CONFIG_ATCSPI200_SPI_DATA_MERGE. When enabled and the
     transfer is 4-byte aligned, the driver uses 32-bit FIFO accesses
     (one u32 per register access instead of one byte) for a
     meaningful throughput improvement. Data merge is enabled/disabled
     dynamically per transfer based on alignment.

Patches 7-8 are consumers of the new support:

  7. Add quad-mode (1-4-4) read and page-program fixups for Macronix
     MX25U1635E and MX25U25635F, which do not advertise their quad
     capabilities correctly via SFDP.
  8. Enable CONFIG_ATCSPI200_SPI_DATA_MERGE in all AE350 defconfig
     variants.

Tested on AE350 with MX25U1635E and MX25U25635F flash in 1-1-1, 1-1-4,
and 1-4-4 modes, with and without data merge.

Leo Yu-Chi Liang (8):
  spi: atcspi200: Clean up register access, macros, naming, DT parsing,
    and style
  spi: atcspi200: Improve clock configuration and divider logic
  spi: atcspi200: Use proper timeout handling for busy-wait loops
  spi: atcspi200: Fix double stop call and simplify transfer loop
  spi: atcspi200: Add spi-mem framework support
  spi: atcspi200: Add data merge mode support
  mtd: spi-nor: Add Macronix MX25U quad-mode fixups
  configs: ae350: Enable ATCSPI200 data merge mode

 configs/ae350_rv32_defconfig            |   1 +
 configs/ae350_rv32_falcon_defconfig     |   1 +
 configs/ae350_rv32_falcon_xip_defconfig |   1 +
 configs/ae350_rv32_spl_defconfig        |   1 +
 configs/ae350_rv32_spl_xip_defconfig    |   1 +
 configs/ae350_rv32_xip_defconfig        |   1 +
 configs/ae350_rv64_defconfig            |   1 +
 configs/ae350_rv64_falcon_defconfig     |   1 +
 configs/ae350_rv64_falcon_xip_defconfig |   1 +
 configs/ae350_rv64_spl_defconfig        |   1 +
 configs/ae350_rv64_spl_xip_defconfig    |   1 +
 configs/ae350_rv64_xip_defconfig        |   1 +
 drivers/mtd/spi/spi-nor-core.c          |  25 +-
 drivers/spi/Kconfig                     |   9 +
 drivers/spi/atcspi200_spi.c             | 658 ++++++++++++++----------
 15 files changed, 436 insertions(+), 268 deletions(-)

-- 
2.34.1