[PATCH 6/8] spi: atcspi200: Add data merge mode support
Leo Yu-Chi Liang
ycliang at andestech.com
Fri Apr 17 04:40:32 CEST 2026
Add CONFIG_ATCSPI200_SPI_DATA_MERGE option to enable 4-byte data
merge mode for the ATCSPI200 SPI controller. When enabled, each
write to the data register transmits four bytes, and each read
retrieves four bytes as a single word, improving throughput for
aligned transfers.
- Add DATA_MERGE bit (bit 7) in format register
- Add data_merge field to private data structure
- Update TX/RX helpers to handle u32 access when data_merge is active
- Dynamically enable/disable data merge based on transfer alignment
(nbytes % 4 == 0) in both spi-mem exec_op and legacy xfer paths
- Use IS_ENABLED() consistently for the Kconfig check
- Add Kconfig entry with proper depends on ATCSPI200_SPI
Signed-off-by: Leo Yu-Chi Liang <ycliang at andestech.com>
---
drivers/spi/Kconfig | 9 ++++++
drivers/spi/atcspi200_spi.c | 62 ++++++++++++++++++++++++++++++-------
2 files changed, 59 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4ff17617d99..f238b2c2534 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -92,6 +92,15 @@ config ATCSPI200_SPI
used to access the SPI flash on AE3XX and AE250 platforms embedding
this Andestech IP core.
+config ATCSPI200_SPI_DATA_MERGE
+ bool "Enable ATCSPI200 data merge mode"
+ depends on ATCSPI200_SPI
+ help
+ Enable data merge mode for the ATCSPI200 SPI controller.
+ When enabled, each write to the data register transmits four
+ bytes, and each read retrieves four bytes as a single word.
+ This improves throughput for aligned transfers.
+
config ATH79_SPI
bool "Atheros SPI driver"
depends on ARCH_ATH79
diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c
index cef0bb8188d..b743f80fb8d 100644
--- a/drivers/spi/atcspi200_spi.c
+++ b/drivers/spi/atcspi200_spi.c
@@ -36,6 +36,7 @@
/* FORMAT register fields */
#define ADDR_LEN_MASK GENMASK(17, 16)
#define DATA_LEN_MASK GENMASK(12, 8)
+#define DATA_MERGE BIT(7)
/* TCTRL register fields */
#define TCTRL_CMD_EN BIT(30)
@@ -89,6 +90,7 @@ struct atcspi200_priv {
size_t tran_len;
void *din;
const void *dout;
+ bool data_merge;
unsigned int max_transfer_length;
};
@@ -149,6 +151,10 @@ static int atcspi200_hw_claim_bus(struct atcspi200_priv *priv)
priv->cmd_len = 0;
format = priv->mode | FIELD_PREP(DATA_LEN_MASK, 8 - 1) |
FIELD_PREP(ADDR_LEN_MASK, 3 - 1);
+ if (IS_ENABLED(CONFIG_ATCSPI200_SPI_DATA_MERGE)) {
+ format |= DATA_MERGE;
+ priv->data_merge = true;
+ }
atcspi200_write(priv, ATCSPI200_REG_FORMAT, format);
atcspi200_hw_set_speed(priv);
@@ -182,20 +188,27 @@ static int atcspi200_hw_stop(struct atcspi200_priv *priv)
SPIBSY, false, SPI_TIMEOUT_MS, false);
}
-static void atcspi200_tx_byte(struct atcspi200_priv *priv, const void *dout)
+static void atcspi200_tx(struct atcspi200_priv *priv, const void *dout)
{
- atcspi200_write(priv, ATCSPI200_REG_DATA, *(u8 *)dout);
+ if (priv->data_merge)
+ atcspi200_write(priv, ATCSPI200_REG_DATA, *(u32 *)dout);
+ else
+ atcspi200_write(priv, ATCSPI200_REG_DATA, *(u8 *)dout);
}
-static void atcspi200_rx_byte(struct atcspi200_priv *priv, void *din)
+static void atcspi200_rx(struct atcspi200_priv *priv, void *din)
{
- *(u8 *)din = (u8)atcspi200_read(priv, ATCSPI200_REG_DATA);
+ if (priv->data_merge)
+ *(u32 *)din = atcspi200_read(priv, ATCSPI200_REG_DATA);
+ else
+ *(u8 *)din = (u8)atcspi200_read(priv, ATCSPI200_REG_DATA);
}
static void atcspi200_pio_transfer(struct atcspi200_priv *priv,
void *din, const void *dout,
unsigned int len)
{
+ unsigned int step = priv->data_merge ? 4 : 1;
unsigned int tx_remain = dout ? len : 0;
unsigned int rx_remain = din ? len : 0;
unsigned long start = get_timer(0);
@@ -205,15 +218,15 @@ static void atcspi200_pio_transfer(struct atcspi200_priv *priv,
u32 status = atcspi200_read(priv, ATCSPI200_REG_STATUS);
if (tx_remain && !(status & TXFFL)) {
- atcspi200_tx_byte(priv, dout);
- dout = (const u8 *)dout + 1;
- tx_remain--;
+ atcspi200_tx(priv, dout);
+ dout = (const u8 *)dout + step;
+ tx_remain -= step;
}
if (rx_remain && (status & RXFVE_MASK)) {
- atcspi200_rx_byte(priv, din);
- din = (u8 *)din + 1;
- rx_remain--;
+ atcspi200_rx(priv, din);
+ din = (u8 *)din + step;
+ rx_remain -= step;
}
}
@@ -232,6 +245,19 @@ static int atcspi200_hw_xfer(struct atcspi200_priv *priv,
unsigned long data_len = bitlen / 8;
int ret = 0;
+ if (IS_ENABLED(CONFIG_ATCSPI200_SPI_DATA_MERGE)) {
+ u32 format = atcspi200_read(priv, ATCSPI200_REG_FORMAT);
+
+ if (data_len % 4 == 0) {
+ format |= DATA_MERGE;
+ priv->data_merge = true;
+ } else {
+ format &= ~DATA_MERGE;
+ priv->data_merge = false;
+ }
+ atcspi200_write(priv, ATCSPI200_REG_FORMAT, format);
+ }
+
max_tran_len = priv->max_transfer_length;
switch (flags) {
case SPI_XFER_BEGIN:
@@ -335,13 +361,25 @@ static int atcspi200_spi_mem_exec_op(struct spi_slave *slave,
u32 format;
int ret;
+ format = atcspi200_read(priv, ATCSPI200_REG_FORMAT);
+
+ /* Dynamically enable/disable data merge based on alignment */
+ if (IS_ENABLED(CONFIG_ATCSPI200_SPI_DATA_MERGE)) {
+ if (op->data.nbytes && (op->data.nbytes % 4 == 0)) {
+ format |= DATA_MERGE;
+ priv->data_merge = true;
+ } else {
+ format &= ~DATA_MERGE;
+ priv->data_merge = false;
+ }
+ }
+
/* Update address length in format register if needed */
if (op->addr.nbytes) {
- format = atcspi200_read(priv, ATCSPI200_REG_FORMAT);
format &= ~ADDR_LEN_MASK;
format |= FIELD_PREP(ADDR_LEN_MASK, op->addr.nbytes - 1);
- atcspi200_write(priv, ATCSPI200_REG_FORMAT, format);
}
+ atcspi200_write(priv, ATCSPI200_REG_FORMAT, format);
/* Set up transfer control for this operation */
atcspi200_set_transfer_ctl(priv, op);
--
2.34.1
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