[PATCH] arm: socfpga: Reset MPFE NoC after programming peripheral / combined RBF

[Chee, Tien Fong]

Hi Dinesh,


On 25/3/2026 1:46 pm, dinesh.maniyam at altera.com wrote:
> From: Dinesh Maniyam <dinesh.maniyam at altera.com>
>
> This patch triggers warm reset to recover the MPFE NoC from corruption
> due to high frequency transient clock output from HPS EMIF IOPLL at
> VCO startup after peripheral RBF is programmed.
>

As described in the commit message is not acceptable until the 
warm-reset / NoC recovery logic appears in the

series or the message is narrowed to “add SYSMGR ROM-code offset 
definitions for …”.


>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at intel.com>
> Signed-off-by: Dinesh Maniyam <dinesh.maniyam at altera.com>
> ---
>   arch/arm/mach-socfpga/include/mach/system_manager_arria10.h | 4 ++++
>   1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> index 0afe63e647e..73e953465a4 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> @@ -37,6 +37,10 @@
>   #define SYSMGR_A10_ISW_HANDOFF_BASE		0x230
>   #define SYSMGR_A10_ISW_HANDOFF_7		0x1c
>   
> +#define SYSMGR_A10_ROMCODE_CTRL			0x204
> +#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND	0x208
> +#define SYSMGR_A10_ISW_HANDOFF			0x230


Redundant offset / naming: SYSMGR_A10_ISW_HANDOFF is 0x230, the same 
value as SYSMGR_A10_ISW_HANDOFF_BASE

> +
>   #define SYSMGR_SDMMC				SYSMGR_A10_SDMMC
>   
>   #define SYSMGR_SDMMC_SMPLSEL_SHIFT	4