[PATCH v3 2/7] mach-snapdragon: Add FIT multi-DTB selection support

[Simon Glass]

Hi Aswin,

On 2026-04-17T12:09:44, Aswin Murugan <aswin.murugan at oss.qualcomm.com> wrote:
> mach-snapdragon: Add FIT multi-DTB selection support
>
> Implement multi DTB selection from FIT images based on hardware
> detection via SMEM.
>
> The implementation provides:
>
> 1. Hardware Detection: Reads SoC parameters from SMEM including chip ID,
>    version, platform ID, OEM variant, DDR size, and storage type from IMEM.
>
> 2. Metadata DTB Processing: Parses a metadata DTB (first image in FIT)
>    to build a "bucket list" of hardware-specific node names that match
>    the detected hardware parameters.
>
> 3. FIT Configuration Matching: Uses standard FIT mechanisms to find the
>    configuration with the most matching tokens in its compatible string
>    compared to the hardware-derived bucket list.
>
> 4. DTB Loading and Overlays: Loads the base DTB and applies any DTBOs
>    specified in the selected configuration using standard FIT overlay
> [...]
>
> arch/arm/mach-snapdragon/Kconfig             |    8 +
>  arch/arm/mach-snapdragon/Makefile            |    1 +
>  arch/arm/mach-snapdragon/board.c             |    7 +
>  arch/arm/mach-snapdragon/qcom_fit_multidtb.c | 1103 ++++++++++++++++++++++++++
>  arch/arm/mach-snapdragon/qcom_fit_multidtb.h |  189 +++++
>  5 files changed, 1308 insertions(+)

> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> @@ -585,6 +586,12 @@ int board_late_init(void)
> +     /* Try FIT multi-DTB selection if enabled */
> +     if (IS_ENABLED(CONFIG_QCOM_FIT_MULTIDTB)) {
> +             if (!qcom_fit_multidtb_setup())
> +                     log_debug("FIT multi-DTB selection not available or failed\n");
> +     }

The logic seems inverted, since qcom_fit_multidtb_setup() returns 0 on success.

> diff --git a/arch/arm/mach-snapdragon/qcom_fit_multidtb.c b/arch/arm/mach-snapdragon/qcom_fit_multidtb.c
> @@ -0,0 +1,1103 @@
> +#define TCSR_SOC_HW_VERSION        0x01fc8000

This address is hardcoded - does this mean the same TCSR base is used
on all SoCs?

> diff --git a/arch/arm/mach-snapdragon/qcom_fit_multidtb.c b/arch/arm/mach-snapdragon/qcom_fit_multidtb.c
> @@ -0,0 +1,1103 @@
> +     *ddr_type = 0;
> +     if (total_ddr_size <= DDR_128MB)
> +             *ddr_type = DDRTYPE_128MB;
> +     else if (total_ddr_size <= DDR_256MB)
> +             *ddr_type = DDRTYPE_256MB;
> +     else if (total_ddr_size <= DDR_512MB)
> +             *ddr_type = DDRTYPE_512MB;
> +     else if (total_ddr_size <= DDR_1024MB)
> +             *ddr_type = DDRTYPE_1024MB;
> +     else if (total_ddr_size <= DDR_2048MB)
> +             *ddr_type = DDRTYPE_2048MB;
> +     else if (total_ddr_size <= DDR_3072MB)
> +             *ddr_type = DDRTYPE_3072MB;
> +     else if (total_ddr_size <= DDR_4096MB)
> +             *ddr_type = DDRTYPE_4096MB;

If total_ddr_size > 4 GB, ddr_type remains 0. Is that intentional, or
should there be a final else clause for larger memory configurations?

> diff --git a/arch/arm/mach-snapdragon/qcom_fit_multidtb.c b/arch/arm/mach-snapdragon/qcom_fit_multidtb.c
> @@ -0,0 +1,1103 @@
> +     printf("DTB: %s\n", fdt_name);

Maybe use log_info() here for consistency with the rest of the file?

Reviewed-by: Simon Glass <sjg at chromium.org>

Regards,
Simon