[PATCH v1] mach-snapdragon: Add KVM hypervisor support

Simon Glass sjg at chromium.org
Mon Apr 20 06:32:10 CEST 2026


Hi Aswin,

On 2026-04-19T17:38:29, Aswin Murugan <aswin.murugan at oss.qualcomm.com> wrote:
> mach-snapdragon: Add KVM hypervisor support
>
> Enable Linux KVM virtualization on Snapdragon SoCs.
>
> Introduce CONFIG_QCOM_KVM_SUPPORT to select KVM or Gunyah
> hypervisor modes at build time.
>
> qcom-priv.h:
>  - Add TrustZone SMC interface definitions and parameter IDs
>  - Define hypervisor boot types (GUNYAH=0, KVM=1)
>  - Add TCR_EL2 bit field definitions for memory config
>
> board.c:
>  - Add qcom_configure_kvm_hypervisor() with EL-aware logic
>  - EL2: Perform direct SMC call for hypervisor setup
>  - EL1: Save context, disable caches, run SMC, restore state,
>    reconfigure TCR_EL2, re-enable caches
>  - Add qcom_configure_gunyah_hypervisor() for standard flow
>  - Add SCM service availability checks
>
> [...]
>
> arch/arm/mach-snapdragon/Kconfig     |   7 ++
>  arch/arm/mach-snapdragon/board.c     | 154 +++++++++++++++++++++++++++++++++++
>  arch/arm/mach-snapdragon/qcom-priv.h |  31 +++++++
>  3 files changed, 192 insertions(+)

> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> @@ -510,6 +510,154 @@ void __weak qcom_late_init(void)
> +     log_debug("At EL1, saving register context\n");
> +
> +     u64 ttbr0_el1, tcr_el1, tcr_el2, mair_el1;
> +     u64 t0sz, phys_addr_size;

Please can you move these declarations to the top of the function
alongside res and current_el.

> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> @@ -510,6 +510,154 @@ void __weak qcom_late_init(void)
> +     if (current_el != 2) {
> +             log_debug("No EL2 transition, skipping TCR_EL2 config\n");
> +             icache_enable();
> +             dcache_enable();
> +             log_warning("KVM hypervisor configuration failed\n");
> +             return 0;
> +     }

This logs a warning saying configuration failed but returns 0
(success). If the EL2 transition truly failed, shouldn't it an error?
If it is intentionally a soft failure, the log message should clarify
why.

> diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
> @@ -510,6 +510,154 @@ void __weak qcom_late_init(void)
> +     arm_smccc_smc(TZ_INFO_IS_SVC_AVAILABLE_ID,
> +                   TZ_INFO_IS_SVC_AVAILABLE_ID_PARAM_ID,
> +                   TZ_CONFIGURE_MILESTONE_SERVICE_ID,
> +                   0, 0, 0, 0, 0, &res);
> +
> +     if (res.a0 != 0)
> +             log_debug("KVM milestone service not available (0x%lx)\n", res.a0);

Just to check: if the service is not available, should the function
continue anyway? In qcom_configure_gunyah_hypervisor() you return
early when the service check fails, but here you continue regardless.
A brief comment explaining why would help.

> diff --git a/arch/arm/mach-snapdragon/qcom-priv.h b/arch/arm/mach-snapdragon/qcom-priv.h
> @@ -17,6 +17,37 @@ extern enum qcom_boot_source qcom_boot_source;
> +/* TCR_EL2 bit field definitions */
> +#define TCR_T0SZ_MASK                                0x1FUL
> +#define TCR_PS_MASK                          (0x7UL << 32)
> +#define TCR_PS_SHIFT                         16
> +#define TCR_SH_ORGN_IRGN_MASK                        0x3F00UL
> +#define TCR_SH_INNER_SHAREABLE                       (3UL << 12)
> +#define TCR_ORGN_WRITE_BACK_ALLOC            BIT(10)
> +#define TCR_IRGN_WRITE_BACK_ALLOC            BIT(8)

arch/arm/include/asm/armv8/mmu.h already defines TCR_IRGN_WBWA,
TCR_ORGN_WBWA, and TCR_SHARED_INNER with the same values. Please can
you reuse those existing definitions rather than duplicating them
here.

Regards,
Simon


More information about the U-Boot mailing list