[PATCH v1 2/8] arm: dts: socfpga: n5x: enable DT register settings and update GMAC nodes

[Chee, Tien Fong]

Hi Lok,


On 18/3/2026 11:00 am, Chen Huei Lok wrote:
> Enable register settings in the N5X U-Boot device tree by adding
> firewall configuration nodes under the L3 interconnect firewall.
> These settings disable OCRAM security at the CCU and relax MPFE
> firewall restrictions required during early boot.
>
> Update the GMAC nodes to include proper compatible,
> reset-names, and clock-names properties, explicitly setting
> their status.
>
> Remove the clocks property from the QSPI node in. The QSPI

The sentence ends mid-phrase. It should say "...from the QSPI node in 
socfpga_n5x_socdk-u-boot.dtsi."


> controller clock is obtained via cm_get_qspi_controller_clk_hz(),
> so the device tree clock reference is unnecessary.
>
> Additionally, include socfpga_soc64_u-boot.dtsi and rename the
> soc node to soc at 0 to align with the common SoCFPGA DT layout.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at altera.com>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> Signed-off-by: Chen Huei Lok <chen.huei.lok at altera.com>
> ---
>   arch/arm/dts/socfpga_n5x-u-boot.dtsi       | 38 +++++++++++++++++++++-
>   arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi |  1 +
>   arch/arm/dts/socfpga_n5x_socdk.dts         |  2 +-
>   3 files changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> index e27a64651e1..326ba722a25 100644
> --- a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
> @@ -5,6 +5,7 @@
>    * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
>    */
>
> +#include "socfpga_soc64_u-boot.dtsi"
>   #include "socfpga_soc64_fit-u-boot.dtsi"
>   #include <dt-bindings/clock/n5x-clock.h>
>
> @@ -15,7 +16,7 @@
>   		bootph-all;
>   	};
>
> -	soc {
> +	soc at 0 {
>   		bootph-all;
>
>   		ccu: cache-controller at f7000000 {
> @@ -46,17 +47,29 @@
>   };
>
>   &gmac0 {
> +	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> +	reset-names = "stmmaceth", "stmmaceth-ocp";
>   	clocks = <&clkmgr N5X_EMAC0_CLK>;
> +	clock-names = "stmmaceth";
> +	status = "okay";


Enabling a peripheral in a platform-level dtsi rather than a board-level 
dtsi is wrong.

Not all N5X board variants will necessarily have GMAC0 active.

The status = "okay" belongs in socfpga_n5x_socdk-u-boot.dtsi


>   };
>
>   &gmac1 {
> +	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> +	reset-names = "stmmaceth", "stmmaceth-ocp";
>   	altr,sysmgr-syscon = <&sysmgr 0x48 0>;
>   	clocks = <&clkmgr N5X_EMAC1_CLK>;
> +	clock-names = "stmmaceth";
> +	status = "disabled";
>   };
>
>   &gmac2 {
> +	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
> +	reset-names = "stmmaceth", "stmmaceth-ocp";
>   	altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
>   	clocks = <&clkmgr N5X_EMAC2_CLK>;
> +	clock-names = "stmmaceth";
> +	status = "disabled";
>   };
>
>   &i2c0 {
> @@ -132,6 +145,29 @@
>   	clocks = <&clkmgr N5X_L4_MAIN_CLK>;
>   };
>
> +&socfpga_l3interconnect_firewall {
> +	coh_cpu0_bypass_OC_Firewall_main_Firewall at f7100200 {


DT node names should follow the generic naming conventions described in 
the Devicetree Specification: short, descriptive, hyphen-separated names.

These look like register block names copied verbatim from hardware 
documentation.

They should use names more like firewall at f7100200 or 
ocram-firewall at f7100200.

Also, the mixed case in OC_Firewall_main_Firewall violates DT naming 
conventions.


> +		reg = <0xf7100200 0x00000014>;
> +		intel,offset-settings =
> +			/* Disable ocram security at CCU for non secure access */
> +			<0x0000004 0x8000ffff 0xe007ffff>,
> +			<0x0000008 0x8000ffff 0xe007ffff>,
> +			<0x000000c 0x8000ffff 0xe007ffff>,
> +			<0x0000010 0x8000ffff 0xe007ffff>;
> +		bootph-all;
> +	};
> +
> +	soc_noc_fw_mpfe_csr_inst_0_mpfe_scr at f8020000 {
> +		reg = <0xf8020000 0x0000001c>;
> +		intel,offset-settings =
> +			/* Disable MPFE firewall for SMMU */
> +			<0x00000000 0x00010101 0x00010101>,
> +			/* Disable MPFE firewall for HMC adapter */
> +			<0x00000004 0x00000001 0x00010101>;
> +		bootph-all;
> +	};
> +};
> +
>   &sysmgr {
>   	compatible = "altr,sys-mgr", "syscon";
>   	bootph-all;
> diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> index 840537c9d0b..bc2fb91dfb5 100644
> --- a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
> @@ -55,6 +55,7 @@
>   };
>
>   &qspi {
> +	/delete-property/ clocks;
>   	status = "okay";
>   };
>
> diff --git a/arch/arm/dts/socfpga_n5x_socdk.dts b/arch/arm/dts/socfpga_n5x_socdk.dts
> index 915b8f6380e..fe5462aff43 100644
> --- a/arch/arm/dts/socfpga_n5x_socdk.dts
> +++ b/arch/arm/dts/socfpga_n5x_socdk.dts
> @@ -24,7 +24,7 @@
>   		reg = <0 0 0 0>;
>   	};
>
> -	soc {
> +	soc at 0 {
>   		clocks {
>   			osc1 {
>   				clock-frequency = <25000000>;
> --
> 2.19.0


Best regards,

Tien Fong