[GIT PULL] AMD/Xilinx changes for 2026-07-rc1 v3

[Michal Simek]

Hi Tom,

please pull these patches to your tree. The biggest part is new pcie driver for 
Versal Gen 2 SOC. Others are small fixes and adjustments.

Thanks,
Michal

The following changes since commit e973fa5115e40f93bb1425db5b1cc1f3d9b8047d:

   cli: flush stdin before enabling cli (2026-04-22 14:23:49 -0600)

are available in the Git repository at:

   https://source.denx.de/u-boot/custodians/u-boot-microblaze.git 
tags/xilinx-for-v2026.07-rc1-v3

for you to fetch changes up to 9e0511261221b63458bc0d4cfd08596f5c8840d4:

   net: zynq_gem: Clear stale speed bits in NWCFG before setting new ones 
(2026-04-23 11:52:18 +0200)

----------------------------------------------------------------
AMD/Xilinx/FPGA changes for v2026.07-rc1 v3

versal2:
- Wire PCIe IP

cmd/fpga:
- Fix loadb help text guarding
- Add support for skipping fpga ID check

zynqmp:
- Describe missing devices/IDs
- Fix issue around zu63dr_SE

clk/versal:
- Fix out-of-bounds parent id for DUMMY_PARENT

net/gem:
- Add support for 10GBE
- Clear stale speed bits in NWCFG

net/axi_emac:
- Filter out broadcast and multicast packets

pci:
- Add driver for AMD PCIe IP based on DesignWare core

----------------------------------------------------------------
Michal Simek (5):
       net: xilinx: Reject broadcast and multicast packets in AXI Ethernet MAC
       soc: xilinx: zynqmp: Add support for new ZynqMP devices
       board: xilinx: zynqmp: Register alternate FPGA device for zu63dr_SE
       cmd: fpga: Fix wrong preprocessor guard for loadb help text
       fpga: xilinx: Add option to skip bitstream ID check

Padmarao Begari (1):
       clk: versal: Fix out-of-bounds parent id for DUMMY_PARENT

Pranav Sanwal (3):
       pci: Add AMD Versal2 DW PCIe host controller driver
       arm: versal2: Map PCIe DBI and config regions when PCIe is enabled
       amd: versal2: Enable PCIe/NVMe support and add NVMe boot target

Pranav Tilak (3):
       net: zynq_gem: add SPEED_10000 case in clock rate selection
       net: zynq_gem: set 128-bit AXI bus width for 10GBE
       net: zynq_gem: reinitialize RX BDs on every init

Rafał Hibner (1):
       net: zynq_gem: Clear stale speed bits in NWCFG before setting new ones

  MAINTAINERS                        |   5 +
  arch/arm/mach-versal2/cpu.c        |  18 +-
  board/xilinx/zynqmp/zynqmp.c       |  17 ++
  cmd/fpga.c                         |   2 +-
  configs/amd_versal2_virt_defconfig |   6 +
  drivers/clk/clk_versal.c           |   1 +
  drivers/fpga/xilinx.c              |   7 +-
  drivers/net/xilinx_axi_emac.c      |  20 +-
  drivers/net/zynq_gem.c             |  61 +++--
  drivers/pci/Kconfig                |  11 +
  drivers/pci/Makefile               |   1 +
  drivers/pci/pcie_dw_amd.c          | 250 ++++++++++++++++++++
  drivers/soc/soc_xilinx_zynqmp.c    |  45 ++++
  include/configs/amd_versal2.h      |   9 +-
  14 files changed, 425 insertions(+), 28 deletions(-)
  create mode 100644 drivers/pci/pcie_dw_amd.c

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs
TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs