[PATCH v2] arm64: renesas: Add Cortex-M33 build option to R-Car Gen5

[Marek Vasut]

On 4/25/26 6:46 PM, Kumar, Udit wrote:
> 
> 
> On 4/23/2026 4:19 AM, Marek Vasut wrote:
>> The R-Car Gen5 SoCs contains Cortex-M33, Cortex-R52 and Cortex-A720AE
>> cores. Add U-Boot build options for the Cortex-M33 core.
>>
>> Since the Cortex-M33 core is a 32bit core, select V8M and ARM64 for
>> RCAR64 accordingly. Select TMU timer on the 32bit core, where it is
>> used instead of the ARMv8 timer. Adjust TMU timer base address to match
>> the address map of the Cortex-M33 core.
> 
> is there any reason, you can not use core's timer ?

I don't think there is one on this particular core.

[...]

>> +# Renesas ARM SoCs R-Car Gen3/Gen4/Gen5 (64bit)
>>   config RCAR_64
>>   	bool
>> -	select ARM64
>> +	select CPU_V8M if RCAR_64_RSIP
>> +	select ARM64 if !RCAR_64_RSIP
>> +	select TMU_TIMER if RCAR_64_RSIP
> 
> You can selecting TMU_TIMER, if this is M core, and later TMU_BASE is
> defined for A core, as well or I am missing something.

That TMU timer is accessible from both CA and CM cores, it is at 
different addresses for either core.

[...]

>> +++ b/arch/arm/mach-renesas/Kconfig.rcar5
>> @@ -1,5 +1,13 @@
>>   if RCAR_GEN5
>>   
>> +config RCAR_64_RSIP
>> +	bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)"
> 
> Sorry but what is RSIP means here

Renesas Secure IP, but for the purpose of U-Boot, it is a Cortex-M33 .

>> +	select SKIP_RELOCATE_CODE
>> +	select TMU_TIMER
> 
> TMU_TIMER is selected here, then you can consider to drop
> select TMU_TIMER if RCAR_64_RSIP, in little above of this patch

Good point.

>> +/* Timer */
>> +#if defined(CONFIG_RCAR_64_RSIP)
>> +#define CFG_SYS_TIMER_COUNTER		(TMU_BASE + 0xc)	/* TCNT0 */
>> +#define CFG_SYS_TIMER_RATE		(133333333 / 4)
> 
> Please check for alignment
What kind of alignment ? Details please ?