[PATCH v1 7/9] clk: s10: Refactor S10 clock driver

[YUSLAIMI, ALIF ZAKUAN]

Hi Tien Fong,

On 21/4/2026 5:30 pm, Chee, Tien Fong wrote:
> Hi Alif,
> 
> 
> On 3/4/2026 10:25 am, alif.zakuan.yuslaimi at altera.com wrote:
>> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>>
>> Refactor Stratix10 clock manager driver to support driver model, 
>> following
>> Agilex clock driver.
>>
>> Create a new clock driver, clk-s10.c, for Stratix10 which supports the
>> driver model. This allows several APIs such as enable/disable clock, and
>> get clock rate to be supported.
>>
>> This driver will be initialized during SPL to bring up the clock as early
>> as possible. The clock initialization process are refactored into this 
>> new
>> driver from clock_manager_s10.c during clock driver probe.
>>
>> Excluding Stratix10 from legacy method of obtaining clkmgr base 
>> address in
>> mach-socfpga/misc.c as the base address is already obtained during clock
>> driver probe during SPL initialization.
>>
>> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>> ---
>>   MAINTAINERS                                   |   1 +
>>   arch/arm/mach-socfpga/Kconfig                 |   2 +
>>   arch/arm/mach-socfpga/clock_manager_s10.c     | 449 ++-----------
>>   .../include/mach/clock_manager_s10.h          | 176 +-----
>>   arch/arm/mach-socfpga/misc.c                  |   3 +-
>>   arch/arm/mach-socfpga/spl_s10.c               |   7 +-
>>   drivers/clk/altera/Makefile                   |   1 +
>>   drivers/clk/altera/clk-s10.c                  | 591 ++++++++++++++++++
>>   drivers/clk/altera/clk-s10.h                  | 202 ++++++
>>   9 files changed, 861 insertions(+), 571 deletions(-)
>>   create mode 100644 drivers/clk/altera/clk-s10.c
>>   create mode 100644 drivers/clk/altera/clk-s10.h
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c58d8f85e33..863e0b763d8 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -159,6 +159,7 @@ F:    arch/arm/mach-socfpga/
>>   F:    board/altera/stratix10-socdk/
>>   F:    board/intel/agilex-socdk/
>>   F:    configs/socfpga_*
>> +F:    drivers/clk/altera/
>>   F:    drivers/ddr/altera/
>>   F:    drivers/power/domain/altr-pmgr-agilex5.c
>>   F:    drivers/sysreset/sysreset_socfpga*
>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/ 
>> Kconfig
>> index aec0fb7b1c8..c7ecdc4055f 100644
>> --- a/arch/arm/mach-socfpga/Kconfig
>> +++ b/arch/arm/mach-socfpga/Kconfig
>> @@ -149,8 +149,10 @@ config ARCH_SOCFPGA_STRATIX10
>>       select ARMV8_MULTIENTRY
>>       select ARMV8_SET_SMPEN
>>       select BINMAN if SPL_ATF
>> +    select CLK
>>       select FPGA_INTEL_SDM_MAILBOX
>>       select GICV2
>> +    select SPL_CLK if SPL
>>       select ARCH_SOCFPGA_SOC64
>> [...]
> 
>> diff --git a/drivers/clk/altera/clk-s10.h b/drivers/clk/altera/clk-s10.h
>> new file mode 100644
>> index 00000000000..f5be1e68500
>> --- /dev/null
>> +++ b/drivers/clk/altera/clk-s10.h
>> @@ -0,0 +1,202 @@
>> +/* SPDX-License-Identifier: GPL-2.0
>> + *
>> + * Copyright (C) 2026 Altera Corporation <www.altera.com>
>> + *
>> + */
>> +
>> +#ifndef    _CLK_S10_
>> +#define    _CLK_S10_
>> +
>> +#ifndef __ASSEMBLY__
>> +#include <linux/bitops.h>
>> +#endif
>> +
>> +#define COUNTER_FREQUENCY_REAL    400000000
> 
> 
> COUNTER_FREQUENCY_REAL 400000000 defined in clk-s10.h but never 
> referenced in clk-s10.c.
> 
> Example: https://github.com/u-boot/u-boot/blob/ 
> e3405917a1806971d9e72a94186b299f05581e1a/drivers/clk/altera/clk- 
> agilex.c#L357
> 
> 
> Best regards,
> 
> Tien Fong
> 
Sure, I will implement this in Stratix10 clock driver as well, I will 
include this in v2 submission after testing this.

Thanks,
Alif