[PATCH v2 1/3] arm: socfpga: Consolidate dram_bank_mmu_setup()

[Sune Brian]

On Tue, Apr 28, 2026 at 11:32 AM <alif.zakuan.yuslaimi at altera.com> wrote:
>
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> Relocate the dram_bank_mmu_setup() implementation from misc_arria10.c to
> the common socfpga misc.c and update the function to correctly handle both
> pre-relocation and post-relocation cases for DRAM cache enabling for
> consistent MMU/dcache setup across Arria10 and CycloneV platforms.
>
> These changes help to improve maintainability and consistency of DRAM
> initialization as well as MMU configuration for Arria10 and CycloneV
> platforms.
>
> New Kconfig is introduced to enable this implementation only on the default
> Arria10 and CycloneV boards as this will increase the SPL size which
> will exceed some Gen5 devices' SPL size limit.
>
> Fixes: e26ecebc684b ("socfpga: arria10: Allow dcache_enable before relocation")
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> ---

For GEN5 cyclone V:
Custom board
512x16 DDR3 die x 3
ECC supported to max Cyclone V allowed
No boot issue on soft / hard reset

log:
U-Boot SPL 2026.07-rc1-dirty (Apr 28 2026 - 13:09:08 +0800)
DDRCAL: Scrubbing ECC RAM (2048 MiB).
DDRCAL: SDRAM-ECC initialized success with 1057 ms
Trying to boot from MMC1


U-Boot 2026.07-rc1-dirty (Apr 28 2026 - 13:09:08 +0800)

Tested-by: Brian Sune <briansune at gmail.com>

>  arch/arm/mach-socfpga/Kconfig        |  1 +
>  arch/arm/mach-socfpga/misc.c         | 31 ++++++++++++++++++++++++++++

>  3 files changed, 32 insertions(+), 26 deletions(-)