[PATCH v2 2/3] ddr: altera: gen5: Add DRAM size checking

[Sune Brian]

On Tue, Apr 28, 2026 at 11:32 AM <alif.zakuan.yuslaimi at altera.com> wrote:
>
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> Add DRAM size checking compare between size from device tree and actual
> hardware.
>
> Trigger hang if DRAM size from device tree is greater than actual hardware.
> Display warning message if DRAM size mismatch between device tree and
> actual hardware.
>
> get_ram_size() uses size from device tree. So, it has consistency with
> other device families.
>
> New Kconfig is introduced to enable this implementation only on the default
> CycloneV board as this will increase the SPL size which will exceed some
> Gen5 devices' SPL size limit.
>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> ---
>  arch/arm/mach-socfpga/Kconfig   |  9 +++++++++
>  drivers/ddr/altera/sdram_gen5.c | 27 +++++++++++++++++++++++++++
>  2 files changed, 36 insertions(+)

For GEN5 cyclone V:
Custom board
512x16 DDR3 die x 3
ECC supported to max Cyclone V allowed
No boot issue on soft / hard reset

log:
U-Boot SPL 2026.07-rc1-dirty (Apr 28 2026 - 13:09:08 +0800)
DDRCAL: Scrubbing ECC RAM (2048 MiB).
DDRCAL: SDRAM-ECC initialized success with 1057 ms
Trying to boot from MMC1


U-Boot 2026.07-rc1-dirty (Apr 28 2026 - 13:09:08 +0800)

Tested-by: Brian Sune <briansune at gmail.com>