[PATCH v2 3/3] ddr: socfpga: Add ECC DRAM scrubbing support for Gen5/Arria10

[Sune Brian]

On Tue, Apr 28, 2026 at 11:32 AM <alif.zakuan.yuslaimi at altera.com> wrote:
>
> From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
>
> The SDRAM must first be rewritten by zeroes if ECC is used to initialize
> the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
> case.
>
> This implementation turns the caches on temporarily, then overwrites the
> whole RAM with zeroes, flushes the caches and turns them off again.
> This provides satisfactory performance.
>
> Move common code sdram_init_ecc_bits() to new common file sdram_soc32.c.
> Preparation for Gen5 uses the same memory initialization function as
> Arria10.
>
> New Kconfig is introduced to enable this implementation only on the default
> Arria10 and CycloneV boards as this will increase the SPL size which
> will exceed some Gen5 devices' SPL size limit.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee at altera.com>
> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
> ---

For GEN5 cyclone V:
Custom board
512x16 DDR3 die x 3
ECC supported to max Cyclone V allowed
No boot issue on soft / hard reset

log:
U-Boot SPL 2026.07-rc1-dirty (Apr 28 2026 - 13:09:08 +0800)
DDRCAL: Scrubbing ECC RAM (2048 MiB).
DDRCAL: SDRAM-ECC initialized success with 1057 ms
Trying to boot from MMC1


U-Boot 2026.07-rc1-dirty (Apr 28 2026 - 13:09:08 +0800)

Tested-by: Brian Sune <briansune at gmail.com>

>  arch/arm/mach-socfpga/Kconfig      | 13 ++++-

>  arch/arm/mach-socfpga/spl_gen5.c   | 17 ++++++
>  drivers/ddr/altera/Makefile        |  4 +-

>  drivers/ddr/altera/sdram_gen5.c    | 41 ++++++++++++--
>  drivers/ddr/altera/sdram_soc32.c   | 85 ++++++++++++++++++++++++++++++
>  drivers/ddr/altera/sdram_soc32.h   | 15 ++++++