[PATCH] arm: dts: socfpga_arria10_socdk_sdmmc: migrate to OF_UPSTREAM
dinesh.maniyam at altera.com
dinesh.maniyam at altera.com
Wed Apr 29 07:32:20 CEST 2026
From: Dinesh Maniyam <dinesh.maniyam at altera.com>
Enable CONFIG_OF_UPSTREAM for the Arria 10 SoCDK SDMMC target so that
the device tree is taken from the dts/upstream/ subtree (synchronised
from the Linux kernel) instead of the locally-maintained copy. This
keeps U-Boot in sync with Linux and avoids drift between the two trees.
Update CONFIG_DEFAULT_DEVICE_TREE to the upstream path
"intel/socfpga/socfpga_arria10_socdk_sdmmc".
Remove the now-obsolete device tree files:
- arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
- arch/arm/dts/socfpga_arria10_socdk.dtsi
and drop the corresponding entry from arch/arm/dts/Makefile.
The upstream socfpga_arria10.dtsi does not provide a label on the
"clkmgr at ffd04000" node, so reference it via its full path in
socfpga_arria10-u-boot.dtsi to keep adding the bootph-all property.
arch/arm/dts/socfpga_arria10.dtsi is intentionally kept since it is
still consumed by the Chameleon V3 / Mercury AA1 device trees which
have not yet been migrated to OF_UPSTREAM.
Build tested with socfpga_arria10_defconfig (arm-none-eabi-).
Signed-off-by: Dinesh Maniyam <dinesh.maniyam at altera.com>
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 2 +-
arch/arm/dts/socfpga_arria10_socdk.dtsi | 178 -------------------
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 27 ---
configs/socfpga_arria10_defconfig | 3 +-
5 files changed, 3 insertions(+), 208 deletions(-)
delete mode 100644 arch/arm/dts/socfpga_arria10_socdk.dtsi
delete mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 4085d4c2de1..51c5b802269 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -446,7 +446,6 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria10_chameleonv3_270_2.dtb \
socfpga_arria10_chameleonv3_270_3.dtb \
socfpga_arria10_chameleonv3_480_2.dtb \
- socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_socdk.dtb \
diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
index 2ed532ffb54..c0ce337d72e 100644
--- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -18,7 +18,7 @@
};
};
-&clkmgr {
+&{/soc/clkmgr at ffd04000} {
bootph-all;
clocks {
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
deleted file mode 100644
index 0efbeccc5cd..00000000000
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ /dev/null
@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2015 Altera Corporation <www.altera.com>
- */
-#include "socfpga_arria10.dtsi"
-
-/ {
- model = "Altera SOCFPGA Arria 10";
- compatible = "altr,socfpga-arria10", "altr,socfpga";
-
- aliases {
- ethernet0 = &gmac0;
- serial0 = &uart1;
- };
-
- chosen {
- bootargs = "earlyprintk";
- stdout-path = "serial0:115200n8";
- };
-
- memory at 0 {
- name = "memory";
- device_type = "memory";
- reg = <0x0 0x40000000>; /* 1GB */
- };
-
- a10leds {
- compatible = "gpio-leds";
-
- a10sr_led0 {
- label = "a10sr-led0";
- gpios = <&a10sr_gpio 0 1>;
- };
-
- a10sr_led1 {
- label = "a10sr-led1";
- gpios = <&a10sr_gpio 1 1>;
- };
-
- a10sr_led2 {
- label = "a10sr-led2";
- gpios = <&a10sr_gpio 2 1>;
- };
-
- a10sr_led3 {
- label = "a10sr-led3";
- gpios = <&a10sr_gpio 3 1>;
- };
- };
-
- ref_033v: 033-v-ref {
- compatible = "regulator-fixed";
- regulator-name = "0.33V";
- regulator-min-microvolt = <330000>;
- regulator-max-microvolt = <330000>;
- };
-
- soc {
- clkmgr at ffd04000 {
- clocks {
- osc1 {
- clock-frequency = <25000000>;
- };
- };
- };
- };
-};
-
-&gmac0 {
- phy-mode = "rgmii";
- phy-addr = <0xffffffff>; /* probe for phy addr */
-
- /*
- * These skews assume the user's FPGA design is adding 600ps of delay
- * for TX_CLK on Arria 10.
- *
- * All skews are offset since hardware skew values for the ksz9031
- * range from a negative skew to a positive skew.
- * See the micrel-ksz90x1.txt Documentation file for details.
- */
- txd0-skew-ps = <0>; /* -420ps */
- txd1-skew-ps = <0>; /* -420ps */
- txd2-skew-ps = <0>; /* -420ps */
- txd3-skew-ps = <0>; /* -420ps */
- rxd0-skew-ps = <420>; /* 0ps */
- rxd1-skew-ps = <420>; /* 0ps */
- rxd2-skew-ps = <420>; /* 0ps */
- rxd3-skew-ps = <420>; /* 0ps */
- txen-skew-ps = <0>; /* -420ps */
- txc-skew-ps = <1860>; /* 960ps */
- rxdv-skew-ps = <420>; /* 0ps */
- rxc-skew-ps = <1680>; /* 780ps */
- max-frame-size = <3800>;
- status = "okay";
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&spi1 {
- status = "okay";
-
- resource-manager at 0 {
- compatible = "altr,a10sr";
- reg = <0>;
- spi-max-frequency = <100000>;
- /* low-level active IRQ at GPIO1_5 */
- interrupt-parent = <&portb>;
- interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- a10sr_gpio: gpio-controller {
- compatible = "altr,a10sr-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- a10sr_rst: reset-controller {
- compatible = "altr,a10sr-reset";
- #reset-cells = <1>;
- };
- };
-};
-
-&i2c1 {
- status = "okay";
-
- /*
- * adjust the falling times to decrease the i2c frequency to 50Khz
- * because the LCD module does not work at the standard 100Khz
- */
- clock-frequency = <100000>;
- i2c-sda-falling-time-ns = <6000>;
- i2c-scl-falling-time-ns = <6000>;
-
- adc at 14 {
- compatible = "lltc,ltc2497";
- reg = <0x14>;
- vref-supply = <&ref_033v>;
- };
-
- adc at 16 {
- compatible = "lltc,ltc2497";
- reg = <0x16>;
- vref-supply = <&ref_033v>;
- };
-
- eeprom at 51 {
- compatible = "atmel,24c32";
- reg = <0x51>;
- pagesize = <32>;
- };
-
- rtc at 68 {
- compatible = "dallas,ds1339";
- reg = <0x68>;
- };
-
- ltc at 5c {
- compatible = "ltc2977";
- reg = <0x5c>;
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-&usb0 {
- status = "okay";
- disable-over-current;
-};
-
-&watchdog1 {
- status = "okay";
-};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
deleted file mode 100644
index 64dc0799f3d..00000000000
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
- */
-
-/dts-v1/;
-#include "socfpga_arria10_socdk.dtsi"
-
-&mmc {
- status = "okay";
- cap-sd-highspeed;
- cap-mmc-highspeed;
- broken-cd;
- bus-width = <4>;
-};
-
-&eccmgr {
- sdmmca-ecc at ff8c2c00 {
- compatible = "altr,socfpga-sdmmc-ecc";
- reg = <0xff8c2c00 0x400>;
- altr,ecc-parent = <&mmc>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
- <47 IRQ_TYPE_LEVEL_HIGH>,
- <16 IRQ_TYPE_LEVEL_HIGH>,
- <48 IRQ_TYPE_LEVEL_HIGH>;
- };
-};
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index b32f40ae408..17169472462 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x4400
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_DEFAULT_DEVICE_TREE="intel/socfpga/socfpga_arria10_socdk_sdmmc"
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK=0xffe2b000
CONFIG_SPL_TEXT_BASE=0xFFE00000
@@ -46,6 +46,7 @@ CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
+CONFIG_OF_UPSTREAM=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
--
2.43.7
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