[PATCH RFC next 5/5] net: SYS_RX_ETH_BUFFER defaults to 8 when CONFIG_FSL_ENETC=y

[Simon Glass]

Hi Quentin,

On 2026-04-29T10:35:00, Quentin Schulz <foss+uboot at 0leil.net> wrote:
> net: SYS_RX_ETH_BUFFER defaults to 8 when CONFIG_FSL_ENETC=y
>
> drivers/net/fsl_enetc.h specifies ENETC_BD_CNT "buffer descriptors count
> must be a multiple of 8". This constant is set to
> CONFIG_SYS_RX_ETH_BUFFER which defaults to 4.
>
> All defconfigs enabling CONFIG_FSL_ENETC fortunately have it set to 8,
> according to
> ./tools/qconfig.py -l -f CONFIG_FSL_ENETC '~CONFIG_SYS_RX_ETH_BUFFER=8'.
>
> Let's make sure the default is sane by having it set to 8 when this
> driver is enabled. Note that originally[1] it was said EEPRO100 and 405
> EMAC should be 8 or higher. 405 (PPC405?) support seems to have been
> dropped in commit b5e7c84f72ee ("ppc4xx: remove ASH405 board"), 11 years
> ago. Maybe there's something we can do for EEPRO100 though?
>
> [1] commit 53cf9435ccf9 ("- CFG_RX_ETH_BUFFER added.")
> Signed-off-by: Quentin Schulz <quentin.schulz at cherry.de>
>
> net/Kconfig | 1 +
>  1 file changed, 1 insertion(+)

> diff --git a/net/Kconfig b/net/Kconfig
> @@ -250,6 +250,7 @@ if NET
>
>  config SYS_RX_ETH_BUFFER
>          int "Number of receive packet buffers"
> +     default 8 if FSL_ENETC
>          default 4

Maybe convert the spaces here to tab?

Also suggest a note in the help text mentioning that FSL_ENETC needs
ENETC_BD_CNT to be a multiple of 8.

Reviewed-by: Simon Glass <sjg at chromium.org>

Regards,
Simon