[PATCH v2] arm: socfpga: soc64: separate reset manager into common and platform-family parts
Chee, Tien Fong
tien.fong.chee at altera.com
Thu Apr 30 06:32:30 CEST 2026
On 15/4/2026 11:04 am, Chen Huei Lok wrote:
> The SoCFPGA SoC64 reset manager code is currently built as
> reset_manager_s10.o even though it is shared across multiple SoC64
> families.
>
> Split the implementation into:
> - reset_manager_soc64.o for common SoC64 logic
> - reset_manager_soc64_families.o for platform-family-specific
> code
>
> This improves code organization and prepares the reset manager for
> additional SoC64 platform families. No functional change intended.
>
> Signed-off-by: Chen Huei Lok <chen.huei.lok at altera.com>
> ---
> arch/arm/mach-socfpga/Makefile | 15 ++--
> arch/arm/mach-socfpga/reset_manager_soc64.c | 80 ++++++++++++++++++
> ...r_s10.c => reset_manager_soc64_families.c} | 81 +------------------
> 3 files changed, 92 insertions(+), 84 deletions(-)
> create mode 100644 arch/arm/mach-socfpga/reset_manager_soc64.c
> rename arch/arm/mach-socfpga/{reset_manager_s10.c => reset_manager_soc64_families.c} (76%)
>
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
> index b6f35ddacc4..ee0ae6a6131 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -34,7 +34,8 @@ obj-y += lowlevel_init_soc64.o
> obj-y += mailbox_s10.o
> obj-y += misc_soc64.o
> obj-y += mmu-arm64_s10.o
> -obj-y += reset_manager_s10.o
> +obj-y += reset_manager_soc64.o
> +obj-y += reset_manager_soc64_families.o
> obj-y += system_manager_soc64.o
> obj-y += timer_s10.o
> obj-y += wrap_handoff_soc64.o
> @@ -47,7 +48,8 @@ obj-y += lowlevel_init_soc64.o
> obj-y += mailbox_s10.o
> obj-y += misc_soc64.o
> obj-y += mmu-arm64_s10.o
> -obj-y += reset_manager_s10.o
> +obj-y += reset_manager_soc64.o
> +obj-y += reset_manager_soc64_families.o
> obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
> obj-y += system_manager_soc64.o
> obj-y += timer_s10.o
> @@ -62,7 +64,8 @@ obj-y += clock_manager_agilex5.o
> obj-y += mailbox_s10.o
> obj-y += misc_soc64.o
> obj-y += mmu-arm64_s10.o
> -obj-y += reset_manager_s10.o
> +obj-y += reset_manager_soc64.o
> +obj-y += reset_manager_soc64_families.o
> obj-y += wrap_handoff_soc64.o
> obj-y += wrap_pll_config_soc64.o
> obj-y += altera-sysmgr.o
> @@ -79,7 +82,8 @@ obj-y += lowlevel_init_soc64.o
> obj-y += mailbox_s10.o
> obj-y += misc_soc64.o
> obj-y += mmu-arm64_s10.o
> -obj-y += reset_manager_s10.o
> +obj-y += reset_manager_soc64.o
> +obj-y += reset_manager_soc64_families.o
> obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
> obj-y += system_manager_soc64.o
> obj-y += timer_s10.o
> @@ -95,7 +99,8 @@ obj-y += lowlevel_init_soc64.o
> obj-y += mailbox_s10.o
> obj-y += misc_soc64.o
> obj-y += mmu-arm64_s10.o
> -obj-y += reset_manager_s10.o
> +obj-y += reset_manager_soc64.o
> +obj-y += reset_manager_soc64_families.o
> obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
> obj-y += system_manager_soc64.o
> obj-y += timer_s10.o
> diff --git a/arch/arm/mach-socfpga/reset_manager_soc64.c b/arch/arm/mach-socfpga/reset_manager_soc64.c
> new file mode 100644
> index 00000000000..9b28a34beb2
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/reset_manager_soc64.c
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
> + * Copyright (C) 2025 Altera Corporation <www.altera.com>
> + *
> + */
> +
> +#include <asm/io.h>
> +#include <asm/arch/reset_manager.h>
> +
> +/* Assert or de-assert SoCFPGA reset manager reset. */
> +void socfpga_per_reset(u32 reset, int set)
> +{
> + unsigned long reg;
> +
> + if (RSTMGR_BANK(reset) == 0)
> + reg = RSTMGR_SOC64_MPUMODRST;
> + else if (RSTMGR_BANK(reset) == 1)
> + reg = RSTMGR_SOC64_PER0MODRST;
> + else if (RSTMGR_BANK(reset) == 2)
> + reg = RSTMGR_SOC64_PER1MODRST;
> + else if (RSTMGR_BANK(reset) == 3)
> + reg = RSTMGR_SOC64_BRGMODRST;
> + else /* Invalid reset register, do nothing */
> + return;
> +
> + if (set)
> + setbits_le32(socfpga_get_rstmgr_addr() + reg,
> + 1 << RSTMGR_RESET(reset));
> + else
> + clrbits_le32(socfpga_get_rstmgr_addr() + reg,
> + 1 << RSTMGR_RESET(reset));
> +}
> +
> +/*
> + * Assert reset on every peripheral but L4WD0.
> + * Watchdog must be kept intact to prevent glitches
> + * and/or hangs.
> + */
> +void socfpga_per_reset_all(void)
> +{
> + const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
> +
> + /* disable all except OCP and l4wd0. OCP disable later */
> + writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
> + socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
> + writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
> + writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
> +}
> +
> +/*
> + * Return non-zero if the CPU has been warm reset
> + */
> +int cpu_has_been_warmreset(void)
> +{
> + return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
> + RSTMGR_L4WD_MPU_WARMRESET_MASK;
> +}
> +
> +void print_reset_info(void)
> +{
> + bool iswd;
> + int n;
> + u32 stat = cpu_has_been_warmreset();
> +
> + printf("Reset state: %s%s", stat ? "Warm " : "Cold",
> + (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
> +
> + stat &= ~RSTMGR_STAT_SDMWARMRST;
> + if (!stat) {
> + puts("\n");
> + return;
> + }
> +
> + n = generic_ffs(stat) - 1;
> + iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
> + printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
> + iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
> + (n - RSTMGR_STAT_MPU0RST_BITPOS));
> +}
> diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_soc64_families.c
> similarity index 76%
> rename from arch/arm/mach-socfpga/reset_manager_s10.c
> rename to arch/arm/mach-socfpga/reset_manager_soc64_families.c
> index b2b4077fd4b..b60e1a82bcf 100644
> --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_soc64_families.c
> @@ -5,17 +5,11 @@
> *
> */
>
> -#include <errno.h>
> -#include <hang.h>
> #include <asm/io.h>
> -#include <asm/secure.h>
> +#include <asm/arch/base_addr_soc64.h>
> #include <asm/arch/reset_manager.h>
> #include <asm/arch/smc_api.h>
> #include <asm/arch/system_manager.h>
> -#include <asm/arch/timer.h>
> -#include <dt-bindings/reset/altr,rst-mgr-s10.h>
> -#include <exports.h>
> -#include <linux/iopoll.h>
> #include <linux/intel-smc.h>
> #include <wait_bit.h>
>
> @@ -26,46 +20,6 @@
> #define F2SDRAM_SIDEBAND_FLAGOUTSET0 0x50
> #define F2SDRAM_SIDEBAND_FLAGOUTCLR0 0x54
>
> -/* Assert or de-assert SoCFPGA reset manager reset. */
> -void socfpga_per_reset(u32 reset, int set)
> -{
> - unsigned long reg;
> -
> - if (RSTMGR_BANK(reset) == 0)
> - reg = RSTMGR_SOC64_MPUMODRST;
> - else if (RSTMGR_BANK(reset) == 1)
> - reg = RSTMGR_SOC64_PER0MODRST;
> - else if (RSTMGR_BANK(reset) == 2)
> - reg = RSTMGR_SOC64_PER1MODRST;
> - else if (RSTMGR_BANK(reset) == 3)
> - reg = RSTMGR_SOC64_BRGMODRST;
> - else /* Invalid reset register, do nothing */
> - return;
> -
> - if (set)
> - setbits_le32(socfpga_get_rstmgr_addr() + reg,
> - 1 << RSTMGR_RESET(reset));
> - else
> - clrbits_le32(socfpga_get_rstmgr_addr() + reg,
> - 1 << RSTMGR_RESET(reset));
> -}
> -
> -/*
> - * Assert reset on every peripheral but L4WD0.
> - * Watchdog must be kept intact to prevent glitches
> - * and/or hangs.
> - */
> -void socfpga_per_reset_all(void)
> -{
> - const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
> -
> - /* disable all except OCP and l4wd0. OCP disable later */
> - writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
> - socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
> - writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
> - writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
> -}
> -
> static void socfpga_f2s_bridges_reset(int enable, unsigned int mask)
> {
> int ret;
> @@ -268,40 +222,9 @@ void socfpga_bridges_reset(int enable, unsigned int mask)
> ARRAY_SIZE(arg), NULL, 0);
> if (ret)
> printf("Failed to %s the HPS bridges, check bridges availability. Status %d.\n",
> - enable ? "enable" : "disable", ret);
> + enable ? "enable" : "disable", ret);
> } else {
> socfpga_s2f_bridges_reset(enable, mask);
> socfpga_f2s_bridges_reset(enable, mask);
> }
> }
> -
> -/*
> - * Return non-zero if the CPU has been warm reset
> - */
> -int cpu_has_been_warmreset(void)
> -{
> - return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
> - RSTMGR_L4WD_MPU_WARMRESET_MASK;
> -}
> -
> -void print_reset_info(void)
> -{
> - bool iswd;
> - int n;
> - u32 stat = cpu_has_been_warmreset();
> -
> - printf("Reset state: %s%s", stat ? "Warm " : "Cold",
> - (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
> -
> - stat &= ~RSTMGR_STAT_SDMWARMRST;
> - if (!stat) {
> - puts("\n");
> - return;
> - }
> -
> - n = generic_ffs(stat) - 1;
> - iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
> - printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
> - iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
> - (n - RSTMGR_STAT_MPU0RST_BITPOS));
> -}
Reviewed-by: Tien Fong Chee <tien.fong.chee at altera.com>
Best regards,
Tien Fong
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