[PATCH 02/10] pinctrl: nxp: imx8mp: Support print pin muxing
Peng Fan (OSS)
peng.fan at oss.nxp.com
Wed Feb 25 02:29:28 CET 2026
From: Peng Fan <peng.fan at nxp.com>
Add support for printing pin names and current mux configuration on
i.MX8MP when CMD_PINMUX is enabled.
- imx_pinctrl_pin_desc structure and PINCTRL_PIN()/IMX_PINCTRL_PIN()
helpers for defining pin descriptors.
- A full pin descriptor table for i.MX8MP pads.
- Implementation of get_pins_count(), get_pin_name(), and
get_pin_muxing() in the i.MX8M pinctrl driver.
There is no good way to add real mux names, so just dump the function ID
from the mux register.
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
drivers/pinctrl/nxp/pinctrl-imx.h | 8 +
drivers/pinctrl/nxp/pinctrl-imx8m.c | 48 ++++++
drivers/pinctrl/nxp/pinctrl-imx8mp.c | 309 +++++++++++++++++++++++++++++++++++
3 files changed, 365 insertions(+)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h
index 9adf999d3bb..569bb869abd 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx.h
+++ b/drivers/pinctrl/nxp/pinctrl-imx.h
@@ -6,6 +6,14 @@
#ifndef __DRIVERS_PINCTRL_IMX_H
#define __DRIVERS_PINCTRL_IMX_H
+#define PINCTRL_PIN(a, b) { .number = a, .name = b }
+#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+struct imx_pinctrl_pin_desc {
+ unsigned int number;
+ const char *name;
+};
+
/**
* @base: the address to the controller in virtual memory
* @input_sel_base: the address of the select input in virtual memory.
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c
index d9c63b3aca6..2835fe3b176 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8m.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c
@@ -4,7 +4,11 @@
*/
#include <dm/device.h>
+#include <dm/device_compat.h>
#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <asm/io.h>
#include "pinctrl-imx.h"
@@ -18,7 +22,51 @@ static const struct udevice_id imx8m_pinctrl_match[] = {
{ /* sentinel */ }
};
+#if CONFIG_IS_ENABLED(CMD_PINMUX)
+
+#if IS_ENABLED(CONFIG_IMX8MP)
+#include "pinctrl-imx8mp.c"
+#endif
+
+static int imx8m_get_pins_count(struct udevice *dev)
+{
+ return ARRAY_SIZE(imx8m_pinctrl_pads);
+}
+
+static const char *imx8m_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ /* sanity checking */
+ if (selector != imx8m_pinctrl_pads[selector].number) {
+ dev_err(dev,
+ "selector(%u) not match with imx8m_pinctrl_pads[selector].number(%u)\n",
+ selector, imx8m_pinctrl_pads[selector].number);
+ return NULL;
+ }
+
+ return imx8m_pinctrl_pads[selector].name;
+}
+
+static int imx8m_get_pin_muxing(struct udevice *dev, unsigned int selector,
+ char *buf, int size)
+{
+ struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+ struct imx_pinctrl_soc_info *info = priv->info;
+ u32 mux_reg = selector << 2;
+ u32 mux_mode = readl(info->base + mux_reg);
+
+ snprintf(buf, size, "Function(%d) at: 0x%p", mux_mode & 0x7, info->base + mux_reg);
+
+ return 0;
+}
+#endif
+
static const struct pinctrl_ops imx8m_pinctrl_ops = {
+#if CONFIG_IS_ENABLED(CMD_PINMUX)
+ .get_pin_name = imx8m_get_pin_name,
+ .get_pins_count = imx8m_get_pins_count,
+ .get_pin_muxing = imx8m_get_pin_muxing,
+#endif
.set_state = imx_pinctrl_set_state_mmio,
};
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mp.c b/drivers/pinctrl/nxp/pinctrl-imx8mp.c
new file mode 100644
index 00000000000..7f02eba5355
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8mp.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "pinctrl-imx.h"
+
+enum imx8mp_pads {
+ RESERVE0 = 0,
+ RESERVE1 = 1,
+ RESERVE2 = 2,
+ RESERVE3 = 3,
+ RESERVE4 = 4,
+ GPIO1_IO00 = 5,
+ GPIO1_IO01 = 6,
+ GPIO1_IO02 = 7,
+ GPIO1_IO03 = 8,
+ GPIO1_IO04 = 9,
+ GPIO1_IO05 = 10,
+ GPIO1_IO06 = 11,
+ GPIO1_IO07 = 12,
+ GPIO1_IO08 = 13,
+ GPIO1_IO09 = 14,
+ GPIO1_IO10 = 15,
+ GPIO1_IO11 = 16,
+ GPIO1_IO12 = 17,
+ GPIO1_IO13 = 18,
+ GPIO1_IO14 = 19,
+ GPIO1_IO15 = 20,
+ ENET_MDC = 21,
+ ENET_MDIO = 22,
+ ENET_TD3 = 23,
+ ENET_TD2 = 24,
+ ENET_TD1 = 25,
+ ENET_TD0 = 26,
+ ENET_TX_CTL = 27,
+ ENET_TXC = 28,
+ ENET_RX_CTL = 29,
+ ENET_RXC = 30,
+ ENET_RD0 = 31,
+ ENET_RD1 = 32,
+ ENET_RD2 = 33,
+ ENET_RD3 = 34,
+ SD1_CLK = 35,
+ SD1_CMD = 36,
+ SD1_DATA0 = 37,
+ SD1_DATA1 = 38,
+ SD1_DATA2 = 39,
+ SD1_DATA3 = 40,
+ SD1_DATA4 = 41,
+ SD1_DATA5 = 42,
+ SD1_DATA6 = 43,
+ SD1_DATA7 = 44,
+ SD1_RESET_B = 45,
+ SD1_STROBE = 46,
+ SD2_CD_B = 47,
+ SD2_CLK = 48,
+ SD2_CMD = 49,
+ SD2_DATA0 = 50,
+ SD2_DATA1 = 51,
+ SD2_DATA2 = 52,
+ SD2_DATA3 = 53,
+ SD2_RESET_B = 54,
+ SD2_WP = 55,
+ NAND_ALE = 56,
+ NAND_CE0_B = 57,
+ NAND_CE1_B = 58,
+ NAND_CE2_B = 59,
+ NAND_CE3_B = 60,
+ NAND_CLE = 61,
+ NAND_DATA00 = 62,
+ NAND_DATA01 = 63,
+ NAND_DATA02 = 64,
+ NAND_DATA03 = 65,
+ NAND_DATA04 = 66,
+ NAND_DATA05 = 67,
+ NAND_DATA06 = 68,
+ NAND_DATA07 = 69,
+ NAND_DQS = 70,
+ NAND_RE_B = 71,
+ NAND_READY_B = 72,
+ NAND_WE_B = 73,
+ NAND_WP_B = 74,
+ SAI5_RXFS = 75,
+ SAI5_RXC = 76,
+ SAI5_RXD0 = 77,
+ SAI5_RXD1 = 78,
+ SAI5_RXD2 = 79,
+ SAI5_RXD3 = 80,
+ SAI5_MCLK = 81,
+ SAI1_RXFS = 82,
+ SAI1_RXC = 83,
+ SAI1_RXD0 = 84,
+ SAI1_RXD1 = 85,
+ SAI1_RXD2 = 86,
+ SAI1_RXD3 = 87,
+ SAI1_RXD4 = 88,
+ SAI1_RXD5 = 89,
+ SAI1_RXD6 = 90,
+ SAI1_RXD7 = 91,
+ SAI1_TXFS = 92,
+ SAI1_TXC = 93,
+ SAI1_TXD0 = 94,
+ SAI1_TXD1 = 95,
+ SAI1_TXD2 = 96,
+ SAI1_TXD3 = 97,
+ SAI1_TXD4 = 98,
+ SAI1_TXD5 = 99,
+ SAI1_TXD6 = 100,
+ SAI1_TXD7 = 101,
+ SAI1_MCLK = 102,
+ SAI2_RXFS = 103,
+ SAI2_RXC = 104,
+ SAI2_RXD0 = 105,
+ SAI2_TXFS = 106,
+ SAI2_TXC = 107,
+ SAI2_TXD0 = 108,
+ SAI2_MCLK = 109,
+ SAI3_RXFS = 110,
+ SAI3_RXC = 111,
+ SAI3_RXD = 112,
+ SAI3_TXFS = 113,
+ SAI3_TXC = 114,
+ SAI3_TXD = 115,
+ SAI3_MCLK = 116,
+ SPDIF_TX = 117,
+ SPDIF_RX = 118,
+ SPDIF_EXT_CLK = 119,
+ ECSPI1_SCLK = 120,
+ ECSPI1_MOSI = 121,
+ ECSPI1_MISO = 122,
+ ECSPI1_SS0 = 123,
+ ECSPI2_SCLK = 124,
+ ECSPI2_MOSI = 125,
+ ECSPI2_MISO = 126,
+ ECSPI2_SS0 = 127,
+ I2C1_SCL = 128,
+ I2C1_SDA = 129,
+ I2C2_SCL = 130,
+ I2C2_SDA = 131,
+ I2C3_SCL = 132,
+ I2C3_SDA = 133,
+ I2C4_SCL = 134,
+ I2C4_SDA = 135,
+ UART1_RXD = 136,
+ UART1_TXD = 137,
+ UART2_RXD = 138,
+ UART2_TXD = 139,
+ UART3_RXD = 140,
+ UART3_TXD = 141,
+ UART4_RXD = 142,
+ UART4_TXD = 143,
+ HDMI_DDC_SCL = 144,
+ HDMI_DDC_SDA = 145,
+ HDMI_CEC = 146,
+ HDMI_HPD = 147,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(RESERVE0),
+ IMX_PINCTRL_PIN(RESERVE1),
+ IMX_PINCTRL_PIN(RESERVE2),
+ IMX_PINCTRL_PIN(RESERVE3),
+ IMX_PINCTRL_PIN(RESERVE4),
+ IMX_PINCTRL_PIN(GPIO1_IO00),
+ IMX_PINCTRL_PIN(GPIO1_IO01),
+ IMX_PINCTRL_PIN(GPIO1_IO02),
+ IMX_PINCTRL_PIN(GPIO1_IO03),
+ IMX_PINCTRL_PIN(GPIO1_IO04),
+ IMX_PINCTRL_PIN(GPIO1_IO05),
+ IMX_PINCTRL_PIN(GPIO1_IO06),
+ IMX_PINCTRL_PIN(GPIO1_IO07),
+ IMX_PINCTRL_PIN(GPIO1_IO08),
+ IMX_PINCTRL_PIN(GPIO1_IO09),
+ IMX_PINCTRL_PIN(GPIO1_IO10),
+ IMX_PINCTRL_PIN(GPIO1_IO11),
+ IMX_PINCTRL_PIN(GPIO1_IO12),
+ IMX_PINCTRL_PIN(GPIO1_IO13),
+ IMX_PINCTRL_PIN(GPIO1_IO14),
+ IMX_PINCTRL_PIN(GPIO1_IO15),
+ IMX_PINCTRL_PIN(ENET_MDC),
+ IMX_PINCTRL_PIN(ENET_MDIO),
+ IMX_PINCTRL_PIN(ENET_TD3),
+ IMX_PINCTRL_PIN(ENET_TD2),
+ IMX_PINCTRL_PIN(ENET_TD1),
+ IMX_PINCTRL_PIN(ENET_TD0),
+ IMX_PINCTRL_PIN(ENET_TX_CTL),
+ IMX_PINCTRL_PIN(ENET_TXC),
+ IMX_PINCTRL_PIN(ENET_RX_CTL),
+ IMX_PINCTRL_PIN(ENET_RXC),
+ IMX_PINCTRL_PIN(ENET_RD0),
+ IMX_PINCTRL_PIN(ENET_RD1),
+ IMX_PINCTRL_PIN(ENET_RD2),
+ IMX_PINCTRL_PIN(ENET_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_RESET_B),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(SD2_WP),
+ IMX_PINCTRL_PIN(NAND_ALE),
+ IMX_PINCTRL_PIN(NAND_CE0_B),
+ IMX_PINCTRL_PIN(NAND_CE1_B),
+ IMX_PINCTRL_PIN(NAND_CE2_B),
+ IMX_PINCTRL_PIN(NAND_CE3_B),
+ IMX_PINCTRL_PIN(NAND_CLE),
+ IMX_PINCTRL_PIN(NAND_DATA00),
+ IMX_PINCTRL_PIN(NAND_DATA01),
+ IMX_PINCTRL_PIN(NAND_DATA02),
+ IMX_PINCTRL_PIN(NAND_DATA03),
+ IMX_PINCTRL_PIN(NAND_DATA04),
+ IMX_PINCTRL_PIN(NAND_DATA05),
+ IMX_PINCTRL_PIN(NAND_DATA06),
+ IMX_PINCTRL_PIN(NAND_DATA07),
+ IMX_PINCTRL_PIN(NAND_DQS),
+ IMX_PINCTRL_PIN(NAND_RE_B),
+ IMX_PINCTRL_PIN(NAND_READY_B),
+ IMX_PINCTRL_PIN(NAND_WE_B),
+ IMX_PINCTRL_PIN(NAND_WP_B),
+ IMX_PINCTRL_PIN(SAI5_RXFS),
+ IMX_PINCTRL_PIN(SAI5_RXC),
+ IMX_PINCTRL_PIN(SAI5_RXD0),
+ IMX_PINCTRL_PIN(SAI5_RXD1),
+ IMX_PINCTRL_PIN(SAI5_RXD2),
+ IMX_PINCTRL_PIN(SAI5_RXD3),
+ IMX_PINCTRL_PIN(SAI5_MCLK),
+ IMX_PINCTRL_PIN(SAI1_RXFS),
+ IMX_PINCTRL_PIN(SAI1_RXC),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD1),
+ IMX_PINCTRL_PIN(SAI1_RXD2),
+ IMX_PINCTRL_PIN(SAI1_RXD3),
+ IMX_PINCTRL_PIN(SAI1_RXD4),
+ IMX_PINCTRL_PIN(SAI1_RXD5),
+ IMX_PINCTRL_PIN(SAI1_RXD6),
+ IMX_PINCTRL_PIN(SAI1_RXD7),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_TXD1),
+ IMX_PINCTRL_PIN(SAI1_TXD2),
+ IMX_PINCTRL_PIN(SAI1_TXD3),
+ IMX_PINCTRL_PIN(SAI1_TXD4),
+ IMX_PINCTRL_PIN(SAI1_TXD5),
+ IMX_PINCTRL_PIN(SAI1_TXD6),
+ IMX_PINCTRL_PIN(SAI1_TXD7),
+ IMX_PINCTRL_PIN(SAI1_MCLK),
+ IMX_PINCTRL_PIN(SAI2_RXFS),
+ IMX_PINCTRL_PIN(SAI2_RXC),
+ IMX_PINCTRL_PIN(SAI2_RXD0),
+ IMX_PINCTRL_PIN(SAI2_TXFS),
+ IMX_PINCTRL_PIN(SAI2_TXC),
+ IMX_PINCTRL_PIN(SAI2_TXD0),
+ IMX_PINCTRL_PIN(SAI2_MCLK),
+ IMX_PINCTRL_PIN(SAI3_RXFS),
+ IMX_PINCTRL_PIN(SAI3_RXC),
+ IMX_PINCTRL_PIN(SAI3_RXD),
+ IMX_PINCTRL_PIN(SAI3_TXFS),
+ IMX_PINCTRL_PIN(SAI3_TXC),
+ IMX_PINCTRL_PIN(SAI3_TXD),
+ IMX_PINCTRL_PIN(SAI3_MCLK),
+ IMX_PINCTRL_PIN(SPDIF_TX),
+ IMX_PINCTRL_PIN(SPDIF_RX),
+ IMX_PINCTRL_PIN(SPDIF_EXT_CLK),
+ IMX_PINCTRL_PIN(ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(ECSPI1_MISO),
+ IMX_PINCTRL_PIN(ECSPI1_SS0),
+ IMX_PINCTRL_PIN(ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(ECSPI2_MISO),
+ IMX_PINCTRL_PIN(ECSPI2_SS0),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(I2C3_SCL),
+ IMX_PINCTRL_PIN(I2C3_SDA),
+ IMX_PINCTRL_PIN(I2C4_SCL),
+ IMX_PINCTRL_PIN(I2C4_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(UART3_RXD),
+ IMX_PINCTRL_PIN(UART3_TXD),
+ IMX_PINCTRL_PIN(UART4_RXD),
+ IMX_PINCTRL_PIN(UART4_TXD),
+ IMX_PINCTRL_PIN(HDMI_DDC_SCL),
+ IMX_PINCTRL_PIN(HDMI_DDC_SDA),
+ IMX_PINCTRL_PIN(HDMI_CEC),
+ IMX_PINCTRL_PIN(HDMI_HPD),
+};
--
2.51.0
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