[PATCH 03/10] pinctrl: nxp: imx8mn: Support print pin muxing
Peng Fan (OSS)
peng.fan at oss.nxp.com
Wed Feb 25 02:29:29 CET 2026
From: Peng Fan <peng.fan at nxp.com>
Add support for printing pin names and current mux configuration on i.MX8MN
when CMD_PINMUX is enabled by adding full pin descriptor table for i.MX8MN
pads.
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
drivers/pinctrl/nxp/pinctrl-imx8m.c | 2 +
drivers/pinctrl/nxp/pinctrl-imx8mn.c | 310 +++++++++++++++++++++++++++++++++++
2 files changed, 312 insertions(+)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c
index 2835fe3b176..eb11edf3948 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8m.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c
@@ -26,6 +26,8 @@ static const struct udevice_id imx8m_pinctrl_match[] = {
#if IS_ENABLED(CONFIG_IMX8MP)
#include "pinctrl-imx8mp.c"
+#elif IS_ENABLED(CONFIG_IMX8MN)
+#include "pinctrl-imx8mn.c"
#endif
static int imx8m_get_pins_count(struct udevice *dev)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8mn.c b/drivers/pinctrl/nxp/pinctrl-imx8mn.c
new file mode 100644
index 00000000000..a3e22cf72ee
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx8mn.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2026 NXP
+ */
+
+#include "pinctrl-imx.h"
+
+enum imx8mn_pads {
+ RESERVE0 = 0,
+ RESERVE1 = 1,
+ RESERVE2 = 2,
+ RESERVE3 = 3,
+ RESERVE4 = 4,
+ RESERVE5 = 5,
+ RESERVE6 = 6,
+ RESERVE7 = 7,
+ BOOT_MODE2 = 8,
+ BOOT_MODE3 = 9,
+ GPIO1_IO00 = 10,
+ GPIO1_IO01 = 11,
+ GPIO1_IO02 = 12,
+ GPIO1_IO03 = 13,
+ GPIO1_IO04 = 14,
+ GPIO1_IO05 = 15,
+ GPIO1_IO06 = 16,
+ GPIO1_IO07 = 17,
+ GPIO1_IO08 = 18,
+ GPIO1_IO09 = 19,
+ GPIO1_IO10 = 20,
+ GPIO1_IO11 = 21,
+ GPIO1_IO12 = 22,
+ GPIO1_IO13 = 23,
+ GPIO1_IO14 = 24,
+ GPIO1_IO15 = 25,
+ ENET_MDC = 26,
+ ENET_MDIO = 27,
+ ENET_TD3 = 28,
+ ENET_TD2 = 29,
+ ENET_TD1 = 30,
+ ENET_TD0 = 31,
+ ENET_TX_CTL = 32,
+ ENET_TXC = 33,
+ ENET_RX_CTL = 34,
+ ENET_RXC = 35,
+ ENET_RD0 = 36,
+ ENET_RD1 = 37,
+ ENET_RD2 = 38,
+ ENET_RD3 = 39,
+ SD1_CLK = 40,
+ SD1_CMD = 41,
+ SD1_DATA0 = 42,
+ SD1_DATA1 = 43,
+ SD1_DATA2 = 44,
+ SD1_DATA3 = 45,
+ SD1_DATA4 = 46,
+ SD1_DATA5 = 47,
+ SD1_DATA6 = 48,
+ SD1_DATA7 = 49,
+ SD1_RESET_B = 50,
+ SD1_STROBE = 51,
+ SD2_CD_B = 52,
+ SD2_CLK = 53,
+ SD2_CMD = 54,
+ SD2_DATA0 = 55,
+ SD2_DATA1 = 56,
+ SD2_DATA2 = 57,
+ SD2_DATA3 = 58,
+ SD2_RESET_B = 59,
+ SD2_WP = 60,
+ NAND_ALE = 61,
+ NAND_CE0 = 62,
+ NAND_CE1 = 63,
+ NAND_CE2 = 64,
+ NAND_CE3 = 65,
+ NAND_CLE = 66,
+ NAND_DATA00 = 67,
+ NAND_DATA01 = 68,
+ NAND_DATA02 = 69,
+ NAND_DATA03 = 70,
+ NAND_DATA04 = 71,
+ NAND_DATA05 = 72,
+ NAND_DATA06 = 73,
+ NAND_DATA07 = 74,
+ NAND_DQS = 75,
+ NAND_RE_B = 76,
+ NAND_READY_B = 77,
+ NAND_WE_B = 78,
+ NAND_WP_B = 79,
+ SAI5_RXFS = 80,
+ SAI5_RXC = 81,
+ SAI5_RXD0 = 82,
+ SAI5_RXD1 = 83,
+ SAI5_RXD2 = 84,
+ SAI5_RXD3 = 85,
+ SAI5_MCLK = 86,
+ SAI1_RXFS = 87,
+ SAI1_RXC = 88,
+ SAI1_RXD0 = 89,
+ SAI1_RXD1 = 90,
+ SAI1_RXD2 = 91,
+ SAI1_RXD3 = 92,
+ SAI1_RXD4 = 93,
+ SAI1_RXD5 = 94,
+ SAI1_RXD6 = 95,
+ SAI1_RXD7 = 96,
+ SAI1_TXFS = 97,
+ SAI1_TXC = 98,
+ SAI1_TXD0 = 99,
+ SAI1_TXD1 = 100,
+ SAI1_TXD2 = 101,
+ SAI1_TXD3 = 102,
+ SAI1_TXD4 = 103,
+ SAI1_TXD5 = 104,
+ SAI1_TXD6 = 105,
+ SAI1_TXD7 = 106,
+ SAI1_MCLK = 107,
+ SAI2_RXFS = 108,
+ SAI2_RXC = 109,
+ SAI2_RXD0 = 110,
+ SAI2_TXFS = 111,
+ SAI2_TXC = 112,
+ SAI2_TXD0 = 113,
+ SAI2_MCLK = 114,
+ SAI3_RXFS = 115,
+ SAI3_RXC = 116,
+ SAI3_RXD = 117,
+ SAI3_TXFS = 118,
+ SAI3_TXC = 119,
+ SAI3_TXD = 120,
+ SAI3_MCLK = 121,
+ SPDIF_TX = 122,
+ SPDIF_RX = 123,
+ SPDIF_EXT_CLK = 124,
+ ECSPI1_SCLK = 125,
+ ECSPI1_MOSI = 126,
+ ECSPI1_MISO = 127,
+ ECSPI1_SS0 = 128,
+ ECSPI2_SCLK = 129,
+ ECSPI2_MOSI = 130,
+ ECSPI2_MISO = 131,
+ ECSPI2_SS0 = 132,
+ I2C1_SCL = 133,
+ I2C1_SDA = 134,
+ I2C2_SCL = 135,
+ I2C2_SDA = 136,
+ I2C3_SCL = 137,
+ I2C3_SDA = 138,
+ I2C4_SCL = 139,
+ I2C4_SDA = 140,
+ UART1_RXD = 141,
+ UART1_TXD = 142,
+ UART2_RXD = 143,
+ UART2_TXD = 144,
+ UART3_RXD = 145,
+ UART3_TXD = 146,
+ UART4_RXD = 147,
+ UART4_TXD = 148,
+};
+
+static const struct imx_pinctrl_pin_desc imx8m_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(RESERVE0),
+ IMX_PINCTRL_PIN(RESERVE1),
+ IMX_PINCTRL_PIN(RESERVE2),
+ IMX_PINCTRL_PIN(RESERVE3),
+ IMX_PINCTRL_PIN(RESERVE4),
+ IMX_PINCTRL_PIN(RESERVE5),
+ IMX_PINCTRL_PIN(RESERVE6),
+ IMX_PINCTRL_PIN(RESERVE7),
+ IMX_PINCTRL_PIN(BOOT_MODE2),
+ IMX_PINCTRL_PIN(BOOT_MODE3),
+ IMX_PINCTRL_PIN(GPIO1_IO00),
+ IMX_PINCTRL_PIN(GPIO1_IO01),
+ IMX_PINCTRL_PIN(GPIO1_IO02),
+ IMX_PINCTRL_PIN(GPIO1_IO03),
+ IMX_PINCTRL_PIN(GPIO1_IO04),
+ IMX_PINCTRL_PIN(GPIO1_IO05),
+ IMX_PINCTRL_PIN(GPIO1_IO06),
+ IMX_PINCTRL_PIN(GPIO1_IO07),
+ IMX_PINCTRL_PIN(GPIO1_IO08),
+ IMX_PINCTRL_PIN(GPIO1_IO09),
+ IMX_PINCTRL_PIN(GPIO1_IO10),
+ IMX_PINCTRL_PIN(GPIO1_IO11),
+ IMX_PINCTRL_PIN(GPIO1_IO12),
+ IMX_PINCTRL_PIN(GPIO1_IO13),
+ IMX_PINCTRL_PIN(GPIO1_IO14),
+ IMX_PINCTRL_PIN(GPIO1_IO15),
+ IMX_PINCTRL_PIN(ENET_MDC),
+ IMX_PINCTRL_PIN(ENET_MDIO),
+ IMX_PINCTRL_PIN(ENET_TD3),
+ IMX_PINCTRL_PIN(ENET_TD2),
+ IMX_PINCTRL_PIN(ENET_TD1),
+ IMX_PINCTRL_PIN(ENET_TD0),
+ IMX_PINCTRL_PIN(ENET_TX_CTL),
+ IMX_PINCTRL_PIN(ENET_TXC),
+ IMX_PINCTRL_PIN(ENET_RX_CTL),
+ IMX_PINCTRL_PIN(ENET_RXC),
+ IMX_PINCTRL_PIN(ENET_RD0),
+ IMX_PINCTRL_PIN(ENET_RD1),
+ IMX_PINCTRL_PIN(ENET_RD2),
+ IMX_PINCTRL_PIN(ENET_RD3),
+ IMX_PINCTRL_PIN(SD1_CLK),
+ IMX_PINCTRL_PIN(SD1_CMD),
+ IMX_PINCTRL_PIN(SD1_DATA0),
+ IMX_PINCTRL_PIN(SD1_DATA1),
+ IMX_PINCTRL_PIN(SD1_DATA2),
+ IMX_PINCTRL_PIN(SD1_DATA3),
+ IMX_PINCTRL_PIN(SD1_DATA4),
+ IMX_PINCTRL_PIN(SD1_DATA5),
+ IMX_PINCTRL_PIN(SD1_DATA6),
+ IMX_PINCTRL_PIN(SD1_DATA7),
+ IMX_PINCTRL_PIN(SD1_RESET_B),
+ IMX_PINCTRL_PIN(SD1_STROBE),
+ IMX_PINCTRL_PIN(SD2_CD_B),
+ IMX_PINCTRL_PIN(SD2_CLK),
+ IMX_PINCTRL_PIN(SD2_CMD),
+ IMX_PINCTRL_PIN(SD2_DATA0),
+ IMX_PINCTRL_PIN(SD2_DATA1),
+ IMX_PINCTRL_PIN(SD2_DATA2),
+ IMX_PINCTRL_PIN(SD2_DATA3),
+ IMX_PINCTRL_PIN(SD2_RESET_B),
+ IMX_PINCTRL_PIN(SD2_WP),
+ IMX_PINCTRL_PIN(NAND_ALE),
+ IMX_PINCTRL_PIN(NAND_CE0),
+ IMX_PINCTRL_PIN(NAND_CE1),
+ IMX_PINCTRL_PIN(NAND_CE2),
+ IMX_PINCTRL_PIN(NAND_CE3),
+ IMX_PINCTRL_PIN(NAND_CLE),
+ IMX_PINCTRL_PIN(NAND_DATA00),
+ IMX_PINCTRL_PIN(NAND_DATA01),
+ IMX_PINCTRL_PIN(NAND_DATA02),
+ IMX_PINCTRL_PIN(NAND_DATA03),
+ IMX_PINCTRL_PIN(NAND_DATA04),
+ IMX_PINCTRL_PIN(NAND_DATA05),
+ IMX_PINCTRL_PIN(NAND_DATA06),
+ IMX_PINCTRL_PIN(NAND_DATA07),
+ IMX_PINCTRL_PIN(NAND_DQS),
+ IMX_PINCTRL_PIN(NAND_RE_B),
+ IMX_PINCTRL_PIN(NAND_READY_B),
+ IMX_PINCTRL_PIN(NAND_WE_B),
+ IMX_PINCTRL_PIN(NAND_WP_B),
+ IMX_PINCTRL_PIN(SAI5_RXFS),
+ IMX_PINCTRL_PIN(SAI5_RXC),
+ IMX_PINCTRL_PIN(SAI5_RXD0),
+ IMX_PINCTRL_PIN(SAI5_RXD1),
+ IMX_PINCTRL_PIN(SAI5_RXD2),
+ IMX_PINCTRL_PIN(SAI5_RXD3),
+ IMX_PINCTRL_PIN(SAI5_MCLK),
+ IMX_PINCTRL_PIN(SAI1_RXFS),
+ IMX_PINCTRL_PIN(SAI1_RXC),
+ IMX_PINCTRL_PIN(SAI1_RXD0),
+ IMX_PINCTRL_PIN(SAI1_RXD1),
+ IMX_PINCTRL_PIN(SAI1_RXD2),
+ IMX_PINCTRL_PIN(SAI1_RXD3),
+ IMX_PINCTRL_PIN(SAI1_RXD4),
+ IMX_PINCTRL_PIN(SAI1_RXD5),
+ IMX_PINCTRL_PIN(SAI1_RXD6),
+ IMX_PINCTRL_PIN(SAI1_RXD7),
+ IMX_PINCTRL_PIN(SAI1_TXFS),
+ IMX_PINCTRL_PIN(SAI1_TXC),
+ IMX_PINCTRL_PIN(SAI1_TXD0),
+ IMX_PINCTRL_PIN(SAI1_TXD1),
+ IMX_PINCTRL_PIN(SAI1_TXD2),
+ IMX_PINCTRL_PIN(SAI1_TXD3),
+ IMX_PINCTRL_PIN(SAI1_TXD4),
+ IMX_PINCTRL_PIN(SAI1_TXD5),
+ IMX_PINCTRL_PIN(SAI1_TXD6),
+ IMX_PINCTRL_PIN(SAI1_TXD7),
+ IMX_PINCTRL_PIN(SAI1_MCLK),
+ IMX_PINCTRL_PIN(SAI2_RXFS),
+ IMX_PINCTRL_PIN(SAI2_RXC),
+ IMX_PINCTRL_PIN(SAI2_RXD0),
+ IMX_PINCTRL_PIN(SAI2_TXFS),
+ IMX_PINCTRL_PIN(SAI2_TXC),
+ IMX_PINCTRL_PIN(SAI2_TXD0),
+ IMX_PINCTRL_PIN(SAI2_MCLK),
+ IMX_PINCTRL_PIN(SAI3_RXFS),
+ IMX_PINCTRL_PIN(SAI3_RXC),
+ IMX_PINCTRL_PIN(SAI3_RXD),
+ IMX_PINCTRL_PIN(SAI3_TXFS),
+ IMX_PINCTRL_PIN(SAI3_TXC),
+ IMX_PINCTRL_PIN(SAI3_TXD),
+ IMX_PINCTRL_PIN(SAI3_MCLK),
+ IMX_PINCTRL_PIN(SPDIF_TX),
+ IMX_PINCTRL_PIN(SPDIF_RX),
+ IMX_PINCTRL_PIN(SPDIF_EXT_CLK),
+ IMX_PINCTRL_PIN(ECSPI1_SCLK),
+ IMX_PINCTRL_PIN(ECSPI1_MOSI),
+ IMX_PINCTRL_PIN(ECSPI1_MISO),
+ IMX_PINCTRL_PIN(ECSPI1_SS0),
+ IMX_PINCTRL_PIN(ECSPI2_SCLK),
+ IMX_PINCTRL_PIN(ECSPI2_MOSI),
+ IMX_PINCTRL_PIN(ECSPI2_MISO),
+ IMX_PINCTRL_PIN(ECSPI2_SS0),
+ IMX_PINCTRL_PIN(I2C1_SCL),
+ IMX_PINCTRL_PIN(I2C1_SDA),
+ IMX_PINCTRL_PIN(I2C2_SCL),
+ IMX_PINCTRL_PIN(I2C2_SDA),
+ IMX_PINCTRL_PIN(I2C3_SCL),
+ IMX_PINCTRL_PIN(I2C3_SDA),
+ IMX_PINCTRL_PIN(I2C4_SCL),
+ IMX_PINCTRL_PIN(I2C4_SDA),
+ IMX_PINCTRL_PIN(UART1_RXD),
+ IMX_PINCTRL_PIN(UART1_TXD),
+ IMX_PINCTRL_PIN(UART2_RXD),
+ IMX_PINCTRL_PIN(UART2_TXD),
+ IMX_PINCTRL_PIN(UART3_RXD),
+ IMX_PINCTRL_PIN(UART3_TXD),
+ IMX_PINCTRL_PIN(UART4_RXD),
+ IMX_PINCTRL_PIN(UART4_TXD),
+};
--
2.51.0
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