[PATCH 00/15] ddr: altera: n5x: add DDR retention support

[Chen Huei Lok]

This series adds DDR retention support for the Altera eASIC N5X
SoCFPGA. DDR retention keeps the DRAM contents alive across a warm or
configuration reset and skips the expensive full PHY re-calibration by
restoring previously trained calibration data from a backup in QSPI.

On a cold/POR boot the PHY is trained normally and the calibration data
is stored to the QSPI backup region. On a subsequent warm reset or FPGA
reconfiguration with the retention bit set, U-Boot validates the backup
(SHA384 over the configuration plus a CRC32 over the calibration data)
and, when it matches, replays the PHY init engine (PIE) handoff instead
of recalibrating, so the DDR contents are preserved.

The series is structured as:

  - fs_loader: QSPI RAW partition loading, used to fetch the backup
    calibration data from flash (patch 1).
  - N5X device tree and defconfig plumbing: fs-loader node, calibration
    offsets, and the SHA384/SHA512/FS_LOADER/SPL-env configs required by
    the retention path (patches 2 and 5).
  - QSPI mailbox handoff before DDR init so the controller is ready when
    retention reads the backup (patch 3).
  - Core self-refresh / calibration-backup support in sdram_n5x.c
    (patch 4), plus robustness fixes: watchdog progress bit, double-bit
    ECC re-init, init-hang recovery, error handling and logging cleanups
    (patches 6-13).
  - mem-clk handoff change detection (patch 14) and PHY init engine
    replay on retention restore (patch 15).

Tested-on: Intel SoCFPGA N5X SoCDK hardware.

Note: This series depends on the N5X boot support series "socfpga: n5x:
Update Boot Support for N5X" by Chen Huei Lok. Please apply that series
before this one. See the latest version at:
https://patchwork.ozlabs.org/project/uboot/cover/20260623020221.32362-1-chen.huei.lok@altera.com/

Chen Huei Lok (7):
  arm: dts: socfpga: n5x: add DDR retention calibration backup nodes
  arm: socfpga: n5x: enable QSPI mailbox before DDR init
  configs: socfpga: n5x: enable required configs for DDR retention
  ddr: altera: n5x: rename is_ddr_init_skipped() and quieten reset log
  ddr: altera: n5x: drop always-false unsigned less-than-zero checks
  ddr: altera: n5x: reconfigure DDR when mem-clk handoff changes
  ddr: altera: n5x: Replay PIE handoff on DDR retention restore

Tien Fong Chee (8):
  misc: fs_loader: Add QSPI RAW partition loading support
  ddr: altera: n5x: Add self-refresh support in DDR4
  ddr: altera: n5x: set DDR init progress bit for watchdog recovery
  ddr: altera: n5x: re-init DDR when double-bit ECC error is detected
  ddr: altera: n5x: re-init DDR after watchdog reset from init hang
  ddr: altera: n5x: return error on invalid DDR controller type
  ddr: altera: n5x: use correct cast for reset status register read
  ddr: altera: n5x: fix debug log typo

 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi    |   13 +
 .../mach-socfpga/include/mach/handoff_soc64.h |    1 +
 .../include/mach/system_manager_soc64.h       |    3 +-
 arch/arm/mach-socfpga/spl_n5x.c               |    8 +-
 arch/arm/mach-socfpga/wrap_handoff_soc64.c    |    8 +-
 configs/socfpga_n5x_defconfig                 |    5 +-
 doc/device-tree-bindings/misc/fs_loader.txt   |    8 +
 drivers/ddr/altera/sdram_n5x.c                | 1051 +++++++++++++++--
 drivers/misc/fs_loader.c                      |   79 +-
 include/fs_loader.h                           |   31 +
 10 files changed, 1057 insertions(+), 150 deletions(-)

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2.43.7