[PATCH 02/15] arm: dts: socfpga: n5x: add DDR retention calibration backup nodes

[Chen Huei Lok]

Add the device tree nodes that the N5X DDR retention restore path depends
on. Reintroduce the fs-loader node and the &sdr DDR calibration backup
properties (firmware-loader, intel,ddrcal-qspi-offset and
intel,ddrcal-ddr-offset) that were dropped during the switch to the
upstream Linux DT config. These describe where the backup calibration
data is stored and the firmware-loader instance used to read it back in
SPL.

Use bootph-all in place of the legacy u-boot,dm-pre-reloc so the nodes
are bound in the pre-relocation SPL phase on the migrated device tree.

Signed-off-by: Tien Fong Chee <tien.fong.chee at altera.com>
Signed-off-by: Chen Huei Lok <chen.huei.lok at altera.com>
---
 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
index 1bed87c1231..6f7d6d6b188 100644
--- a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
@@ -8,6 +8,12 @@
 #include "socfpga_n5x-u-boot.dtsi"
 
 /{
+	fs_loader0: fs-loader {
+		bootph-all;
+		compatible = "u-boot,fs-loader";
+		sfconfig = <0 0>;
+	};
+
 	chosen {
 		u-boot,spl-boot-order = &mmc;
 	};
@@ -36,6 +42,13 @@
 	};
 };
 
+&sdr {
+	intel,ddrcal-qspi-offset = "0x7000000";
+	intel,ddrcal-ddr-offset = "0x100000";
+	firmware-loader = <&fs_loader0>;
+	bootph-all;
+};
+
 &flash0 {
 	bootph-all;
 	cdns,page-size = <256>;
-- 
2.43.7