[PATCH 03/15] arm: socfpga: n5x: enable QSPI mailbox before DDR init

[Chen Huei Lok]

Move the mbox_qspi_open() call ahead of DRAM initialization so the QSPI
controller is handed over to the HPS and its reference clock is
configured before the DDR retention path reads the calibration backup
from QSPI during DDR init.

Signed-off-by: Chen Huei Lok <chen.huei.lok at altera.com>
---
 arch/arm/mach-socfpga/spl_n5x.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c
index 8b03d047f33..0810aed6597 100644
--- a/arch/arm/mach-socfpga/spl_n5x.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -104,6 +104,10 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 
+#ifdef CONFIG_CADENCE_QSPI
+	mbox_qspi_open();
+#endif
+
 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 	if (ret) {
@@ -111,8 +115,4 @@ void board_init_f(ulong dummy)
 		hang();
 	}
 #endif
-
-#ifdef CONFIG_CADENCE_QSPI
-	mbox_qspi_open();
-#endif
 }
-- 
2.43.7