[PATCH 05/15] configs: socfpga: n5x: enable required configs for DDR retention

[Chen Huei Lok]

DDR retention lets N5X skip a full DDR re-calibration across a warm reset
by reusing previously calibrated PHY data, which significantly shortens
warm reboot time. To do this the SPL must, early in boot and before DRAM
is usable, locate a known-good backup of the calibration data, verify it,
and replay it into the DDR PHY before handoff. Enable the configs that
this restore path depends on:

- CONFIG_FS_LOADER / CONFIG_SPL_FS_LOADER: the generic firmware loader is
  used by the DDR driver (request_firmware_into_buf()) to pull the backup
  calibration header and data from the QSPI/NAND RAW partition into the
  OCRAM scratch buffer (SOC64_OCRAM_PHY_BACKUP_BASE). The loader device is
  resolved through the "firmware-loader" phandle on the DDR node, falling
  back to /chosen. SPL_FS_LOADER is required because the restore runs in
  SPL, before DRAM is available.

- CONFIG_SHA384: the calibration backup is bound to the current DDR
  configuration with a SHA-384 digest (sha384_csum_wd() over the DDR
  handoff image and the mem-clk table). On store the digest is written
  into the backup header; on restore it is recomputed and compared
  (is_ddrconfig_hash_match()), so a backup that no longer matches the
  running DDR / mem-clk configuration is rejected. Enabling SHA384 selects
  the SHA-512 implementation it is built on, so CONFIG_SHA512_ALGO does
  not need to be listed explicitly.

- CONFIG_SPL_ENV_SUPPORT: the firmware loader reads its storage selection
  from the environment (storage_interface, fw_dev_part, ...), so the
  environment must be accessible in SPL for the loader to bind the backing
  flash device.

Init order and failure modes: the restore is best-effort and fully
guarded. The buffer load is bounds-checked against the HPS handoff region
(SOC64_HANDOFF_BASE) to prevent overflow, the header magic must match, a
CRC32 over the data must match, and finally the SHA-384 config hash must
match. If any check fails (missing loader, read error, bad magic, CRC or
hash mismatch) the backup is discarded and DDR falls back to a normal
full calibration, so an invalid or stale backup never corrupts bring-up.

These symbols are enabled only after the fs_loader RAW-partition support
and the N5X self-refresh / retention restore code that consume them, so
the series stays bisectable. The defconfig is kept in canonical
savedefconfig order; CONFIG_SPL_CRC32 is now selected implicitly by the
options enabled here and is therefore dropped from the explicit list.

Signed-off-by: Tien Fong Chee <tien.fong.chee at altera.com>
Signed-off-by: Chen Huei Lok <chen.huei.lok at altera.com>
---
 configs/socfpga_n5x_defconfig | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig
index 8f4723398df..4683726208e 100644
--- a/configs/socfpga_n5x_defconfig
+++ b/configs/socfpga_n5x_defconfig
@@ -42,6 +42,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
 CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000
 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000
 CONFIG_SPL_CACHE=y
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000
 CONFIG_SPL_ATF=y
@@ -71,6 +72,8 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_DW=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
 CONFIG_SYS_MMC_MAX_BLK_COUNT=256
 CONFIG_MMC_DW=y
 CONFIG_SPI_FLASH_ISSI=y
@@ -91,5 +94,5 @@ CONFIG_DESIGNWARE_WATCHDOG=y
 CONFIG_WDT=y
 # CONFIG_SPL_USE_TINY_PRINTF is not set
 CONFIG_PANIC_HANG=y
-CONFIG_SPL_CRC32=y
+CONFIG_SHA384=y
 # CONFIG_TOOLS_MKEFICAPSULE is not set
-- 
2.43.7