[PATCH v2 0/2] arch: arm: dts: socfpga: Fix SoC64 TCU SCR span and sysmgr grant masks

[Boon Khai Ng]

This series cleans up two issues in the shared SoC64 U-Boot firewall
overlay (intel,socfpga-dtreg) for Agilex7/7M and Stratix10.
Patch 1 corrects the noc_fw_tcu_tcu_scr reg span from 0x4 to 0x100 so it
matches the documented 256-byte decode window (0xFFD21400-0xFFD214FF),
updating both nodes that describe this register for consistency. This is
a device-tree correctness change; runtime behaviour is unchanged because
the dtreg driver only programs offset 0x0.

Patch 2 narrows the intel,offset-settings masks for the system manager
L3-master grant registers (EMAC0-2, NAND, SDMMC, USB0/1). The previous
wide masks (e.g. 0xffff0103) caused clrsetbits_le32() to clear unrelated
bits before setting the intended grant bit, corrupting the GMAC
configuration. This surfaced as a DomU ethernet-passthrough failure under
Xen (NETDEV watchdog TX timeouts, link flapping). Narrowing the masks to
only the intended bits fixes it.

Alif Zakuan Yuslaimi (2):
  arch: arm: dts: socfpga: Update L4_SYS Security Control Register size
  arch: arm: dts: socfpga: Update system manager core registers masking
    bits

 arch/arm/dts/socfpga_soc64_u-boot.dtsi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

-- 

Changelog 
v2:
- patch 1: also update the duplicate noc_fw_tcu_tcu_scr node under
  socfpga-l3interconnect-firewall (was only updated under
  socfpga-smmu-secure-config in v1).
- Added cover letter

v1:
Link:
https://patchwork.ozlabs.org/project/uboot/patch/
20260225032149.1342-1-boon.khai.ng at altera.com/

https://patchwork.ozlabs.org/project/uboot/patch/
20260225032149.1342-2-boon.khai.ng at altera.com/

2.43.7