[PATCH v2 1/2] arch: arm: dts: socfpga: Update L4_SYS Security Control Register size

[Boon Khai Ng]

From: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>

The noc_fw_tcu_tcu_scr register has a base address of 0xFFD21400 and an
end address of 0xFFD214FF for Agilex7/7M and Stratix10, i.e. a 256-byte
address block per the HPS address map.

This register appears in two intel,socfpga-dtreg nodes
(socfpga-l3interconnect-firewall and socfpga-smmu-secure-config). Update
the reg span from 0x4 to 0x100 in both nodes so the described decode
window matches hardware and the two nodes stay consistent.

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi at altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng at altera.com>
---
 arch/arm/dts/socfpga_soc64_u-boot.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
index ce5b37ef547..09506718d83 100644
--- a/arch/arm/dts/socfpga_soc64_u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi
@@ -109,7 +109,7 @@
 			};
 
 			noc_fw_tcu_tcu_scr at ffd21400 {
-				reg = <0xffd21400 0x00000004>;
+				reg = <0xffd21400 0x00000100>;
 				/* Disable DMA ECC security access, for SMMU use */
 				intel,offset-settings = <0x00000000 0x01010001 0x01010001>;
 				bootph-all;
@@ -132,7 +132,7 @@
 
 			/* TCU */
 			noc_fw_tcu_tcu_scr at ffd21400 {
-				reg = <0xffd21400 0x00000004>;
+				reg = <0xffd21400 0x00000100>;
 				intel,offset-settings =
 					<0x00000000 0x01010001 0x01010001>;
 				bootph-all;
-- 
2.43.7